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Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller
| Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller |
| Autore | Yanda Richard F |
| Pubbl/distr/stampa | Oxford, : Newnes |
| Descrizione fisica | 1 online resource (276 p.) |
| Disciplina | 621.39732 |
| Altri autori (Persone) |
HeynesMichael
MillerAnne K |
| Soggetto topico |
Logic circuits - Design and construction
Metal oxide semiconductors, Complementary |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-00979-2
9786611009793 0-08-047709-7 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Contents; Foreword; Acknowledgments; About the Authors; Chapter 1: IC Fabrication Overview; Section 1: Introduction; 1.1 Integrated Circuits; 1.2 The Semiconductor Industry; Section 2: Support Technologies; 2.1 Crystal Growth and Wafer Preparation; 2.2 Contamination Control; 2.3 Circuit Design and Mask Making; 2.4 Process Diagnostics and Metrology; Section 3: Integrated Circuit Fabrication; 3.1 Layering; 3.2 Patterning; 3.3 Doping; 3.4 Process Control and In-line Monitoring; Section 4: Test and Assembly; 4.1 Electrical Tests; 4.2 Die Separation; 4.3 Die Attach and Wire Bonding
4.4 Encapsulation4.5 Final Test; Section 5: Summary; Chapter 2: Support Technologies; Section 1: Introduction; Section 2: Contamination Control; 2.1 Why Control Contamination?; 2.2 Contamination Sources; 2.3 The Cleanroom; Section 3: Crystal Growth and Wafer Preparation; 3.1 Introduction; 3.2 Silicon Purification; 3.3 Czochralski Silicon Growth; 3.4 Shaping, Grinding, Cutting and Polishing; 3.5 Final Inspection and Shipping; Section 4: Circuit Design; 4.1 Introduction; 4.2 Product Definition and New Product Plan; 4.3 The Design Team; 4.4 The Design Process; 4.5 Design Verification and Tapeout Section 5: Photomask and Reticle Preparation5.1 Introduction; 5.2 Reticle Substrate Preparation; 5.3 Pattern Transfer; 5.4 Inspection and Defect Repair; Chapter 3: Forming Wells; Section 1: Introduction; Section 2: Initial Oxidation; Section 3: Photolithography; 3.1 Introduction; 3.2 Coat (Spin); 3.3 Exposure (Step); 3.4 Develop; 3.5 After Develop Inspect (ADI); Section 4: Ion Implantation; Chapter 4: Isolate Active Areas (Shallow Trench Isolation); Section 1: Introduction to Shallow Trench Isolation; Section 2: Pad Oxide Growth; Section 3: Silicon Nitride Deposition Section 4: Photolithography for Photo/EtchSection 5: Hard Mask Formation Using Plasma Etch; 5.1 Hard Mask Overview; 5.2 Plasma Etch Overview; 5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride; Section 6: Form Trenches in Silicon with Plasma Etch; Section 7: Fill Trenches with Silicon Dioxide; Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide; Section 9: Wet Etch Removal of Silicon Nitride and Pad Oxide; Chapter 5: Building the Transistors; Section 1: Introduction; Section 2: Thin Film Formation; 2.1 Gate Dielectric Oxidation 2.2 Polycrystalline Silicon (Poly) Deposition2.3 Nitride Cap Deposition; Section 3: Poly Gate Formation; 3.1 Photoresist Patterning; 3.2 Plasma Etch; Section 4: Source/Drain Formation; 4.1 Introduction; 4.2 Shallow Implant; 4.3 Spacer Formation; 4.4 High-Dose Implant; 4.5 Anneal; Section 5: Salicide Formation; 5.1 Sputter Cobalt; 5.2 RTP Reaction Forming Silicide; 5.3 Strip Residual Cobalt; 5.4 Anneal the Silicide; Chapter 6: First Level Metallization; Section 1: Introduction; Section 2: Nitride and Oxide Depositions; 2.1 Nitride Deposition; 2.2 Oxide Deposition; Section 3: CMP Planarization Section 4: Photo/Etch for Contact Holes |
| Record Nr. | UNINA-9910457087103321 |
Yanda Richard F
|
||
| Oxford, : Newnes | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller
| Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller |
| Autore | Yanda Richard F |
| Pubbl/distr/stampa | Oxford, : Newnes |
| Descrizione fisica | 1 online resource (276 p.) |
| Disciplina | 621.39732 |
| Altri autori (Persone) |
HeynesMichael
MillerAnne K |
| Soggetto topico |
Logic circuits - Design and construction
Metal oxide semiconductors, Complementary |
| ISBN |
1-281-00979-2
9786611009793 0-08-047709-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Contents; Foreword; Acknowledgments; About the Authors; Chapter 1: IC Fabrication Overview; Section 1: Introduction; 1.1 Integrated Circuits; 1.2 The Semiconductor Industry; Section 2: Support Technologies; 2.1 Crystal Growth and Wafer Preparation; 2.2 Contamination Control; 2.3 Circuit Design and Mask Making; 2.4 Process Diagnostics and Metrology; Section 3: Integrated Circuit Fabrication; 3.1 Layering; 3.2 Patterning; 3.3 Doping; 3.4 Process Control and In-line Monitoring; Section 4: Test and Assembly; 4.1 Electrical Tests; 4.2 Die Separation; 4.3 Die Attach and Wire Bonding
4.4 Encapsulation4.5 Final Test; Section 5: Summary; Chapter 2: Support Technologies; Section 1: Introduction; Section 2: Contamination Control; 2.1 Why Control Contamination?; 2.2 Contamination Sources; 2.3 The Cleanroom; Section 3: Crystal Growth and Wafer Preparation; 3.1 Introduction; 3.2 Silicon Purification; 3.3 Czochralski Silicon Growth; 3.4 Shaping, Grinding, Cutting and Polishing; 3.5 Final Inspection and Shipping; Section 4: Circuit Design; 4.1 Introduction; 4.2 Product Definition and New Product Plan; 4.3 The Design Team; 4.4 The Design Process; 4.5 Design Verification and Tapeout Section 5: Photomask and Reticle Preparation5.1 Introduction; 5.2 Reticle Substrate Preparation; 5.3 Pattern Transfer; 5.4 Inspection and Defect Repair; Chapter 3: Forming Wells; Section 1: Introduction; Section 2: Initial Oxidation; Section 3: Photolithography; 3.1 Introduction; 3.2 Coat (Spin); 3.3 Exposure (Step); 3.4 Develop; 3.5 After Develop Inspect (ADI); Section 4: Ion Implantation; Chapter 4: Isolate Active Areas (Shallow Trench Isolation); Section 1: Introduction to Shallow Trench Isolation; Section 2: Pad Oxide Growth; Section 3: Silicon Nitride Deposition Section 4: Photolithography for Photo/EtchSection 5: Hard Mask Formation Using Plasma Etch; 5.1 Hard Mask Overview; 5.2 Plasma Etch Overview; 5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride; Section 6: Form Trenches in Silicon with Plasma Etch; Section 7: Fill Trenches with Silicon Dioxide; Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide; Section 9: Wet Etch Removal of Silicon Nitride and Pad Oxide; Chapter 5: Building the Transistors; Section 1: Introduction; Section 2: Thin Film Formation; 2.1 Gate Dielectric Oxidation 2.2 Polycrystalline Silicon (Poly) Deposition2.3 Nitride Cap Deposition; Section 3: Poly Gate Formation; 3.1 Photoresist Patterning; 3.2 Plasma Etch; Section 4: Source/Drain Formation; 4.1 Introduction; 4.2 Shallow Implant; 4.3 Spacer Formation; 4.4 High-Dose Implant; 4.5 Anneal; Section 5: Salicide Formation; 5.1 Sputter Cobalt; 5.2 RTP Reaction Forming Silicide; 5.3 Strip Residual Cobalt; 5.4 Anneal the Silicide; Chapter 6: First Level Metallization; Section 1: Introduction; Section 2: Nitride and Oxide Depositions; 2.1 Nitride Deposition; 2.2 Oxide Deposition; Section 3: CMP Planarization Section 4: Photo/Etch for Contact Holes |
| Record Nr. | UNINA-9910784359603321 |
|
Yanda Richard F
|
||
| Oxford, : Newnes | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller
| Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller |
| Autore | Yanda Richard F |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Oxford, : Newnes |
| Descrizione fisica | 1 online resource (276 p.) |
| Disciplina | 621.39732 |
| Altri autori (Persone) |
HeynesMichael
MillerAnne K |
| Soggetto topico |
Logic circuits - Design and construction
Metal oxide semiconductors, Complementary |
| ISBN |
1-281-00979-2
9786611009793 0-08-047709-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Contents; Foreword; Acknowledgments; About the Authors; Chapter 1: IC Fabrication Overview; Section 1: Introduction; 1.1 Integrated Circuits; 1.2 The Semiconductor Industry; Section 2: Support Technologies; 2.1 Crystal Growth and Wafer Preparation; 2.2 Contamination Control; 2.3 Circuit Design and Mask Making; 2.4 Process Diagnostics and Metrology; Section 3: Integrated Circuit Fabrication; 3.1 Layering; 3.2 Patterning; 3.3 Doping; 3.4 Process Control and In-line Monitoring; Section 4: Test and Assembly; 4.1 Electrical Tests; 4.2 Die Separation; 4.3 Die Attach and Wire Bonding
4.4 Encapsulation4.5 Final Test; Section 5: Summary; Chapter 2: Support Technologies; Section 1: Introduction; Section 2: Contamination Control; 2.1 Why Control Contamination?; 2.2 Contamination Sources; 2.3 The Cleanroom; Section 3: Crystal Growth and Wafer Preparation; 3.1 Introduction; 3.2 Silicon Purification; 3.3 Czochralski Silicon Growth; 3.4 Shaping, Grinding, Cutting and Polishing; 3.5 Final Inspection and Shipping; Section 4: Circuit Design; 4.1 Introduction; 4.2 Product Definition and New Product Plan; 4.3 The Design Team; 4.4 The Design Process; 4.5 Design Verification and Tapeout Section 5: Photomask and Reticle Preparation5.1 Introduction; 5.2 Reticle Substrate Preparation; 5.3 Pattern Transfer; 5.4 Inspection and Defect Repair; Chapter 3: Forming Wells; Section 1: Introduction; Section 2: Initial Oxidation; Section 3: Photolithography; 3.1 Introduction; 3.2 Coat (Spin); 3.3 Exposure (Step); 3.4 Develop; 3.5 After Develop Inspect (ADI); Section 4: Ion Implantation; Chapter 4: Isolate Active Areas (Shallow Trench Isolation); Section 1: Introduction to Shallow Trench Isolation; Section 2: Pad Oxide Growth; Section 3: Silicon Nitride Deposition Section 4: Photolithography for Photo/EtchSection 5: Hard Mask Formation Using Plasma Etch; 5.1 Hard Mask Overview; 5.2 Plasma Etch Overview; 5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride; Section 6: Form Trenches in Silicon with Plasma Etch; Section 7: Fill Trenches with Silicon Dioxide; Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide; Section 9: Wet Etch Removal of Silicon Nitride and Pad Oxide; Chapter 5: Building the Transistors; Section 1: Introduction; Section 2: Thin Film Formation; 2.1 Gate Dielectric Oxidation 2.2 Polycrystalline Silicon (Poly) Deposition2.3 Nitride Cap Deposition; Section 3: Poly Gate Formation; 3.1 Photoresist Patterning; 3.2 Plasma Etch; Section 4: Source/Drain Formation; 4.1 Introduction; 4.2 Shallow Implant; 4.3 Spacer Formation; 4.4 High-Dose Implant; 4.5 Anneal; Section 5: Salicide Formation; 5.1 Sputter Cobalt; 5.2 RTP Reaction Forming Silicide; 5.3 Strip Residual Cobalt; 5.4 Anneal the Silicide; Chapter 6: First Level Metallization; Section 1: Introduction; Section 2: Nitride and Oxide Depositions; 2.1 Nitride Deposition; 2.2 Oxide Deposition; Section 3: CMP Planarization Section 4: Photo/Etch for Contact Holes |
| Record Nr. | UNINA-9910825105903321 |
|
Yanda Richard F
|
||
| Oxford, : Newnes | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||