Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
FPGA-based implementation of signal processing systems / / Roger Woods [and three others]
| FPGA-based implementation of signal processing systems / / Roger Woods [and three others] |
| Autore | Woods Roger <1963-> |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Chichester, England : , : Wiley, , 2017 |
| Descrizione fisica | 1 online resource (359 pages) : illustrations |
| Disciplina | 621.382/2 |
| Soggetto topico |
Signal processing - Digital techniques
Digital integrated circuits Field programmable gate arrays |
| ISBN |
1-119-07796-6
1-119-07923-3 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910164059703321 |
Woods Roger <1963->
|
||
| Chichester, England : , : Wiley, , 2017 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
FPGA-based implementation of signal processing systems / / Roger Woods [and three others]
| FPGA-based implementation of signal processing systems / / Roger Woods [and three others] |
| Autore | Woods Roger <1963-> |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Chichester, England : , : Wiley, , 2017 |
| Descrizione fisica | 1 online resource (359 pages) : illustrations |
| Disciplina | 621.382/2 |
| Soggetto topico |
Signal processing - Digital techniques
Digital integrated circuits Field programmable gate arrays |
| ISBN |
1-119-07796-6
1-119-07923-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910676649403321 |
|
Woods Roger <1963->
|
||
| Chichester, England : , : Wiley, , 2017 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Reconfigurable Computing: Architectures, Tools, and Applications [[electronic resource] ] : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings / / edited by Roger Woods, Katherine Compton, Christos Bourganis, Pedro C. Diniz
| Reconfigurable Computing: Architectures, Tools, and Applications [[electronic resource] ] : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings / / edited by Roger Woods, Katherine Compton, Christos Bourganis, Pedro C. Diniz |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 |
| Descrizione fisica | 1 online resource (XIV, 346 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| ISBN | 3-540-78610-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- Synthesizing FPGA Circuits from Parallel Programs -- From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing -- The von Neumann Syndrome and the CS Education Dilemma -- Programming and Compilation -- Optimal Unroll Factor for Reconfigurable Architectures -- Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems -- DNA and String Processing Applications -- DNA Physical Mapping on a Reconfigurable Platform -- Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension -- Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs -- Scientific Applications -- A Custom Processor for a TDMA Solver in a CFD Application -- A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation -- Reconfigurable Computing Hardware and Systems -- Physical Design of FPGA Interconnect to Prevent Information Leakage -- Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs -- Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems -- Image Processing -- FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor -- A Parallel Hardware Architecture for Image Feature Detection -- Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System -- Run-Time Behavior -- A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems -- A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor -- Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens -- Instruction Set Extension -- ARISE Machines: Extending Processors with Hybrid Accelerators -- The Instruction-Set Extension Problem: A Survey -- Random Number Generation and Financial Computation -- An FPGA Run-Time Parameterisable Log-Normal Random Number Generator -- Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA -- Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models -- Posters -- Hybrid-Mode Floating-Point FPGA CORDIC Co-processor -- Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard -- Creating the World’s Largest Reconfigurable Supercomputing System Based on the Scalable SGI® Altix® 4700 System Infrastructure and Benchmarking Life-Science Applications -- Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs -- A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures -- PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications -- Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip -- Efficiency of Dynamic Reconfigurable Datapath Extensions – A Case Study -- Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices -- Data Reallocation by Exploiting FPGA Configuration Mechanisms -- A Networked, Lightweight and Partially Reconfigurable Platform -- Neuromolecularware – A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis -- An FPGA Configuration Scheme for Bitstream Protection -- Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. |
| Record Nr. | UNISA-996465518003316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Reconfigurable Computing: Architectures, Tools, and Applications : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings / / edited by Roger Woods, Katherine Compton, Christos Bourganis, Pedro C. Diniz
| Reconfigurable Computing: Architectures, Tools, and Applications : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings / / edited by Roger Woods, Katherine Compton, Christos Bourganis, Pedro C. Diniz |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 |
| Descrizione fisica | 1 online resource (XIV, 346 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| ISBN | 3-540-78610-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- Synthesizing FPGA Circuits from Parallel Programs -- From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing -- The von Neumann Syndrome and the CS Education Dilemma -- Programming and Compilation -- Optimal Unroll Factor for Reconfigurable Architectures -- Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems -- DNA and String Processing Applications -- DNA Physical Mapping on a Reconfigurable Platform -- Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension -- Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs -- Scientific Applications -- A Custom Processor for a TDMA Solver in a CFD Application -- A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation -- Reconfigurable Computing Hardware and Systems -- Physical Design of FPGA Interconnect to Prevent Information Leakage -- Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs -- Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems -- Image Processing -- FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor -- A Parallel Hardware Architecture for Image Feature Detection -- Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System -- Run-Time Behavior -- A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems -- A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor -- Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens -- Instruction Set Extension -- ARISE Machines: Extending Processors with Hybrid Accelerators -- The Instruction-Set Extension Problem: A Survey -- Random Number Generation and Financial Computation -- An FPGA Run-Time Parameterisable Log-Normal Random Number Generator -- Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA -- Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models -- Posters -- Hybrid-Mode Floating-Point FPGA CORDIC Co-processor -- Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard -- Creating the World’s Largest Reconfigurable Supercomputing System Based on the Scalable SGI® Altix® 4700 System Infrastructure and Benchmarking Life-Science Applications -- Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs -- A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures -- PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications -- Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip -- Efficiency of Dynamic Reconfigurable Datapath Extensions – A Case Study -- Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices -- Data Reallocation by Exploiting FPGA Configuration Mechanisms -- A Networked, Lightweight and Partially Reconfigurable Platform -- Neuromolecularware – A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis -- An FPGA Configuration Scheme for Bitstream Protection -- Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. |
| Record Nr. | UNINA-9910485047503321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||