Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
Applied Reconfigurable Computing [[electronic resource] ] : 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings / / edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger Woods, Pedro Diniz
| Applied Reconfigurable Computing [[electronic resource] ] : 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings / / edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger Woods, Pedro Diniz |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIII, 418 p. 217 illus., 110 illus. in color.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Operating systems (Computers) Software engineering Computer systems Computers, Special purpose Artificial intelligence Computer Hardware Operating Systems Software Engineering Computer System Implementation Special Purpose and Application-Based Systems Artificial Intelligence |
| ISBN | 3-030-17227-9 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Applications -- Fault-Tolerant Architecture for On-Board Dual-Core Synthetic-Aperture Radar Imaging -- Optimizing CNN-based Hyperspectral Image Classification on FPGAs -- Supporting Columnar In-Memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow -- A Novel Encoder for TDCs -- A Resource Reduced Application-Specific FPGA Switch -- Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications -- Partial Reconfiguration and Security -- Probabilistic Performance Modelling when using Partial Reconfiguration to Accelerate Streaming Applications with Non-Deterministic Task Scheduling -- Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems -- (ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-based Countermeasures on FPGAs -- Proof-Carrying Hardware versus the Stealthy Malicious LUT Hardware Trojan -- Secure Local Configuration of Intellectual Property Without a Trusted Third Party -- Image/Video Processing -- HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing -- Real-time FPGA implementation of connected component labelling for a 4K video stream -- A Scalable FPGA-based Architecture for Depth Estimation in SLAM -- High-Level Synthesis -- Evaluating LULESH Kernels on OpenCL FPGA -- The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems -- Graph-based Code Restructuring Targeting HLS for FPGAs -- CGRAs and Vector Processing -- UltraSynth: Integration of a CGRA into a Control Engineering Environment -- Exploiting reconfigurable vector processing for energy-efficient computation in 3D-stacked memories -- Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms -- Architectures -- ReM: a Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures -- Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators -- Design Frameworks and Methodology -- Hybrid Prototyping for Manycore Design and Validation -- Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks -- Invited Talk -- Third Party CAD Tools for FPGA Design | A Survey of the Current Landscape -- Convolutional Neural Networks -- Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation -- Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs -- Faster Convolutional Neural Networks in Low Density FPGAs using Block Pruning. |
| Record Nr. | UNISA-996466302503316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Applied Reconfigurable Computing : 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings / / edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger Woods, Pedro Diniz
| Applied Reconfigurable Computing : 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings / / edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger Woods, Pedro Diniz |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIII, 418 p. 217 illus., 110 illus. in color.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Operating systems (Computers) Software engineering Computer systems Computers, Special purpose Artificial intelligence Computer Hardware Operating Systems Software Engineering Computer System Implementation Special Purpose and Application-Based Systems Artificial Intelligence |
| ISBN | 3-030-17227-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Applications -- Fault-Tolerant Architecture for On-Board Dual-Core Synthetic-Aperture Radar Imaging -- Optimizing CNN-based Hyperspectral Image Classification on FPGAs -- Supporting Columnar In-Memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow -- A Novel Encoder for TDCs -- A Resource Reduced Application-Specific FPGA Switch -- Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications -- Partial Reconfiguration and Security -- Probabilistic Performance Modelling when using Partial Reconfiguration to Accelerate Streaming Applications with Non-Deterministic Task Scheduling -- Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems -- (ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-based Countermeasures on FPGAs -- Proof-Carrying Hardware versus the Stealthy Malicious LUT Hardware Trojan -- Secure Local Configuration of Intellectual Property Without a Trusted Third Party -- Image/Video Processing -- HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing -- Real-time FPGA implementation of connected component labelling for a 4K video stream -- A Scalable FPGA-based Architecture for Depth Estimation in SLAM -- High-Level Synthesis -- Evaluating LULESH Kernels on OpenCL FPGA -- The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems -- Graph-based Code Restructuring Targeting HLS for FPGAs -- CGRAs and Vector Processing -- UltraSynth: Integration of a CGRA into a Control Engineering Environment -- Exploiting reconfigurable vector processing for energy-efficient computation in 3D-stacked memories -- Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms -- Architectures -- ReM: a Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures -- Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators -- Design Frameworks and Methodology -- Hybrid Prototyping for Manycore Design and Validation -- Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks -- Invited Talk -- Third Party CAD Tools for FPGA Design | A Survey of the Current Landscape -- Convolutional Neural Networks -- Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation -- Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs -- Faster Convolutional Neural Networks in Low Density FPGAs using Block Pruning. |
| Record Nr. | UNINA-9910337562203321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Engineering innovative products : a practical experience / / edited by Roger Woods, [and three others]
| Engineering innovative products : a practical experience / / edited by Roger Woods, [and three others] |
| Pubbl/distr/stampa | Chichester, England : , : Wiley, , 2014 |
| Descrizione fisica | 1 online resource (291 p.) |
| Disciplina | 658.5/75 |
| Soggetto topico |
New products
Marketing |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-118-75769-6
1-118-75772-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Title Page; Copyright; Contents; List of Contributors; Foreword; Preface; List of Abbreviations; Chapter 1 Introduction; 1.1 Introduction; 1.2 Importance of SMEs; 1.3 Inspiring Innovation for Engineers; 1.4 Rationale; 1.5 Focus; 1.6 Processes and Organization of Course; 1.7 Breakdown of Book Material; References; Chapter 2 Idea Generation, Filtering and Development; 2.1 Introduction; 2.2 Timeline; 2.3 Team Structure; 2.3.1 Team-Working Theory; 2.3.2 Team Roles; 2.4 Idea Generation; 2.4.1 Mentor Role; 2.4.2 Role of the Team; 2.4.3 Role of the Individual; 2.4.4 Imitation
2.5 To Filter or Not2.5.1 Already Exists; 2.5.2 Market Issues; 2.5.3 Technically Too Difficult; 2.5.4 Beyond Expertise; 2.5.5 Difficult to Pitch; 2.5.6 No Potential for Future Development; 2.6 Idea Incubation and Development; 2.7 Conclusions; References; Chapter 3 The Ideal Pitch; 3.1 Introduction; 3.2 Business Pitch; 3.2.1 CONNECT Springboard; 3.2.2 Pitch Outline; 3.3 Case Studies; 3.3.1 MVR; 3.3.2 Nutrifit; 3.3.3 Noctua; 3.4 Pain and Solution; 3.5 Value Proposition and Technology; 3.6 Market and Competition; 3.7 Company Traction and Go-to-Market Strategy; 3.8 Finance 3.9 Presentation Process3.10 Conclusions; References; Chapter 4 Creating an Effective Business Plan; 4.1 Introduction; 4.2 Business Plan; 4.2.1 Business Plan Outline; 4.2.2 Executive Summary; 4.3 Company; 4.3.1 Team; 4.3.2 Branding; 4.4 The Business; 4.4.1 Products and Services; 4.4.2 Uniqueness; 4.4.3 Future Products; 4.5 Business Strategy; 4.5.1 Corporate Strategy; 4.5.2 Competitive Edge; 4.5.3 Pricing Strategy; 4.5.4 Sales Strategy; 4.6 Market; 4.6.1 Market Definition; 4.6.2 Key Market Segments; 4.6.3 Market Trends; 4.6.4 Target Market; 4.7 Competition; 4.7.1 Direct Competition 4.7.2 Indirect Competition4.7.3 How We Compare; 4.8 Market Analysis; 4.8.1 Market Growth; 4.8.2 Position; 4.8.3 Pricing; 4.8.4 Sales Strategy and Projection; 4.8.5 Distribution; 4.8.6 Advertising and Promotion; 4.9 Finances; 4.9.1 Costs; 4.9.2 Breakeven Analysis; 4.9.3 Profit and Loss Accounts; 4.9.4 Balance Sheet; 4.9.5 Performance Ratios; 4.10 Conclusions; References; Chapter 5 Brands that Connect Create Differences that Matter; 5.1 Introduction; 5.2 Why Branding Matters; 5.2.1 The Branding Evolution; 5.2.2 The Dynamics of Trust; 5.3 The Doing Part of Branding; 5.3.1 A Brilliant Idea 5.3.2 Be Useful5.3.3 Be Credible; 5.3.4 Have a Dominant Proposition; 5.3.5 Brand Check Your Idea; 5.3.6 Belief Systems Influence Behaviour; 5.4 The Secret Sauce: Tell a Great Story; 5.5 World-Beating Attitude; 5.5.1 Who Else is Out There?; 5.5.2 Do Your Homework; 5.6 Name it. Name it Good; 5.6.1 Taglines Can Make Things Simple, Not Dumb; 5.7 Brand Strategy (is Not a Dirty Word); 5.7.1 Make Sense to Your Advocates and Your Customers; 5.7.2 A Word on Industrial/Tech Branding; 5.8 A Coherent Visual Identity; 5.8.1 A Central Visual Image; 5.8.2 But What About My Logo?; 5.8.3 Brand Touchpoints 5.9 Conclusions |
| Record Nr. | UNINA-9910464831803321 |
| Chichester, England : , : Wiley, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Engineering innovative products : a practical experience / / edited by Roger Woods, [and three others]
| Engineering innovative products : a practical experience / / edited by Roger Woods, [and three others] |
| Pubbl/distr/stampa | Chichester, England : , : Wiley, , 2014 |
| Descrizione fisica | 1 online resource (291 pages) : illustrations, tables |
| Disciplina | 658.5/75 |
| Soggetto topico |
New products
Marketing |
| ISBN |
1-118-75772-6
1-118-75769-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910795814503321 |
| Chichester, England : , : Wiley, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Engineering innovative products : a practical experience / / edited by Roger Woods, [and three others]
| Engineering innovative products : a practical experience / / edited by Roger Woods, [and three others] |
| Pubbl/distr/stampa | Chichester, England : , : Wiley, , 2014 |
| Descrizione fisica | 1 online resource (291 pages) : illustrations, tables |
| Disciplina | 658.5/75 |
| Soggetto topico |
New products
Marketing |
| ISBN |
1-118-75772-6
1-118-75769-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910821170703321 |
| Chichester, England : , : Wiley, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Field-Programmable Logic and Applications [[electronic resource] ] : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings / / edited by Gordon Brebner, Roger Woods
| Field-Programmable Logic and Applications [[electronic resource] ] : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings / / edited by Gordon Brebner, Roger Woods |
| Edizione | [1st ed. 2001.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 |
| Descrizione fisica | 1 online resource (XV, 665 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Software engineering Computer communication systems Logic design Microprocessors Computer-aided engineering Computer System Implementation Software Engineering/Programming and Operating Systems Computer Communication Networks Logic Design Processor Architectures Computer-Aided Engineering (CAD, CAE) and Design |
| ISBN | 3-540-44687-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Keynote 1 -- Technology Trends and Adaptive Computing -- Architectural Frameworks -- Prototyping Framework for Reconfigurable Processors -- An Emulator for Exploring RaPiD Configurable Computing Architectures -- Place and Route 1 -- A New Placement Method for Direct Mapping into LUT-Based FPGAs -- fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits -- Architecture -- Macrocell Architectures for Product Term Embedded Memory Arrays -- Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs -- Memory Synthesis for FPGA-Based Reconfigurable Computers -- DSP 1 -- Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic -- Implementation of (Normalised) RLS Lattice on Virtex -- Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing -- Synthesis -- Static Profile-Driven Compilation for FPGAs -- Synthesizing RTL Hardware from Java Byte Codes -- PuMA++: From Behavioral Specification to Multi-FPGA-Prototype -- Encryption -- Secure Configuration of Field Programmable Gate Arrays -- Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm -- JBits™ Implementations of the Advanced Encryption Standard (Rijndael) -- Runtime Recon.guration 1 -- Task-Parallel Programming of Reconfigurable Systems -- Chip-Based Reconfigurable Task Management -- Configuration Caching and Swapping -- Graphics and Vision -- Multiple Stereo Matching Using an Extended Architecture -- Implementation of a NURBS to Bézier Conversor with Constant Latency -- Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems -- Invited Keynote 2 -- Processing Models for the Next Generation Network -- Place and Route 2 -- Tightly Integrated Placement and Routing for FPGAs -- Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays -- Networking -- Reconfigurable Router Modules Using Network Protocol Wrappers -- Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware -- Processor Interaction -- The MOLEN ??-Coded Processor -- Run-Time Optimized Reconfiguration Using Instruction Forecasting -- CRISP: A Template for Reconfigurable Instruction Set Processors -- Applications -- Evaluation of an FPGA Implementation of the Discrete Element Method -- Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers -- A Reconfigurable Embedded Input Device for Kinetically Challenged Persons -- Methodology 1 -- Bubble Partitioning for LUT-Based Sequential Circuits -- Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits -- Placing, Routing, and Editing Virtual FPGAs -- DSP 2 -- Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver -- A Music Synthesizer on FPGA -- Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders -- Loops and Systolic -- Loop Tiling for Reconfigurable Accelerators -- The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems -- A n-Bit Reconfigurable Scalar Quantiser -- Image Processing -- Real Time Morphological Image Contrast Enhancement in Virtex FPGA -- Demonstrating Real-time JPEG Image Compression-Decompression using Standard Component IP Cores on a Programmable Logic based Platform for DSP and Image Processing -- Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware -- Invited Keynote 3 -- The Evolution of Programmable Logic: Past, Present, and Future Predictions -- Runtime Reconfiguration 2 -- Dynamically Reconfigurable Cores -- Reconfigurable Breakpoints for Co-debug -- Faults -- Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification -- FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits -- Methodology 2 -- A Generic Library for Adaptive Computing Environments -- Generative Development System for FPGA essors with Active Components -- Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines -- System Level Tools for DSP in FPGAs -- Arithmetic -- Parameterized Function Evaluation for FPGAs -- Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures -- A Digit-Serial Structure for Reconfigurable Multipliers -- FPGA Resource Reduction Through Truncated Multiplication -- Short Papers 1 -- Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures -- An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars -- Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach -- An Approach to Real-Time Visualization of PIV Method with FPGA -- FPGA-Based Discrete Wavelet Transforms System -- X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor -- Arithmetic Operation Oriented Reconfigurable Chip: RHW -- Short Papers 2 -- Initial Analysis of the Proteus Architecture -- Building Asynchronous Circuits with JBits -- Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux -- A Reconfigurable Approach to Packet Filtering -- FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding -- A Data Re-use Based Compiler Optimization for FPGAs -- Dijkstra’s Shortest Path Routing Algorithm in Reconfigurable Hardware -- A System on Chip for Power Line Communications According to European Home Systems Specifications. |
| Record Nr. | UNISA-996465912603316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Field-Programmable Logic and Applications : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings / / edited by Gordon Brebner, Roger Woods
| Field-Programmable Logic and Applications : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings / / edited by Gordon Brebner, Roger Woods |
| Edizione | [1st ed. 2001.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 |
| Descrizione fisica | 1 online resource (XV, 665 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Software engineering Computer communication systems Logic design Microprocessors Computer-aided engineering Computer System Implementation Software Engineering/Programming and Operating Systems Computer Communication Networks Logic Design Processor Architectures Computer-Aided Engineering (CAD, CAE) and Design |
| ISBN | 3-540-44687-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Keynote 1 -- Technology Trends and Adaptive Computing -- Architectural Frameworks -- Prototyping Framework for Reconfigurable Processors -- An Emulator for Exploring RaPiD Configurable Computing Architectures -- Place and Route 1 -- A New Placement Method for Direct Mapping into LUT-Based FPGAs -- fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits -- Architecture -- Macrocell Architectures for Product Term Embedded Memory Arrays -- Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs -- Memory Synthesis for FPGA-Based Reconfigurable Computers -- DSP 1 -- Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic -- Implementation of (Normalised) RLS Lattice on Virtex -- Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing -- Synthesis -- Static Profile-Driven Compilation for FPGAs -- Synthesizing RTL Hardware from Java Byte Codes -- PuMA++: From Behavioral Specification to Multi-FPGA-Prototype -- Encryption -- Secure Configuration of Field Programmable Gate Arrays -- Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm -- JBits™ Implementations of the Advanced Encryption Standard (Rijndael) -- Runtime Recon.guration 1 -- Task-Parallel Programming of Reconfigurable Systems -- Chip-Based Reconfigurable Task Management -- Configuration Caching and Swapping -- Graphics and Vision -- Multiple Stereo Matching Using an Extended Architecture -- Implementation of a NURBS to Bézier Conversor with Constant Latency -- Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems -- Invited Keynote 2 -- Processing Models for the Next Generation Network -- Place and Route 2 -- Tightly Integrated Placement and Routing for FPGAs -- Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays -- Networking -- Reconfigurable Router Modules Using Network Protocol Wrappers -- Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware -- Processor Interaction -- The MOLEN ??-Coded Processor -- Run-Time Optimized Reconfiguration Using Instruction Forecasting -- CRISP: A Template for Reconfigurable Instruction Set Processors -- Applications -- Evaluation of an FPGA Implementation of the Discrete Element Method -- Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers -- A Reconfigurable Embedded Input Device for Kinetically Challenged Persons -- Methodology 1 -- Bubble Partitioning for LUT-Based Sequential Circuits -- Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits -- Placing, Routing, and Editing Virtual FPGAs -- DSP 2 -- Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver -- A Music Synthesizer on FPGA -- Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders -- Loops and Systolic -- Loop Tiling for Reconfigurable Accelerators -- The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems -- A n-Bit Reconfigurable Scalar Quantiser -- Image Processing -- Real Time Morphological Image Contrast Enhancement in Virtex FPGA -- Demonstrating Real-time JPEG Image Compression-Decompression using Standard Component IP Cores on a Programmable Logic based Platform for DSP and Image Processing -- Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware -- Invited Keynote 3 -- The Evolution of Programmable Logic: Past, Present, and Future Predictions -- Runtime Reconfiguration 2 -- Dynamically Reconfigurable Cores -- Reconfigurable Breakpoints for Co-debug -- Faults -- Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification -- FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits -- Methodology 2 -- A Generic Library for Adaptive Computing Environments -- Generative Development System for FPGA essors with Active Components -- Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines -- System Level Tools for DSP in FPGAs -- Arithmetic -- Parameterized Function Evaluation for FPGAs -- Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures -- A Digit-Serial Structure for Reconfigurable Multipliers -- FPGA Resource Reduction Through Truncated Multiplication -- Short Papers 1 -- Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures -- An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars -- Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach -- An Approach to Real-Time Visualization of PIV Method with FPGA -- FPGA-Based Discrete Wavelet Transforms System -- X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor -- Arithmetic Operation Oriented Reconfigurable Chip: RHW -- Short Papers 2 -- Initial Analysis of the Proteus Architecture -- Building Asynchronous Circuits with JBits -- Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux -- A Reconfigurable Approach to Packet Filtering -- FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding -- A Data Re-use Based Compiler Optimization for FPGAs -- Dijkstra’s Shortest Path Routing Algorithm in Reconfigurable Hardware -- A System on Chip for Power Line Communications According to European Home Systems Specifications. |
| Record Nr. | UNINA-9910768457503321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The Palgrave handbook of testimony and culture / / edited by Sara Jones and Roger Woods
| The Palgrave handbook of testimony and culture / / edited by Sara Jones and Roger Woods |
| Pubbl/distr/stampa | Cham, Switzerland : , : Palgrave Macmillan, , [2023] |
| Descrizione fisica | 1 online resource : illustrations |
| Disciplina | 929.605 |
| Soggetto topico | Collective memory |
| ISBN | 9783031137945 (electronic book) |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910717422703321 |
| Cham, Switzerland : , : Palgrave Macmillan, , [2023] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011, Proceedings / / edited by Andreas Koch, Ram Krishnamurthy, John McAllister, Roger Woods, Tarek El-Ghazawi
| Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011, Proceedings / / edited by Andreas Koch, Ram Krishnamurthy, John McAllister, Roger Woods, Tarek El-Ghazawi |
| Edizione | [1st ed. 2011.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2011 |
| Descrizione fisica | 1 online resource (XIV, 398 p.) |
| Disciplina | 004.6 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Algorithms Software engineering Computer science Computer programming Computer simulation Computer Communication Networks Software Engineering Theory of Computation Programming Techniques Computer Modelling |
| ISBN | 3-642-19475-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996465915703316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009, Proceedings / / edited by Jürgen Becker, Roger Woods, Peter Athanas, Fearghal Morgan
| Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009, Proceedings / / edited by Jürgen Becker, Roger Woods, Peter Athanas, Fearghal Morgan |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XV, 388 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Computer vision Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation Computer Vision |
| ISBN | 3-642-00641-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- FPGA Design Productivity – A Discussion of the State of the Art and a Research Agenda -- Resiliency in Elemental Computing -- The Colour of Embedded Computation -- Applications 1 -- A HyperTransport 3 Physical Layer Interface for FPGAs -- Parametric Design for Reconfigurable Software-Defined Radio -- Applications 2 -- Hardware/Software FPGA Architecture for Robotics Applications -- Reconfigurable Operator Based Multimedia Embedded Processor -- FPGA Security and Bitstream Analysis -- A Protocol for Secure Remote Updates of FPGA Configurations -- FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing -- Fault Tolerant Systems -- An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications -- Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs -- Architectures -- A Novel Local Interconnect Architecture for Variable Grain Logic Cell -- Dynamically Adapted Low Power ASIPs -- Fast Optical Reconfiguration of a Nine-Context DORGA -- Place and Route Techniques -- Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep -- On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks -- A New Datapath Merging Method for Reconfigurable System -- Cryptography -- Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform -- Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm -- Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs -- Resource Allocation and Scheduling -- Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures -- Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems -- Applications 3 -- Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator -- FPGA-Based Anomalous Trajectory Detection Using SOFM -- Posters -- SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems -- A Parallel Branching Program Machine for Emulation of Sequential Circuits -- Memory Sharing Approach for TMR Softcore Processor -- The Need for Reconfigurable Routers in Networks-on-Chip -- Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware -- Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder -- Tile-Based Fault Tolerant Approach Using Partial Reconfiguration -- Regular Expression Pattern Matching Supporting Constrained Repetitions -- Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function -- AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications -- CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers -- Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera System -- Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture -- A Hardware Accelerated Simulation Environment for Spiking Neural Networks -- Survey of Advanced CABAC Accelerator Architectures for Future Multimedia -- Real Time Simulation in Floating Point Precision Using FPGA Computing -- A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem -- A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems -- Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator -- ACCFS – Operating System Integration of Computational Accelerators Using a VFS Approach -- A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. |
| Record Nr. | UNISA-996465883203316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
