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Nano-CMOS circuit and physical design [[electronic resource] /] / Ban P. Wong ... [et al.]
| Nano-CMOS circuit and physical design [[electronic resource] /] / Ban P. Wong ... [et al.] |
| Pubbl/distr/stampa | Hoboken, N.J., : John Wiley, c2005 |
| Descrizione fisica | 1 online resource (413 p.) |
| Disciplina | 621.39/732 |
| Altri autori (Persone) | WongBan P. <1953-> |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Design and construction
Integrated circuits - Design and construction |
| ISBN |
1-280-25476-9
9786610254767 0-470-35761-4 0-471-67886-4 0-471-65382-9 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
NANO-CMOS CIRCUIT AND PHYSICAL DESIGN; CONTENTS; FOREWORD; PREFACE; 1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS; 1.1 Design Methodology in the Nano-CMOS Era; 1.2 Innovations Needed to Continue Performance Scaling; 1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography; 1.3.1 Back-End-of-Line Challenges (Metallization); 1.3.2 Front-End-of-Line Challenges (Transistors); 1.4 Process Control and Reliability; 1.5 Lithographic Issues and Mask Data Explosion; 1.6 New Breed of Circuit and Physical Design Engineers; 1.7 Modeling Challenges
1.8 Need for Design Methodology Changes1.9 Summary; References; PART I PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS; 2 CMOS DEVICE AND PROCESS TECHNOLOGY; 2.1 Equipment Requirements for Front-End Processing; 2.1.1 Technical Background; 2.1.2 Gate Dielectric Scaling; 2.1.3 Strain Engineering; 2.1.4 Rapid Thermal Processing Technology; 2.2 Front-End-Device Problems in CMOS Scaling; 2.2.1 CMOS Scaling Challenges; 2.2.2 Quantum Effects Model; 2.2.3 Polysilicon Gate Depletion Effects; 2.2.4 Metal Gate Electrodes 2.2.5 Direct-Tunneling Gate Leakage2.2.6 Parasitic Capacitance; 2.2.7 Reliability Concerns; 2.3 Back-End-of-Line Technology; 2.3.1 Interconnect Scaling; 2.3.2 Copper Wire Technology; 2.3.3 Low-κ Dielectric Challenges; 2.3.4 Future Global Interconnect Technology; References; 3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY; 3.1 Introduction and Simple Imaging Theory; 3.2 Challenges for the 100-nm Node; 3.2.1 κ-Factor for the 100-nm Node; 3.2.2 Significant Process Variations; 3.2.3 Impact of Low-κ Imaging on Process Sensitivities; 3.2.4 Low-κ Imaging and Impact on Depth of Focus 3.2.5 Low-κ Imaging and Exposure Tolerance3.2.6 Low-κ Imaging and Impact on Mask Error Enhancement Factor; 3.2.7 Low-κ Imaging and Sensitivity to Aberrations; 3.2.8 Low-κ Imaging and CD Variation as a Function of Pitch; 3.2.9 Low-κ Imaging and Corner Rounding Radius; 3.3 Resolution Enhancement Techniques: Physics; 3.3.1 Specialized Illumination Patterns; 3.3.2 Optical Proximity Corrections; 3.3.3 Subresolution Assist Features; 3.3.4 Alternating Phase-Shift Masks; 3.4 Physical Design Style Impact on RET and OPC Complexity; 3.4.1 Specialized Illumination Conditions 3.4.2 Two-Dimensional Layouts3.4.3 Alternating Phase-Shift Masks; 3.4.4 Mask Costs; 3.5 The Road Ahead: Future Lithographic Technologies; 3.5.1 The Evolutionary Path: 157-nm Lithography; 3.5.2 Still Evolutionary: Immersion Lithography; 3.5.3 Quantum Leap: EUV Lithography; 3.5.4 Particle Beam Lithography; 3.5.5 Direct-Write Electron Beam Tools; References; PART II PROCESS SCALING IMPACT ON DESIGN; 4 MIXED-SIGNAL CIRCUIT DESIGN; 4.1 Introduction; 4.2 Design Considerations; 4.3 Device Modeling; 4.4 Passive Components; 4.5 Design Methodology; 4.5.1 Benchmark Circuits 4.5.2 Design Using Thin Oxide Devices |
| Record Nr. | UNINA-9910146057103321 |
| Hoboken, N.J., : John Wiley, c2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Nano-CMOS circuit and physical design / / Ban P. Wong ... [et al.]
| Nano-CMOS circuit and physical design / / Ban P. Wong ... [et al.] |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : John Wiley, c2005 |
| Descrizione fisica | 1 online resource (413 p.) |
| Disciplina | 621.39/732 |
| Altri autori (Persone) | WongBan P. <1953-> |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Design and construction
Integrated circuits - Design and construction |
| ISBN |
1-280-25476-9
9786610254767 0-470-35761-4 0-471-67886-4 0-471-65382-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
NANO-CMOS CIRCUIT AND PHYSICAL DESIGN; CONTENTS; FOREWORD; PREFACE; 1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS; 1.1 Design Methodology in the Nano-CMOS Era; 1.2 Innovations Needed to Continue Performance Scaling; 1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography; 1.3.1 Back-End-of-Line Challenges (Metallization); 1.3.2 Front-End-of-Line Challenges (Transistors); 1.4 Process Control and Reliability; 1.5 Lithographic Issues and Mask Data Explosion; 1.6 New Breed of Circuit and Physical Design Engineers; 1.7 Modeling Challenges
1.8 Need for Design Methodology Changes1.9 Summary; References; PART I PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS; 2 CMOS DEVICE AND PROCESS TECHNOLOGY; 2.1 Equipment Requirements for Front-End Processing; 2.1.1 Technical Background; 2.1.2 Gate Dielectric Scaling; 2.1.3 Strain Engineering; 2.1.4 Rapid Thermal Processing Technology; 2.2 Front-End-Device Problems in CMOS Scaling; 2.2.1 CMOS Scaling Challenges; 2.2.2 Quantum Effects Model; 2.2.3 Polysilicon Gate Depletion Effects; 2.2.4 Metal Gate Electrodes 2.2.5 Direct-Tunneling Gate Leakage2.2.6 Parasitic Capacitance; 2.2.7 Reliability Concerns; 2.3 Back-End-of-Line Technology; 2.3.1 Interconnect Scaling; 2.3.2 Copper Wire Technology; 2.3.3 Low-κ Dielectric Challenges; 2.3.4 Future Global Interconnect Technology; References; 3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY; 3.1 Introduction and Simple Imaging Theory; 3.2 Challenges for the 100-nm Node; 3.2.1 κ-Factor for the 100-nm Node; 3.2.2 Significant Process Variations; 3.2.3 Impact of Low-κ Imaging on Process Sensitivities; 3.2.4 Low-κ Imaging and Impact on Depth of Focus 3.2.5 Low-κ Imaging and Exposure Tolerance3.2.6 Low-κ Imaging and Impact on Mask Error Enhancement Factor; 3.2.7 Low-κ Imaging and Sensitivity to Aberrations; 3.2.8 Low-κ Imaging and CD Variation as a Function of Pitch; 3.2.9 Low-κ Imaging and Corner Rounding Radius; 3.3 Resolution Enhancement Techniques: Physics; 3.3.1 Specialized Illumination Patterns; 3.3.2 Optical Proximity Corrections; 3.3.3 Subresolution Assist Features; 3.3.4 Alternating Phase-Shift Masks; 3.4 Physical Design Style Impact on RET and OPC Complexity; 3.4.1 Specialized Illumination Conditions 3.4.2 Two-Dimensional Layouts3.4.3 Alternating Phase-Shift Masks; 3.4.4 Mask Costs; 3.5 The Road Ahead: Future Lithographic Technologies; 3.5.1 The Evolutionary Path: 157-nm Lithography; 3.5.2 Still Evolutionary: Immersion Lithography; 3.5.3 Quantum Leap: EUV Lithography; 3.5.4 Particle Beam Lithography; 3.5.5 Direct-Write Electron Beam Tools; References; PART II PROCESS SCALING IMPACT ON DESIGN; 4 MIXED-SIGNAL CIRCUIT DESIGN; 4.1 Introduction; 4.2 Design Considerations; 4.3 Device Modeling; 4.4 Passive Components; 4.5 Design Methodology; 4.5.1 Benchmark Circuits 4.5.2 Design Using Thin Oxide Devices |
| Record Nr. | UNINA-9910806143603321 |
| Hoboken, N.J., : John Wiley, c2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Nano-CMOS design for manufacturabililty [[electronic resource] ] : robust circuit and physical design for sub-65 nm technology nodes / / Ban Wong ... [et al.]
| Nano-CMOS design for manufacturabililty [[electronic resource] ] : robust circuit and physical design for sub-65 nm technology nodes / / Ban Wong ... [et al.] |
| Pubbl/distr/stampa | Hoboken, NJ, : Wiley, c2009 |
| Descrizione fisica | 1 online resource (403 p.) |
| Disciplina |
621.39/5
621.39732 |
| Altri autori (Persone) | WongBan P. <1953-> |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Design and construction
Integrated circuits - Design and construction Nanoelectronics |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-282-68822-7
9786612688225 0-470-38282-1 1-61583-175-4 0-470-38281-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
NANO-CMOS DESIGN FOR MANUFACTURABILILTY; CONTENTS; PREFACE; ACKNOWLEDGMENTS; 1 Introduction; 1.1 Value of Design for Manufacturability; 1.2 Deficiencies in Boolean-Based Design Rules in the Subwavelength Regime; 1.3 Impact of Variability on Yield and Performance; 1.4 Industry Challenge: The Disappearing Process Window; 1.5 Mobility Enhancement Techniques: A New Source of Variability Induced by Design-Process Interaction; 1.6 Design Dependency of Chip Surface Topology; 1.7 Newly Exacerbated Narrow Width Effect in Nano-CMOS Nodes; 1.8 Well Proximity Effect
1.9 Need for Model-Based DFM Solutions Beyond 65 nm1.10 Summary; References; I NEWLY EXACERBATED EFFECTS; 2 Lithography-Related Aspects of DFM; 2.1 Economic Motivations for DFM; 2.2 Lithographic Tools and Techniques for Advanced Technology Nodes; 2.2.1 Lithographic Approaches to Sub-90-nm Lithography; 2.2.2 Lithographic Infrastructure; 2.2.3 Immersion Exposure Tools; 2.2.4 Overlay; 2.2.5 Cooptimization of the Mask, the Illuminator, and Apodization; 2.2.6 Optical Proximity Correction; 2.2.7 Double Patterning; 2.2.8 Lithographic Roadmap; 2.3 Lithography Limited Yield 2.3.1 Deviations of Printed Shape from Drawn Polygon2.3.2 Increased Variabilities; 2.3.3 Catastrophic Failures; 2.4 Lithography-Driven DFM Solutions; 2.4.1 Practical Boundary Conditions for DFM; 2.4.2 Classical Approach; 2.4.3 Printability Checkers; 2.4.4 Model-Based Design Rule Checks; 2.4.5 ASIC Cell Optimizations; 2.4.6 Lithography-Aware Routers; 2.4.7 Advanced OPC Techniques for Improved Manufacturing; References; 3 Interaction of Layout with Transistor Performance and Stress Engineering Techniques; 3.1 Introduction; 3.2 Impact of Stress on Transistor Performance; 3.2.1 Electron Mobility 3.2.2 Hole Mobility3.2.3 Threshold Voltage; 3.2.4 Junction Leakage; 3.2.5 High Stress Levels; 3.2.6 Crystal Orientations; 3.2.7 Uniaxial, Biaxial, and Arbitrary Stress Patterns; 3.2.8 Stress Gradients; 3.2.9 Effects of Temperature and High Dopant Concentrations; 3.2.10 Stress Effects in Nonsilicon Semiconductors; 3.3 Stress Propagation; 3.3.1 Stress Propagation for Various Stress Source Geometries; 3.3.2 Stress Propagation Through STI and Other Barriers; 3.3.3 Free Boundaries; 3.4 Stress Sources; 3.4.1 Thermal Mismatch: STI and Silicide; 3.4.2 Lattice Mismatch: eSiGe and Si : C 3.4.3 Layer Growth3.4.4 Intrinsic Stress: CESL and DSL; 3.4.5 Stress Memorization Technique; 3.4.6 Stress Measurement Techniques; 3.4.7 Stress Simulation Techniques; 3.5 Introducing Stress into Transistors; 3.5.1 Stress Evolution During Process Flow; 3.5.2 Stress Relaxation Mechanisms; 3.5.3 Combining Several Stress Sources; 3.5.4 Stress-Engineered Memory Retention; 3.5.5 Layout-Induced Variations; 3.5.6 Bulk Transistors versus SOI and FinFET; References; II DESIGN SOLUTIONS; 4 Signal and Power Integrity; 4.1 Introduction; 4.2 Interconnect Resistance, Capacitance, and Inductance 4.2.1 Process Scaling and Interconnect Fabrication |
| Record Nr. | UNINA-9910144431403321 |
| Hoboken, NJ, : Wiley, c2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Nano-CMOS design for manufacturabililty [[electronic resource] ] : robust circuit and physical design for sub-65 nm technology nodes / / Ban Wong ... [et al.]
| Nano-CMOS design for manufacturabililty [[electronic resource] ] : robust circuit and physical design for sub-65 nm technology nodes / / Ban Wong ... [et al.] |
| Pubbl/distr/stampa | Hoboken, NJ, : Wiley, c2009 |
| Descrizione fisica | 1 online resource (403 p.) |
| Disciplina |
621.39/5
621.39732 |
| Altri autori (Persone) | WongBan P. <1953-> |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Design and construction
Integrated circuits - Design and construction Nanoelectronics |
| ISBN |
1-282-68822-7
9786612688225 0-470-38282-1 1-61583-175-4 0-470-38281-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
NANO-CMOS DESIGN FOR MANUFACTURABILILTY; CONTENTS; PREFACE; ACKNOWLEDGMENTS; 1 Introduction; 1.1 Value of Design for Manufacturability; 1.2 Deficiencies in Boolean-Based Design Rules in the Subwavelength Regime; 1.3 Impact of Variability on Yield and Performance; 1.4 Industry Challenge: The Disappearing Process Window; 1.5 Mobility Enhancement Techniques: A New Source of Variability Induced by Design-Process Interaction; 1.6 Design Dependency of Chip Surface Topology; 1.7 Newly Exacerbated Narrow Width Effect in Nano-CMOS Nodes; 1.8 Well Proximity Effect
1.9 Need for Model-Based DFM Solutions Beyond 65 nm1.10 Summary; References; I NEWLY EXACERBATED EFFECTS; 2 Lithography-Related Aspects of DFM; 2.1 Economic Motivations for DFM; 2.2 Lithographic Tools and Techniques for Advanced Technology Nodes; 2.2.1 Lithographic Approaches to Sub-90-nm Lithography; 2.2.2 Lithographic Infrastructure; 2.2.3 Immersion Exposure Tools; 2.2.4 Overlay; 2.2.5 Cooptimization of the Mask, the Illuminator, and Apodization; 2.2.6 Optical Proximity Correction; 2.2.7 Double Patterning; 2.2.8 Lithographic Roadmap; 2.3 Lithography Limited Yield 2.3.1 Deviations of Printed Shape from Drawn Polygon2.3.2 Increased Variabilities; 2.3.3 Catastrophic Failures; 2.4 Lithography-Driven DFM Solutions; 2.4.1 Practical Boundary Conditions for DFM; 2.4.2 Classical Approach; 2.4.3 Printability Checkers; 2.4.4 Model-Based Design Rule Checks; 2.4.5 ASIC Cell Optimizations; 2.4.6 Lithography-Aware Routers; 2.4.7 Advanced OPC Techniques for Improved Manufacturing; References; 3 Interaction of Layout with Transistor Performance and Stress Engineering Techniques; 3.1 Introduction; 3.2 Impact of Stress on Transistor Performance; 3.2.1 Electron Mobility 3.2.2 Hole Mobility3.2.3 Threshold Voltage; 3.2.4 Junction Leakage; 3.2.5 High Stress Levels; 3.2.6 Crystal Orientations; 3.2.7 Uniaxial, Biaxial, and Arbitrary Stress Patterns; 3.2.8 Stress Gradients; 3.2.9 Effects of Temperature and High Dopant Concentrations; 3.2.10 Stress Effects in Nonsilicon Semiconductors; 3.3 Stress Propagation; 3.3.1 Stress Propagation for Various Stress Source Geometries; 3.3.2 Stress Propagation Through STI and Other Barriers; 3.3.3 Free Boundaries; 3.4 Stress Sources; 3.4.1 Thermal Mismatch: STI and Silicide; 3.4.2 Lattice Mismatch: eSiGe and Si : C 3.4.3 Layer Growth3.4.4 Intrinsic Stress: CESL and DSL; 3.4.5 Stress Memorization Technique; 3.4.6 Stress Measurement Techniques; 3.4.7 Stress Simulation Techniques; 3.5 Introducing Stress into Transistors; 3.5.1 Stress Evolution During Process Flow; 3.5.2 Stress Relaxation Mechanisms; 3.5.3 Combining Several Stress Sources; 3.5.4 Stress-Engineered Memory Retention; 3.5.5 Layout-Induced Variations; 3.5.6 Bulk Transistors versus SOI and FinFET; References; II DESIGN SOLUTIONS; 4 Signal and Power Integrity; 4.1 Introduction; 4.2 Interconnect Resistance, Capacitance, and Inductance 4.2.1 Process Scaling and Interconnect Fabrication |
| Record Nr. | UNINA-9910830274603321 |
| Hoboken, NJ, : Wiley, c2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Nano-CMOS design for manufacturabililty : robust circuit and physical design for sub-65 nm technology nodes / / Ban Wong ... [et al.]
| Nano-CMOS design for manufacturabililty : robust circuit and physical design for sub-65 nm technology nodes / / Ban Wong ... [et al.] |
| Pubbl/distr/stampa | Hoboken, NJ, : Wiley, c2009 |
| Descrizione fisica | 1 online resource (403 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) | WongBan P. <1953-> |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Design and construction
Integrated circuits - Design and construction Nanoelectronics |
| ISBN |
1-282-68822-7
9786612688225 0-470-38282-1 1-61583-175-4 0-470-38281-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
NANO-CMOS DESIGN FOR MANUFACTURABILILTY; CONTENTS; PREFACE; ACKNOWLEDGMENTS; 1 Introduction; 1.1 Value of Design for Manufacturability; 1.2 Deficiencies in Boolean-Based Design Rules in the Subwavelength Regime; 1.3 Impact of Variability on Yield and Performance; 1.4 Industry Challenge: The Disappearing Process Window; 1.5 Mobility Enhancement Techniques: A New Source of Variability Induced by Design-Process Interaction; 1.6 Design Dependency of Chip Surface Topology; 1.7 Newly Exacerbated Narrow Width Effect in Nano-CMOS Nodes; 1.8 Well Proximity Effect
1.9 Need for Model-Based DFM Solutions Beyond 65 nm1.10 Summary; References; I NEWLY EXACERBATED EFFECTS; 2 Lithography-Related Aspects of DFM; 2.1 Economic Motivations for DFM; 2.2 Lithographic Tools and Techniques for Advanced Technology Nodes; 2.2.1 Lithographic Approaches to Sub-90-nm Lithography; 2.2.2 Lithographic Infrastructure; 2.2.3 Immersion Exposure Tools; 2.2.4 Overlay; 2.2.5 Cooptimization of the Mask, the Illuminator, and Apodization; 2.2.6 Optical Proximity Correction; 2.2.7 Double Patterning; 2.2.8 Lithographic Roadmap; 2.3 Lithography Limited Yield 2.3.1 Deviations of Printed Shape from Drawn Polygon2.3.2 Increased Variabilities; 2.3.3 Catastrophic Failures; 2.4 Lithography-Driven DFM Solutions; 2.4.1 Practical Boundary Conditions for DFM; 2.4.2 Classical Approach; 2.4.3 Printability Checkers; 2.4.4 Model-Based Design Rule Checks; 2.4.5 ASIC Cell Optimizations; 2.4.6 Lithography-Aware Routers; 2.4.7 Advanced OPC Techniques for Improved Manufacturing; References; 3 Interaction of Layout with Transistor Performance and Stress Engineering Techniques; 3.1 Introduction; 3.2 Impact of Stress on Transistor Performance; 3.2.1 Electron Mobility 3.2.2 Hole Mobility3.2.3 Threshold Voltage; 3.2.4 Junction Leakage; 3.2.5 High Stress Levels; 3.2.6 Crystal Orientations; 3.2.7 Uniaxial, Biaxial, and Arbitrary Stress Patterns; 3.2.8 Stress Gradients; 3.2.9 Effects of Temperature and High Dopant Concentrations; 3.2.10 Stress Effects in Nonsilicon Semiconductors; 3.3 Stress Propagation; 3.3.1 Stress Propagation for Various Stress Source Geometries; 3.3.2 Stress Propagation Through STI and Other Barriers; 3.3.3 Free Boundaries; 3.4 Stress Sources; 3.4.1 Thermal Mismatch: STI and Silicide; 3.4.2 Lattice Mismatch: eSiGe and Si : C 3.4.3 Layer Growth3.4.4 Intrinsic Stress: CESL and DSL; 3.4.5 Stress Memorization Technique; 3.4.6 Stress Measurement Techniques; 3.4.7 Stress Simulation Techniques; 3.5 Introducing Stress into Transistors; 3.5.1 Stress Evolution During Process Flow; 3.5.2 Stress Relaxation Mechanisms; 3.5.3 Combining Several Stress Sources; 3.5.4 Stress-Engineered Memory Retention; 3.5.5 Layout-Induced Variations; 3.5.6 Bulk Transistors versus SOI and FinFET; References; II DESIGN SOLUTIONS; 4 Signal and Power Integrity; 4.1 Introduction; 4.2 Interconnect Resistance, Capacitance, and Inductance 4.2.1 Process Scaling and Interconnect Fabrication |
| Record Nr. | UNINA-9910876528803321 |
| Hoboken, NJ, : Wiley, c2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||