| Autore |
Wilson Peter R (Peter Robert), <1939->
|
| Edizione | [1st ed.] |
| Pubbl/distr/stampa |
Amsterdam ; ; Boston ; ; London, : Newnes, 2007
|
| Descrizione fisica |
xxii, 289 p. : ill
|
| Disciplina |
621.395
|
| Soggetto topico |
Field programmable gate arrays - Design and construction
Gate array circuits
|
| Formato |
Materiale a stampa  |
| Livello bibliografico |
Monografia |
| Lingua di pubblicazione |
eng
|
| Nota di contenuto |
Front cover -- Design Recipes for FPGAs -- Copyright page -- Contents -- Acknowledgements -- Preface -- List of Figures -- Part 1 Overview -- Chapter 1 Introduction -- Why FPGAs? -- Chapter 2 An FPGA Primer -- Introduction -- FPGA evolution -- Programmable logic devices -- Field programmable gate arrays -- FPGA design techniques -- Design constraints using FPGAs -- Summary -- Chapter 3 A VHDL Primer The Essentials -- Introduction -- Entity: model interface -- Architecture: model behavior -- Process: basic functional unit in VHDL -- Basic variable types and operators -- Decisions and loops -- Hierarchical design -- Debugging models -- Basic data types -- Summary -- Chapter 4 Design Automation and Testing for FPGAs -- Simulation -- Libraries -- Synthesis -- Physical design flow -- Place and route -- Timing analysis -- Design pitfalls -- VHDL issues for FPGA design -- Summary -- Part 2 Applications -- Chapter 5 Images and High-Speed Processing -- Introduction -- The camera link interface -- Getting started -- Specifying the interfaces -- Defining the top level design -- System block definitions and interfaces -- The cameralink interface -- The PC interface -- Summary -- Chapter 6 Embedded Processors -- Introduction -- A simple embedded processor -- Soft core processors on an FPGA -- Summary -- Part 3 Designer's Toolbox -- Chapter 7 Serial Communications -- Introduction -- Manchester encoding and decoding -- NRZ coding and decoding -- NRZI coding and decoding -- RS-232 -- Universal Serial Bus -- Summary -- Chapter 8 Digital Filters -- Introduction -- Converting S-domain to Z-domain -- Implementing Z-domain functions in VHDL -- Basic low pass filter model -- FIR filters -- IIR filters -- Summary -- Chapter 9 Secure Systems -- Introduction to block ciphers -- Feistel lattice structures -- The Data Encryption Standard -- Advanced Encryption Standard.
Implementing AES in VHDL -- Summary -- Chapter 10 Memory -- Introduction -- Modeling memory in VHDL -- Read Only Memory -- Random Access Memory -- Synchronous RAM -- FLASH memory -- Summary -- Chapter 11 PS/2 Mouse Interface -- Introduction -- PS/2 mouse basics -- PS/2 mouse commands -- PS/2 mouse data packets -- PS/2 operation modes -- PS/2 mouse with wheel -- Basic PS/2 mouse handler VHDL -- Modified PS/2 mouse handler VHDL -- Summary -- Chapter 12 PS/2 Keyboard Interface -- Introduction -- PS/2 keyboard basics -- PS/2 keyboard commands -- PS/2 keyboard data packets -- PS/2 keyboard operation modes -- Summary -- Chapter 13 A Simple VGA Interface -- Introduction -- Basic pixel timing -- Image handling -- VGA interface VHDL -- Horizontal sync -- Vertical sync -- Horizontal and vertical blanking pulses -- Calculating the correct pixel data -- Summary -- Part 4 Optimizing Designs -- Chapter 14 Synthesis -- Introduction -- VHDL supported in RTL synthesis -- Some interesting cases where synthesis may fail -- What is being synthesized? -- Summary -- Chapter 15 Behavioral Modeling in VHDL -- Introduction -- How to go from RTL to behavioral VHDL -- Summary -- Chapter 16 Design Optimization -- Introduction -- Techniques for logic optimization -- Improving performance -- Critical path analysis -- Summary -- Chapter 17 VHDL-AMS -- Introduction -- Introduction to VHDL-AMS -- Analog pins: TERMINALS -- Mixed-domain modeling -- Analog variables: quantities -- Simultaneous equations in VHDL-AMS -- A VHDL-AMS example -- Differential equations in VHDL-AMS -- Mixed-signal modeling with VHDL-AMS -- A basic switch model -- Basic VHDL-AMS comparator model -- Multiple domain modeling -- Summary -- Chapter 18 Design Optimization Example: DES -- Introduction -- The DES -- Moods -- Initial design -- Initial synthesis -- Optimizing the data path -- Final optimization.
Results -- Triple DES -- Comparing the approaches -- Summary -- Part 5 Fundamental Techniques -- Chapter 19 Counters -- Introduction -- Basic binary counter -- Synthesized simple binary counter -- Shift register -- The Johnson counter -- BCD counter -- Summary -- Chapter 20 Latches, Flip-Flops and Registers -- Introduction -- Latches -- Flip-flops -- Registers -- Summary -- Chapter 21 Serial to Parallel & -- Parallel to Serial Conversion -- Serial to Parallel Conversion -- Parallel to Serial Conversion -- Summary -- Chapter 22 ALU Functions -- Introduction -- Logic functions -- 1-bit adder -- Structural n-bit addition -- Configurable n-bit addition -- Twos complement -- Summary -- Chapter 23 Decoders and Multiplexers -- Decoders -- Multiplexers -- Summary -- Chapter 24 Finite State Machines in VHDL -- Introduction -- State transition diagrams -- Implementing FSM in VHDL -- Summary -- Chapter 25 Fixed Point Arithmetic in VHDL -- Introduction -- Basic fixed point types -- Fixed point functions -- Testing the fixed point function -- Summary -- Chapter 26 Binary Multiplication -- Introduction -- Basic binary multiplication -- VHDL unsigned multiplier -- Synthesis of the multiplication function -- 'Simple' multiplication -- Summary -- Chapter 27 Bibliography -- Introduction -- Useful texts for VHDL -- Useful Texts for FPGAs -- General Digital Design Books -- Index -- A -- B -- C -- D -- E -- F -- L -- M -- P -- R -- S -- V -- Z.
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| Record Nr. | UNINA-9910811745003321 |
Info
Design recipes for FPGAs [[electronic resource] /] / Peter R. Wilson
