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Electrical overstress (EOS) [[electronic resource] ] : devices, circuits and systems / / Steven H. Voldman
| Electrical overstress (EOS) [[electronic resource] ] : devices, circuits and systems / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014 |
| Descrizione fisica | 1 online resource (370 p.) |
| Disciplina | 621.3815 |
| Collana | ESD series |
| Soggetto topico |
Semiconductors - Failures
Semiconductors - Protection Transients (Electricity) Overvoltage |
| ISBN |
1-118-70333-2
1-118-70332-4 1-118-70334-0 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Electrical Overstress (EOS): Devices, Circuits and Systems; Contents; About the Author; Preface; Acknowledgements; 1 Fundamentals of Electrical Overstress; 1.1 Electrical Overstress; 1.1.1 The Cost of Electrical Overstress; 1.1.2 Product Field Returns - The Percentage that is Electrical Overstress; 1.1.3 Product Field Returns - No Defect Found versus Electrical Overstress; 1.1.4 Product Failures - Failures in Integrated Circuits; 1.1.5 Classification of Electrical Overstress Events; 1.1.6 Electrical Over-Current; 1.1.7 Electrical Over-Voltage; 1.1.8 Electrical Over-Power
1.2 De-Mystifying Electrical Overstress1.2.1 Electrical Overstress Events; 1.3 Sources of Electrical Overstress; 1.3.1 Sources of Electrical Overstress in Manufacturing Environment; 1.3.2 Sources of Electrical Overstress in Production Environments; 1.4 Misconceptions of Electrical Overstress; 1.5 Minimization of Electrical Overstress Sources; 1.6 Mitigation of Electrical Overstress; 1.7 Signs of Electrical Overstress Damage; 1.7.1 Signs of Electrical Overstress Damage - The Electrical Signature; 1.7.2 Signs of Electrical Overstress Damage - The Visual Signature 1.8 Electrical Overstress and Electrostatic Discharge1.8.1 Comparison of High and Low Current EOS versus ESD Events; 1.8.2 Electrical Overstress and Electrostatic Discharge Differences; 1.8.3 Electrical Overstress and Electrostatic Discharge Similarities; 1.8.4 Comparison of EOS versus ESDWaveforms; 1.8.5 Comparison of EOS versus ESD Event Failure Damage; 1.9 Electromagnetic Interference; 1.9.1 Electrical Overstress Induced Electromagnetic Interference; 1.10 Electromagnetic Compatibility; 1.11 Thermal Over-Stress; 1.11.1 Electrical Overstress and Thermal Overstress 1.11.2 Temperature Dependent Electrical Overstress1.11.3 Electrical Overstress and Melting Temperature; 1.12 Reliability Technology Scaling; 1.12.1 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.12.2 The Shrinking Reliability Design Box; 1.12.3 The Shrinking Electrostatic Discharge Design Box; 1.12.4 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.13 Safe Operating Area; 1.13.1 Electrical Safe Operating Area; 1.13.2 Thermal Safe Operating Area; 1.13.3 Transient Safe Operating Area; 1.14 Summary and Closing Comments; References 2 Fundamentals of EOS Models2.1 Thermal Time Constants; 2.1.1 The Thermal Diffusion Time; 2.1.2 The Adiabatic Regime Time Constant; 2.1.3 The Thermal Diffusion Regime Time Constant; 2.1.4 The Steady State Regime Time Constant; 2.2 Pulse Event Time Constants; 2.2.1 The ESD HBM Pulse Time Constant; 2.2.2 The ESD MM Pulse Time Constant; 2.2.3 The ESD Charged Device Model Pulse Time Constant; 2.2.4 The ESD Pulse Time Constant - Transmission Line Pulse; 2.2.5 The ESD Pulse Time Constant - Very Fast Transmission Line Pulse; 2.2.6 The IEC 61000-4-2 Pulse Time Constant 2.2.7 The Cable Discharge Event Pulse Time Constant |
| Record Nr. | UNINA-9910139024303321 |
Voldman Steven H
|
||
| Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electrical overstress (EOS) [[electronic resource] ] : devices, circuits and systems / / Steven H. Voldman
| Electrical overstress (EOS) [[electronic resource] ] : devices, circuits and systems / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014 |
| Descrizione fisica | 1 online resource (370 p.) |
| Disciplina | 621.3815 |
| Collana | ESD series |
| Soggetto topico |
Semiconductors - Failures
Semiconductors - Protection Transients (Electricity) Overvoltage |
| ISBN |
1-118-70333-2
1-118-70332-4 1-118-70334-0 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Electrical Overstress (EOS): Devices, Circuits and Systems; Contents; About the Author; Preface; Acknowledgements; 1 Fundamentals of Electrical Overstress; 1.1 Electrical Overstress; 1.1.1 The Cost of Electrical Overstress; 1.1.2 Product Field Returns - The Percentage that is Electrical Overstress; 1.1.3 Product Field Returns - No Defect Found versus Electrical Overstress; 1.1.4 Product Failures - Failures in Integrated Circuits; 1.1.5 Classification of Electrical Overstress Events; 1.1.6 Electrical Over-Current; 1.1.7 Electrical Over-Voltage; 1.1.8 Electrical Over-Power
1.2 De-Mystifying Electrical Overstress1.2.1 Electrical Overstress Events; 1.3 Sources of Electrical Overstress; 1.3.1 Sources of Electrical Overstress in Manufacturing Environment; 1.3.2 Sources of Electrical Overstress in Production Environments; 1.4 Misconceptions of Electrical Overstress; 1.5 Minimization of Electrical Overstress Sources; 1.6 Mitigation of Electrical Overstress; 1.7 Signs of Electrical Overstress Damage; 1.7.1 Signs of Electrical Overstress Damage - The Electrical Signature; 1.7.2 Signs of Electrical Overstress Damage - The Visual Signature 1.8 Electrical Overstress and Electrostatic Discharge1.8.1 Comparison of High and Low Current EOS versus ESD Events; 1.8.2 Electrical Overstress and Electrostatic Discharge Differences; 1.8.3 Electrical Overstress and Electrostatic Discharge Similarities; 1.8.4 Comparison of EOS versus ESDWaveforms; 1.8.5 Comparison of EOS versus ESD Event Failure Damage; 1.9 Electromagnetic Interference; 1.9.1 Electrical Overstress Induced Electromagnetic Interference; 1.10 Electromagnetic Compatibility; 1.11 Thermal Over-Stress; 1.11.1 Electrical Overstress and Thermal Overstress 1.11.2 Temperature Dependent Electrical Overstress1.11.3 Electrical Overstress and Melting Temperature; 1.12 Reliability Technology Scaling; 1.12.1 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.12.2 The Shrinking Reliability Design Box; 1.12.3 The Shrinking Electrostatic Discharge Design Box; 1.12.4 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.13 Safe Operating Area; 1.13.1 Electrical Safe Operating Area; 1.13.2 Thermal Safe Operating Area; 1.13.3 Transient Safe Operating Area; 1.14 Summary and Closing Comments; References 2 Fundamentals of EOS Models2.1 Thermal Time Constants; 2.1.1 The Thermal Diffusion Time; 2.1.2 The Adiabatic Regime Time Constant; 2.1.3 The Thermal Diffusion Regime Time Constant; 2.1.4 The Steady State Regime Time Constant; 2.2 Pulse Event Time Constants; 2.2.1 The ESD HBM Pulse Time Constant; 2.2.2 The ESD MM Pulse Time Constant; 2.2.3 The ESD Charged Device Model Pulse Time Constant; 2.2.4 The ESD Pulse Time Constant - Transmission Line Pulse; 2.2.5 The ESD Pulse Time Constant - Very Fast Transmission Line Pulse; 2.2.6 The IEC 61000-4-2 Pulse Time Constant 2.2.7 The Cable Discharge Event Pulse Time Constant |
| Record Nr. | UNINA-9910810547003321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : design and synthesis / / Steven H. Voldman
| ESD [[electronic resource] ] : design and synthesis / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K., : Wiley, 2011 |
| Descrizione fisica | 1 online resource (292 p.) |
| Disciplina | 621.3815/2 |
| Collana | ESD series |
| Soggetto topico |
Semiconductors - Protection
Integrated circuits - Protection Electrostatics Analog electronic systems - Design and construction |
| ISBN |
1-283-40527-X
9786613405272 1-119-99114-5 1-119-99113-7 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD Design and Synthesis; Contents; About the Author; Preface; Acknowledgments; 1 ESD Design Synthesis; 1.1 ESD DESIGN SYNTHESIS AND ARCHITECTURE FLOW; 1.1.1 Top-Down ESD Design; 1.1.2 Bottom-Up ESD Design; 1.1.3 Top-Down ESD Design - Memory Semiconductor Chips; 1.1.4 Top-Down ESD Design - ASIC Design System; 1.2 ESD DESIGN - THE SIGNAL PATH AND THE ALTERNATE CURRENT PATH; 1.3 ESD ELECTRICAL CIRCUIT AND SCHEMATIC ARCHITECTURE CONCEPTS; 1.3.1 The Ideal ESD Network and the Current-Voltage DC Design Window; 1.3.2 The ESD Design Window
1.3.3 The Ideal ESD Networks in the Frequency Domain Design Window1.4 MAPPING SEMICONDUCTOR CHIPS AND ESD DESIGNS; 1.4.1 Mapping Across Semiconductor Fabricators; 1.4.2 ESD Design Mapping Across Technology Generations; 1.4.3 Mapping from Bipolar Technology to CMOS Technology; 1.4.4 Mapping from Digital CMOS Technology to Mixed Signal Analog-Digital CMOS Technology; 1.4.5 Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI); 1.4.6 ESD Design - Mapping CMOS to RF CMOS Technology; 1.5 ESD CHIP ARCHITECTURE, AND ESD TEST STANDARDS; 1.5.1 ESD Chip Architecture and ESD Testing 1.6 ESD TESTING1.6.1 ESD Qualification Testing; 1.6.2 ESD Test Models; 1.6.3 ESD Characterization Testing; 1.6.4 TLP Testing; 1.7 ESD CHIP ARCHITECTURE AND ESD ALTERNATIVE CURRENT PATHS; 1.7.1 ESD Circuits, I/O, and Cores; 1.7.2 ESD Signal Pin Circuits; 1.7.3 ESD Power Clamp Networks; 1.7.4 ESD Rail-to-Rail Circuits; 1.7.5 ESD Design and Noise; 1.7.6 Internal Signal Path ESD Networks; 1.7.7 Cross-Domain ESD Networks; 1.8 ESD NETWORKS, SEQUENCING, AND CHIP ARCHITECTURE; 1.9 ESD DESIGN SYNTHESIS - LATCHUP-FREE ESD NETWORKS; 1.10 ESD DESIGN CONCEPTS - BUFFERING - INTER-DEVICE 1.11 ESD DESIGN CONCEPTS - BALLASTING - INTER-DEVICE1.12 ESD DESIGN CONCEPTS - BALLASTING - INTRA-DEVICE; 1.13 ESD DESIGN CONCEPTS - DISTRIBUTED LOAD TECHNIQUES; 1.14 ESD DESIGN CONCEPTS - DUMMY CIRCUITS; 1.15 ESD DESIGN CONCEPTS - POWER SUPPLY DE-COUPLING; 1.16 ESD DESIGN CONCEPTS - FEEDBACK LOOP DE-COUPLING; 1.17 ESD LAYOUT AND FLOORPLAN-RELATED CONCEPTS; 1.17.1 Design Symmetry; 1.17.2 Design Segmentation; 1.17.3 ESD Design Concepts - Utilization of Empty Space; 1.17.4 ESD Design Synthesis - Across Chip Line Width Variation (ACLV); 1.17.5 ESD Design Concepts - Dummy Shapes 1.17.6 ESD Design Concepts - Dummy Masks1.17.7 ESD Design Concepts - Adjacency; 1.18 ESD DESIGN CONCEPTS - ANALOG CIRCUIT TECHNIQUES; 1.19 ESD DESIGN CONCEPTS - WIRE BONDS; 1.20 DESIGN RULES; 1.20.1 ESD Design Rule Checking (DRC); 1.20.2 ESD Layout vs. Schematic (LVS); 1.20.3 Electrical Resistance Checking (ERC); 1.21 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 ESD Architecture and Floorplanning; 2.1 ESD DESIGN FLOORPLAN; 2.2 PERIPHERAL I/O DESIGN; 2.2.1 Pad-Limited Peripheral I/O Design Architecture; 2.2.2 Pad-Limited Peripheral I/O Design Architecture - Staggered I/O 2.2.3 Core-Limited Peripheral I/O Design Architecture |
| Record Nr. | UNINA-9910131049403321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K., : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : design and synthesis / / Steven H. Voldman
| ESD [[electronic resource] ] : design and synthesis / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K., : Wiley, 2011 |
| Descrizione fisica | 1 online resource (292 p.) |
| Disciplina | 621.3815/2 |
| Collana | ESD series |
| Soggetto topico |
Semiconductors - Protection
Integrated circuits - Protection Electrostatics Analog electronic systems - Design and construction |
| ISBN |
1-283-40527-X
9786613405272 1-119-99114-5 1-119-99113-7 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD Design and Synthesis; Contents; About the Author; Preface; Acknowledgments; 1 ESD Design Synthesis; 1.1 ESD DESIGN SYNTHESIS AND ARCHITECTURE FLOW; 1.1.1 Top-Down ESD Design; 1.1.2 Bottom-Up ESD Design; 1.1.3 Top-Down ESD Design - Memory Semiconductor Chips; 1.1.4 Top-Down ESD Design - ASIC Design System; 1.2 ESD DESIGN - THE SIGNAL PATH AND THE ALTERNATE CURRENT PATH; 1.3 ESD ELECTRICAL CIRCUIT AND SCHEMATIC ARCHITECTURE CONCEPTS; 1.3.1 The Ideal ESD Network and the Current-Voltage DC Design Window; 1.3.2 The ESD Design Window
1.3.3 The Ideal ESD Networks in the Frequency Domain Design Window1.4 MAPPING SEMICONDUCTOR CHIPS AND ESD DESIGNS; 1.4.1 Mapping Across Semiconductor Fabricators; 1.4.2 ESD Design Mapping Across Technology Generations; 1.4.3 Mapping from Bipolar Technology to CMOS Technology; 1.4.4 Mapping from Digital CMOS Technology to Mixed Signal Analog-Digital CMOS Technology; 1.4.5 Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI); 1.4.6 ESD Design - Mapping CMOS to RF CMOS Technology; 1.5 ESD CHIP ARCHITECTURE, AND ESD TEST STANDARDS; 1.5.1 ESD Chip Architecture and ESD Testing 1.6 ESD TESTING1.6.1 ESD Qualification Testing; 1.6.2 ESD Test Models; 1.6.3 ESD Characterization Testing; 1.6.4 TLP Testing; 1.7 ESD CHIP ARCHITECTURE AND ESD ALTERNATIVE CURRENT PATHS; 1.7.1 ESD Circuits, I/O, and Cores; 1.7.2 ESD Signal Pin Circuits; 1.7.3 ESD Power Clamp Networks; 1.7.4 ESD Rail-to-Rail Circuits; 1.7.5 ESD Design and Noise; 1.7.6 Internal Signal Path ESD Networks; 1.7.7 Cross-Domain ESD Networks; 1.8 ESD NETWORKS, SEQUENCING, AND CHIP ARCHITECTURE; 1.9 ESD DESIGN SYNTHESIS - LATCHUP-FREE ESD NETWORKS; 1.10 ESD DESIGN CONCEPTS - BUFFERING - INTER-DEVICE 1.11 ESD DESIGN CONCEPTS - BALLASTING - INTER-DEVICE1.12 ESD DESIGN CONCEPTS - BALLASTING - INTRA-DEVICE; 1.13 ESD DESIGN CONCEPTS - DISTRIBUTED LOAD TECHNIQUES; 1.14 ESD DESIGN CONCEPTS - DUMMY CIRCUITS; 1.15 ESD DESIGN CONCEPTS - POWER SUPPLY DE-COUPLING; 1.16 ESD DESIGN CONCEPTS - FEEDBACK LOOP DE-COUPLING; 1.17 ESD LAYOUT AND FLOORPLAN-RELATED CONCEPTS; 1.17.1 Design Symmetry; 1.17.2 Design Segmentation; 1.17.3 ESD Design Concepts - Utilization of Empty Space; 1.17.4 ESD Design Synthesis - Across Chip Line Width Variation (ACLV); 1.17.5 ESD Design Concepts - Dummy Shapes 1.17.6 ESD Design Concepts - Dummy Masks1.17.7 ESD Design Concepts - Adjacency; 1.18 ESD DESIGN CONCEPTS - ANALOG CIRCUIT TECHNIQUES; 1.19 ESD DESIGN CONCEPTS - WIRE BONDS; 1.20 DESIGN RULES; 1.20.1 ESD Design Rule Checking (DRC); 1.20.2 ESD Layout vs. Schematic (LVS); 1.20.3 Electrical Resistance Checking (ERC); 1.21 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 ESD Architecture and Floorplanning; 2.1 ESD DESIGN FLOORPLAN; 2.2 PERIPHERAL I/O DESIGN; 2.2.1 Pad-Limited Peripheral I/O Design Architecture; 2.2.2 Pad-Limited Peripheral I/O Design Architecture - Staggered I/O 2.2.3 Core-Limited Peripheral I/O Design Architecture |
| Record Nr. | UNINA-9910813763203321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K., : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : failure mechanisms and models / / Steven H. Voldman
| ESD [[electronic resource] ] : failure mechanisms and models / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 |
| Descrizione fisica | 1 online resource (410 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Semiconductors - Failures
Integrated circuits - Protection Integrated circuits - Testing Integrated circuits - Reliability Electric discharges Electrostatics |
| ISBN |
1-282-23713-6
9786612237133 0-470-74725-0 0-470-74726-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD Failure Mechanisms and Models; Contents; About the Author; Preface; Acknowledgments; 1 Failure Analysis and ESD; 1.1 INTRODUCTION; 1.1.1 FA Techniques for Evaluation of ESD Events; 1.1.2 Fundamental Concepts of ESD FA Methods and Practices; 1.1.3 ESD Failure: Why Do Semiconductor Chips Fail?; 1.1.4 How to Use FA to Design ESD Robust Technologies; 1.1.5 How to Use FA to Design ESD Robust Circuits; 1.1.6 How to Use FA for Temperature Prediction; 1.1.7 How to Use Failure Models for Power Prediction; 1.1.8 FA Methods, Design Rules, and ESD Ground Rules
1.1.9 FA and Semiconductor Process-Induced ESD Design Asymmetry 1.1.10 FA Methodology and Electro-thermal Simulation; 1.1.11 FA and ESD Testing Methodology; 1.1.12 FA Methodology for Evaluation of ESD Parasitics; 1.1.13 FA Methods and ESD Device Operation Verification; 1.1.14 FA Methodology to Evaluate Inter-power Rail Electrical Connectivity; 1.1.15 How to Use FA to Eliminate Failure Mechanisms; 1.2 ESD FAILURE: HOW DO MICRO-ELECTRONIC DEVICES FAIL?; 1.2.1 ESD Failure: How Do Metallurgical Junctions Fail?; 1.2.2 ESD Failure: How Do Insulators Fail?; 1.2.3 ESD Failure: How Do Metals Fail? 1.3 SENSITIVITY OF SEMICONDUCTOR COMPONENTS 1.3.1 ESD Sensitivity as a Function of Materials; 1.3.2 ESD Sensitivity as a Function of Semiconductor Devices; 1.3.3 ESD Sensitivity as a Function of Product Type; 1.3.4 ESD and Technology Scaling; 1.3.5 ESD Technology Roadmap; 1.4 HOW DO SEMICONDUCTOR CHIPS FAIL--ARE THE FAILURES RANDOM OR SYSTEMATIC?; 1.5 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 2 Failure Analysis Tools, Models, and Physics of Failure; 2.1 FA TECHNIQUES FOR EVALUATION OF ESD EVENTS; 2.2 FA TOOLS; 2.2.1 Optical Microscope; 2.2.2 Scanning Electron Microscope 2.2.3 Transmission Electron Microscope 2.2.4 Emission Microscope; 2.2.5 Thermally Induced Voltage Alteration; 2.2.6 Superconducting Quantum Interference Device Microscope; 2.2.7 Atomic Force Microscope; 2.2.8 The 2-D AFM; 2.2.9 Picosecond Current Analysis Tool; 2.2.10 Transmission Line Pulse--Pico second Current Analysis Tool; 2.3 ESD SIMULATION: ESD PULSE MODELS; 2.3.1 Human Body Model; 2.3.2 Machine Model; 2.3.3 Cassette Model; 2.3.4 Socketed Device Model; 2.3.5 Charged Board Model; 2.3.6 Cable Discharge Event; 2.3.7 IEC System-Level Pulse Model; 2.3.8 Human Metal Model 2.3.9 Transmission Line Pulse Testing 2.3.10 Very Fast Transmission Line Pulse (VF-TLP) Model; 2.3.11 Ultra-fast Transmission Line Pulse (UF-TLP) Model; 2.4 ELECTRO-THERMAL PHYSICAL MODELS; 2.4.1 Tasca Model; 2.4.2 Wunsch-Bell Model; 2.4.3 Smith-Littau Model; 2.4.4 Ash Model; 2.4.5 Arkihpov, Astvatsaturyan, Godovosyn, and Rudenko Model; 2.4.6 Dwyer, Franklin, and Campbell Model; 2.4.7 Vlasov-Sinkevitch Model; 2.5 STATISTICAL MODELS FOR ESD PREDICTION; 2.6 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 3 CMOS Failure Mechanisms; 3.1 TABLES OF CMOS ESD FAILURE MECHANISMS 3.2 LOCOS ISOLATION-DEFINED CMOS |
| Record Nr. | UNINA-9910139802703321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : failure mechanisms and models / / Steven H. Voldman
| ESD [[electronic resource] ] : failure mechanisms and models / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 |
| Descrizione fisica | 1 online resource (410 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Semiconductors - Failures
Integrated circuits - Protection Integrated circuits - Testing Integrated circuits - Reliability Electric discharges Electrostatics |
| ISBN |
1-282-23713-6
9786612237133 0-470-74725-0 0-470-74726-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD Failure Mechanisms and Models; Contents; About the Author; Preface; Acknowledgments; 1 Failure Analysis and ESD; 1.1 INTRODUCTION; 1.1.1 FA Techniques for Evaluation of ESD Events; 1.1.2 Fundamental Concepts of ESD FA Methods and Practices; 1.1.3 ESD Failure: Why Do Semiconductor Chips Fail?; 1.1.4 How to Use FA to Design ESD Robust Technologies; 1.1.5 How to Use FA to Design ESD Robust Circuits; 1.1.6 How to Use FA for Temperature Prediction; 1.1.7 How to Use Failure Models for Power Prediction; 1.1.8 FA Methods, Design Rules, and ESD Ground Rules
1.1.9 FA and Semiconductor Process-Induced ESD Design Asymmetry 1.1.10 FA Methodology and Electro-thermal Simulation; 1.1.11 FA and ESD Testing Methodology; 1.1.12 FA Methodology for Evaluation of ESD Parasitics; 1.1.13 FA Methods and ESD Device Operation Verification; 1.1.14 FA Methodology to Evaluate Inter-power Rail Electrical Connectivity; 1.1.15 How to Use FA to Eliminate Failure Mechanisms; 1.2 ESD FAILURE: HOW DO MICRO-ELECTRONIC DEVICES FAIL?; 1.2.1 ESD Failure: How Do Metallurgical Junctions Fail?; 1.2.2 ESD Failure: How Do Insulators Fail?; 1.2.3 ESD Failure: How Do Metals Fail? 1.3 SENSITIVITY OF SEMICONDUCTOR COMPONENTS 1.3.1 ESD Sensitivity as a Function of Materials; 1.3.2 ESD Sensitivity as a Function of Semiconductor Devices; 1.3.3 ESD Sensitivity as a Function of Product Type; 1.3.4 ESD and Technology Scaling; 1.3.5 ESD Technology Roadmap; 1.4 HOW DO SEMICONDUCTOR CHIPS FAIL--ARE THE FAILURES RANDOM OR SYSTEMATIC?; 1.5 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 2 Failure Analysis Tools, Models, and Physics of Failure; 2.1 FA TECHNIQUES FOR EVALUATION OF ESD EVENTS; 2.2 FA TOOLS; 2.2.1 Optical Microscope; 2.2.2 Scanning Electron Microscope 2.2.3 Transmission Electron Microscope 2.2.4 Emission Microscope; 2.2.5 Thermally Induced Voltage Alteration; 2.2.6 Superconducting Quantum Interference Device Microscope; 2.2.7 Atomic Force Microscope; 2.2.8 The 2-D AFM; 2.2.9 Picosecond Current Analysis Tool; 2.2.10 Transmission Line Pulse--Pico second Current Analysis Tool; 2.3 ESD SIMULATION: ESD PULSE MODELS; 2.3.1 Human Body Model; 2.3.2 Machine Model; 2.3.3 Cassette Model; 2.3.4 Socketed Device Model; 2.3.5 Charged Board Model; 2.3.6 Cable Discharge Event; 2.3.7 IEC System-Level Pulse Model; 2.3.8 Human Metal Model 2.3.9 Transmission Line Pulse Testing 2.3.10 Very Fast Transmission Line Pulse (VF-TLP) Model; 2.3.11 Ultra-fast Transmission Line Pulse (UF-TLP) Model; 2.4 ELECTRO-THERMAL PHYSICAL MODELS; 2.4.1 Tasca Model; 2.4.2 Wunsch-Bell Model; 2.4.3 Smith-Littau Model; 2.4.4 Ash Model; 2.4.5 Arkihpov, Astvatsaturyan, Godovosyn, and Rudenko Model; 2.4.6 Dwyer, Franklin, and Campbell Model; 2.4.7 Vlasov-Sinkevitch Model; 2.5 STATISTICAL MODELS FOR ESD PREDICTION; 2.6 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 3 CMOS Failure Mechanisms; 3.1 TABLES OF CMOS ESD FAILURE MECHANISMS 3.2 LOCOS ISOLATION-DEFINED CMOS |
| Record Nr. | UNINA-9910817124503321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : circuits and devices / / Steven H. Voldman
| ESD [[electronic resource] ] : circuits and devices / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley, 2006 |
| Descrizione fisica | 1 online resource (414 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Integrated circuits - Protection
Electronic apparatus and appliances - Protection Static eliminators Electric discharges Electrostatics |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-118-95448-3
1-118-95449-1 1-118-95447-5 1-280-33967-5 0-470-03347-9 0-470-03006-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Electrostatic discharge -- Design synthesis -- Mosfet ESD design -- ESD design : diode design -- ESD design : passive resistors -- Passives for digital, analog, and RF applications -- Off-chip drivers and ESD -- Receiver circuits -- Silicon on insulator (SOI) ESD design -- ESD circuits : BiCMOS -- ESD power clamps -- Bipolar ESD power clamps -- Silicon-controlled rectifier power clamps. |
| Record Nr. | UNINA-9910143743003321 |
|
Voldman Steven H
|
||
| Hoboken, NJ, : John Wiley, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : RF technology and circuits / / Steven H. Voldman
| ESD [[electronic resource] ] : RF technology and circuits / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, England ; ; Hoboken, NJ, : J. Wiley, c2006 |
| Descrizione fisica | 1 online resource (422 p.) |
| Disciplina |
621.384
621.38412 |
| Soggetto topico |
Radio frequency integrated circuits - Design and construction
Radio frequency integrated circuits - Protection Electrostatics Electric discharges - Prevention Static eliminators |
| ISBN |
1-280-72219-3
9786610722198 0-470-06140-5 0-470-06139-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD; Contents; Preface; Acknowledgements; Chapter 1 RF DESIGN and ESD; 1.1 Fundamental Concepts of ESD Design; 1.2 Fundamental Concepts of RF ESD Design; 1.3 Key RF ESD Contributions; 1.4 Key RF ESD Patents; 1.5 ESD Failure Mechanisms; 1.5.1 RF CMOS ESD Failure Mechanisms; 1.5.2 Silicon Germanium ESD Failure Mechanisms; 1.5.3 Silicon Germanium Carbon ESD Failure Mechanisms in Silicon Germanium Carbon Devices; 1.5.4 Gallium Arsenide Technology ESD Failure Mechanisms; 1.5.5 Indium Gallium Arsenide ESD Failure Mechanisms; 1.5.6 RF Bipolar Circuits ESD Failure Mechanisms; 1.6 RF Basics
1.7 Two-Port Network Parameters1.7.1 Z-Parameters; 1.7.2 Y-Parameters; 1.7.3. S-Parameters; 1.7.4 T-Parameters; 1.8 Stability: RF Design Stability and ESD; 1.9 Device Degradation and ESD Failure; 1.9.1 ESD-Induced D.C. Parameter Shift and Failure Criteria; 1.9.2 RF Parameters, ESD Degradation, and Failure Criteria; 1.10 RF ESD Testing; 1.10.1 ESD Testing Models; 1.10.2 RF Maximum Power-to-Failure and ESD Pulse Testing Methodology; 1.10.3 ESD-Induced RF Degradation and S-Parameter Evaluation Test Methodology; 1.11 Time Domain Reflectometry (TDR) and Impedance Methodology for ESD Testing 1.11.1 Time Domain Reflectometry (TDR) ESD Test System Evaluation1.11.2 ESD Degradation System Level Method - Eye Tests; 1.12 Product Level ESD Test and RF Functional Parameter Failure; 1.13 Combined RF and ESD TLP Test Systems; 1.14 Closing Comments and Summary; Problems; References; Chapter 2 RF ESD Design; 2.1 ESD Design Methods: Ideal ESD Networks and RF ESD Design Windows; 2.1.1 Ideal ESD Networks and the Current-Voltage d.c. Design Window; 2.1.2 Ideal ESD Networks in the Frequency Domain Design Window; 2.2 RF ESD Design Methods: Linearity 2.3 RF ESD Design: Passive Element Quality Factors and Figures of Merit2.4 RF ESD Design Methods: Method of Substitution; 2.4.1 Method of Substitution of Passive Element to ESD Network Element; 2.4.2 Substitution of ESD Network Element to Passive Element; 2.5 RF ESD Design Methods: Matching Networks and RF ESD Networks; 2.5.1 RF ESD Method - Conversion of Matching Networks to ESD Networks; 2.5.2 RF ESD Method: Conversion of ESD Networks into Matching Networks; 2.5.2.1 Conversion of ESD Networks into L-Match Networks; 2.5.2.2 Conversion of ESD Networks into Pie-Match Networks 2.5.2.3 Conversion of ESD Networks into T-Match Networks2.6 RF ESD Design Methods: Inductive Shunt; 2.7 RF ESD Design Methods: Cancellation Method; 2.7.1 Quality Factors and the Cancellation Method; 2.7.2 Inductive Cancellation of Capacitance Load and Figures of Merit; 2.7.3 Cancellation Method and ESD Circuitry; 2.8 RF ESD Design Methods: Impedance Isolation Technique Using LC Resonator; 2.9 RF ESD Design Methods: Lumped versus Distributed Loads; 2.9.1 RF ESD Distributed Load with Coplanar Wave Guides; 2.9.2 RF ESD Distribution Coplanar Waveguides Analysis Using ABCD Matrices 2.10 ESD RF Design Synthesis and Floor Planning: RF, Analog, and Digital Integration |
| Record Nr. | UNINA-9910830973303321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, England ; ; Hoboken, NJ, : J. Wiley, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : circuits and devices / / Steven H. Voldman
| ESD [[electronic resource] ] : circuits and devices / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley, 2006 |
| Descrizione fisica | 1 online resource (414 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Integrated circuits - Protection
Electronic apparatus and appliances - Protection Static eliminators Electric discharges Electrostatics |
| ISBN |
1-118-95448-3
1-118-95449-1 1-118-95447-5 1-280-33967-5 0-470-03347-9 0-470-03006-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Electrostatic discharge -- Design synthesis -- Mosfet ESD design -- ESD design : diode design -- ESD design : passive resistors -- Passives for digital, analog, and RF applications -- Off-chip drivers and ESD -- Receiver circuits -- Silicon on insulator (SOI) ESD design -- ESD circuits : BiCMOS -- ESD power clamps -- Bipolar ESD power clamps -- Silicon-controlled rectifier power clamps. |
| Record Nr. | UNINA-9910824563303321 |
|
Voldman Steven H
|
||
| Hoboken, NJ, : John Wiley, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : RF technology and circuits / / Steven H. Voldman
| ESD [[electronic resource] ] : RF technology and circuits / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, England ; ; Hoboken, NJ, : J. Wiley, c2006 |
| Descrizione fisica | 1 online resource (422 p.) |
| Disciplina |
621.384
621.38412 |
| Soggetto topico |
Radio frequency integrated circuits - Design and construction
Radio frequency integrated circuits - Protection Electrostatics Electric discharges - Prevention Static eliminators |
| ISBN |
1-280-72219-3
9786610722198 0-470-06140-5 0-470-06139-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD; Contents; Preface; Acknowledgements; Chapter 1 RF DESIGN and ESD; 1.1 Fundamental Concepts of ESD Design; 1.2 Fundamental Concepts of RF ESD Design; 1.3 Key RF ESD Contributions; 1.4 Key RF ESD Patents; 1.5 ESD Failure Mechanisms; 1.5.1 RF CMOS ESD Failure Mechanisms; 1.5.2 Silicon Germanium ESD Failure Mechanisms; 1.5.3 Silicon Germanium Carbon ESD Failure Mechanisms in Silicon Germanium Carbon Devices; 1.5.4 Gallium Arsenide Technology ESD Failure Mechanisms; 1.5.5 Indium Gallium Arsenide ESD Failure Mechanisms; 1.5.6 RF Bipolar Circuits ESD Failure Mechanisms; 1.6 RF Basics
1.7 Two-Port Network Parameters1.7.1 Z-Parameters; 1.7.2 Y-Parameters; 1.7.3. S-Parameters; 1.7.4 T-Parameters; 1.8 Stability: RF Design Stability and ESD; 1.9 Device Degradation and ESD Failure; 1.9.1 ESD-Induced D.C. Parameter Shift and Failure Criteria; 1.9.2 RF Parameters, ESD Degradation, and Failure Criteria; 1.10 RF ESD Testing; 1.10.1 ESD Testing Models; 1.10.2 RF Maximum Power-to-Failure and ESD Pulse Testing Methodology; 1.10.3 ESD-Induced RF Degradation and S-Parameter Evaluation Test Methodology; 1.11 Time Domain Reflectometry (TDR) and Impedance Methodology for ESD Testing 1.11.1 Time Domain Reflectometry (TDR) ESD Test System Evaluation1.11.2 ESD Degradation System Level Method - Eye Tests; 1.12 Product Level ESD Test and RF Functional Parameter Failure; 1.13 Combined RF and ESD TLP Test Systems; 1.14 Closing Comments and Summary; Problems; References; Chapter 2 RF ESD Design; 2.1 ESD Design Methods: Ideal ESD Networks and RF ESD Design Windows; 2.1.1 Ideal ESD Networks and the Current-Voltage d.c. Design Window; 2.1.2 Ideal ESD Networks in the Frequency Domain Design Window; 2.2 RF ESD Design Methods: Linearity 2.3 RF ESD Design: Passive Element Quality Factors and Figures of Merit2.4 RF ESD Design Methods: Method of Substitution; 2.4.1 Method of Substitution of Passive Element to ESD Network Element; 2.4.2 Substitution of ESD Network Element to Passive Element; 2.5 RF ESD Design Methods: Matching Networks and RF ESD Networks; 2.5.1 RF ESD Method - Conversion of Matching Networks to ESD Networks; 2.5.2 RF ESD Method: Conversion of ESD Networks into Matching Networks; 2.5.2.1 Conversion of ESD Networks into L-Match Networks; 2.5.2.2 Conversion of ESD Networks into Pie-Match Networks 2.5.2.3 Conversion of ESD Networks into T-Match Networks2.6 RF ESD Design Methods: Inductive Shunt; 2.7 RF ESD Design Methods: Cancellation Method; 2.7.1 Quality Factors and the Cancellation Method; 2.7.2 Inductive Cancellation of Capacitance Load and Figures of Merit; 2.7.3 Cancellation Method and ESD Circuitry; 2.8 RF ESD Design Methods: Impedance Isolation Technique Using LC Resonator; 2.9 RF ESD Design Methods: Lumped versus Distributed Loads; 2.9.1 RF ESD Distributed Load with Coplanar Wave Guides; 2.9.2 RF ESD Distribution Coplanar Waveguides Analysis Using ABCD Matrices 2.10 ESD RF Design Synthesis and Floor Planning: RF, Analog, and Digital Integration |
| Record Nr. | UNINA-9910841240003321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, England ; ; Hoboken, NJ, : J. Wiley, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
