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16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors : ASAP 2005 : 23-25 July 2005, Samos, Greece
| 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors : ASAP 2005 : 23-25 July 2005, Samos, Greece |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2005 |
| Soggetto topico |
Array processors - Digital techniques
Signal processing Application specific integrated circuits |
| ISBN | 1-5386-0301-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996206221003316 |
| [Place of publication not identified], : IEEE Computer Society, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors : ASAP 2005 : 23-25 July 2005, Samos, Greece
| 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors : ASAP 2005 : 23-25 July 2005, Samos, Greece |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2005 |
| Soggetto topico |
Array processors - Digital techniques
Signal processing Application specific integrated circuits |
| ISBN | 1-5386-0301-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910142342103321 |
| [Place of publication not identified], : IEEE Computer Society, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2004 Computing Frontier Conference April 14-16, 2004, Ischia, Italy
| 2004 Computing Frontier Conference April 14-16, 2004, Ischia, Italy |
| Autore | Vassiliadis Stamatis |
| Pubbl/distr/stampa | New York NY, : ACM Press, 2004 |
| Descrizione fisica | 1 online resource (522 p.;) |
| Disciplina | 004 |
| Collana | ACM Conferences |
| Soggetto topico |
Computer science
Information technology Computer networks Engineering & Applied Sciences Computer Science |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | CF '04 |
| Record Nr. | UNINA-9910375844003321 |
Vassiliadis Stamatis
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| New York NY, : ACM Press, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : Third and Fourth International Workshop, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings / / edited by Andy Pimentel, Stamatis Vassiliadis
| Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : Third and Fourth International Workshop, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings / / edited by Andy Pimentel, Stamatis Vassiliadis |
| Edizione | [1st ed. 2004.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004 |
| Descrizione fisica | 1 online resource (XIV, 566 p.) |
| Disciplina | 004.2/2 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computers
Computer hardware Microprocessors Computer communication systems Computer system failures Architecture, Computer Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| ISBN | 3-540-27776-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | SAMOS III – Reconfigurable Computing -- The Molen Programming Paradigm -- Loading ??-Code: Design Considerations -- RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems -- Basic OS Support for Distributed Reconfigurable Hardware -- A Cost-Efficient RISC Processor Platform for Real Time Audio Applications -- Customising Processors: Design-Time and Run-Time Opportunities -- Intermediate Level Components for Reconfigurable Platforms -- Performance Estimation of Streaming Media Applications for Reconfigurable Platforms -- SAMOS III – Architectures and Implementation -- CoDeL: Automatically Synthesizing Network Interface Controllers -- Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units -- An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs -- Register-Based Permutation Networks for Stride Permutations -- A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures -- Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability -- Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs -- SAMOS III – Compilers, System Modeling, and Simulation -- Comparison of Data Dependence Analysis Tests -- MOUSE: A Shortcut from Matlab Source to SIMD DSP Assembly Code -- High-Level Energy Estimation for ARM-Based SOCs -- IDF Models for Trace Transformations: A Case Study in Computational Refinement -- Systems, Architectures, Modeling, and Simulation 2004 (SAMOS IV) -- Programming Extremely Flexible Platforms -- SAMOS IV – Reconfigurable Computing -- The Virtex II ProTM MOLEN Processor -- Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements -- Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques -- Modeling Loop Unrolling: Approaches and Open Issues -- Self-loop Pipelining and Reconfigurable Dataflow Arrays -- Architecture Exploration for 3G Telephony Applications Using a Hardware–Software Prototyping Platform -- Embedded Context Aware Hardware Component Generation for Dataflow System Exploration -- On the (Re-)Use of IP-Components in Re-configurable Platforms -- Customising Hardware Designs for Elliptic Curve Cryptography -- Dynamic Hardware Reconfigurations: Performance Impact for MPEG2 -- Compiler and System Techniques for soc Distributed Reconfigurable Accelerators -- SAMOS IV – Architectures and Implementation -- Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications -- On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering -- Memory Bandwidth Requirements of Tile-Based Rendering -- Using CoDeL to Rapidly Prototype Network Processsor Extensions -- Synchronous Transfer Architecture (STA) -- Generated DSP Cores for Implementation of an OFDM Communication System -- A Novel Data-Path for Accelerating DSP Kernels -- Scalable FFT Processors and Pipelined Butterfly Units -- Scalable Instruction-Level Parallelism -- A Low-Power Multithreaded Processor for Baseband Communication Systems -- Initial Evaluation of Multimedia Extensions on VLIW Architectures -- HIBI v.2 Communication Network for System-on-Chip -- SAMOS IV – System Modeling, and Simulation -- DIF: An Interchange Format for Dataflow-Based Design Tools -- Scalable and Modular Scheduling -- Early ISS Integration into Network-on-Chip Designs -- Cycle Accurate Simulation Model Generation for SoC Prototyping -- Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting -- A Communication-Centric Design Flow for HIBI-Based SoCs -- Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets -- Communication Optimization in Compaan Process Networks -- Analysis of Dataflow Programs with Interval-Limited Data-Rates -- High-Speed Event-Driven RTL Compiled Simulation -- A High-Level Programming Paradigm for SystemC -- Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications -- Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration. |
| Record Nr. | UNISA-996465722603316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Computer Systems: Architectures, Modeling, and Simulation : Third and Fourth International Workshop, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings / / edited by Andy Pimentel, Stamatis Vassiliadis
| Computer Systems: Architectures, Modeling, and Simulation : Third and Fourth International Workshop, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings / / edited by Andy Pimentel, Stamatis Vassiliadis |
| Edizione | [1st ed. 2004.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004 |
| Descrizione fisica | 1 online resource (XIV, 566 p.) |
| Disciplina | 004.2/2 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers - Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| ISBN | 3-540-27776-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | SAMOS III – Reconfigurable Computing -- The Molen Programming Paradigm -- Loading ??-Code: Design Considerations -- RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems -- Basic OS Support for Distributed Reconfigurable Hardware -- A Cost-Efficient RISC Processor Platform for Real Time Audio Applications -- Customising Processors: Design-Time and Run-Time Opportunities -- Intermediate Level Components for Reconfigurable Platforms -- Performance Estimation of Streaming Media Applications for Reconfigurable Platforms -- SAMOS III – Architectures and Implementation -- CoDeL: Automatically Synthesizing Network Interface Controllers -- Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units -- An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs -- Register-Based Permutation Networks for Stride Permutations -- A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures -- Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability -- Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs -- SAMOS III – Compilers, System Modeling, and Simulation -- Comparison of Data Dependence Analysis Tests -- MOUSE: A Shortcut from Matlab Source to SIMD DSP Assembly Code -- High-Level Energy Estimation for ARM-Based SOCs -- IDF Models for Trace Transformations: A Case Study in Computational Refinement -- Systems, Architectures, Modeling, and Simulation 2004 (SAMOS IV) -- Programming Extremely Flexible Platforms -- SAMOS IV – Reconfigurable Computing -- The Virtex II ProTM MOLEN Processor -- Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements -- Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques -- Modeling Loop Unrolling: Approaches and Open Issues -- Self-loop Pipelining and Reconfigurable Dataflow Arrays -- Architecture Exploration for 3G Telephony Applications Using a Hardware–Software Prototyping Platform -- Embedded Context Aware Hardware Component Generation for Dataflow System Exploration -- On the (Re-)Use of IP-Components in Re-configurable Platforms -- Customising Hardware Designs for Elliptic Curve Cryptography -- Dynamic Hardware Reconfigurations: Performance Impact for MPEG2 -- Compiler and System Techniques for soc Distributed Reconfigurable Accelerators -- SAMOS IV – Architectures and Implementation -- Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications -- On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering -- Memory Bandwidth Requirements of Tile-Based Rendering -- Using CoDeL to Rapidly Prototype Network Processsor Extensions -- Synchronous Transfer Architecture (STA) -- Generated DSP Cores for Implementation of an OFDM Communication System -- A Novel Data-Path for Accelerating DSP Kernels -- Scalable FFT Processors and Pipelined Butterfly Units -- Scalable Instruction-Level Parallelism -- A Low-Power Multithreaded Processor for Baseband Communication Systems -- Initial Evaluation of Multimedia Extensions on VLIW Architectures -- HIBI v.2 Communication Network for System-on-Chip -- SAMOS IV – System Modeling, and Simulation -- DIF: An Interchange Format for Dataflow-Based Design Tools -- Scalable and Modular Scheduling -- Early ISS Integration into Network-on-Chip Designs -- Cycle Accurate Simulation Model Generation for SoC Prototyping -- Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting -- A Communication-Centric Design Flow for HIBI-Based SoCs -- Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets -- Communication Optimization in Compaan Process Networks -- Analysis of Dataflow Programs with Interval-Limited Data-Rates -- High-Speed Event-Driven RTL Compiled Simulation -- A High-Level Programming Paradigm for SystemC -- Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications -- Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration. |
| Record Nr. | UNINA-9910144188203321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings / / edited by Stamatis Vassiliadis, Mladen Berekovic, Timo D. Hämäläinen
| Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings / / edited by Stamatis Vassiliadis, Mladen Berekovic, Timo D. Hämäläinen |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (XVII, 470 p.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| ISBN | 3-540-73625-5 |
| Classificazione |
DAT 260f
SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- Software Is the Answer But What Is the Question? -- Integrating VLIW Processors with a Network on Chip -- System Modeling and Simulation -- Communication Architecture Simulation on the Virtual Synchronization Framework -- A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems -- Performance Evaluation of Memory Management Configurations in Linux for an OS-Level Design Space Exploration -- SC2SCFL: Automated SystemC to Translation -- VLSI Architectures -- Model and Validation of Block Cleaning Cost for Flash Memory -- VLSI Architecture for MRF Based Stereo Matching -- Low-Power Twiddle Factor Unit for FFT Computation -- Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors -- Scheduling & Programming Models -- An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code -- Improving TriMedia Cache Performance by Profile Guided Code Reordering -- A Streaming Machine Description and Programming Model -- Multi-processor Architectures -- Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via Packing -- Strategies for Compiling ?TC to Novel Chip Multiprocessors -- Image Quantisation on a Massively Parallel Embedded Processor -- Stream Image Processing on a Dual-Core Embedded System -- Reconfigurable Architectures -- MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing -- FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder -- Evaluating Large System-on-Chip on Multi-FPGA Platform -- Design Space Exploration -- Efficiency Measures for Multimedia SOCs -- On-Chip Bus Modeling for Power and Performance Estimation -- A Framework Introducing Model Reversibility in SoC Design Space Exploration -- Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration -- Processor Components -- Resource Conflict Detection in Simulation of Function Unit Pipelines -- A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing -- High-Bandwidth Address Generation Unit -- An IP Core for Embedded Java Systems -- Embedded Processors -- Parallel Memory Architecture for TTA Processor -- A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size -- Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction -- A Study of Energy Saving in Customizable Processors -- SoC for SDR -- Trends in Low Power Handset Software Defined Radio -- Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals -- Area Efficient Fully Programmable Baseband Processors -- The Next Generation Challenge for Software Defined Radio -- Design Methodology for Software Radio Systems -- Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC -- A Comparative Study of Different FFT Architectures for Software Defined Radio -- Wireless Sensors -- Design of 100 ?W Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring -- Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network -- System Architecture Modeling of an UWB Receiver for Wireless Sensor Network -- An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks -- SensorOS: A New Operating System for Time Critical WSN Applications -- Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks -- k ?+? Neigh: An Energy Efficient Topology Control for Wireless Sensor Networks. |
| Record Nr. | UNISA-996466103503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Embedded Computer Systems: Architectures, Modeling, and Simulation : 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings / / edited by Stamatis Vassiliadis, Mladen Berekovic, Timo D. Hämäläinen
| Embedded Computer Systems: Architectures, Modeling, and Simulation : 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings / / edited by Stamatis Vassiliadis, Mladen Berekovic, Timo D. Hämäläinen |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (XVII, 470 p.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers - Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| ISBN | 3-540-73625-5 |
| Classificazione |
DAT 260f
SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- Software Is the Answer But What Is the Question? -- Integrating VLIW Processors with a Network on Chip -- System Modeling and Simulation -- Communication Architecture Simulation on the Virtual Synchronization Framework -- A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems -- Performance Evaluation of Memory Management Configurations in Linux for an OS-Level Design Space Exploration -- SC2SCFL: Automated SystemC to Translation -- VLSI Architectures -- Model and Validation of Block Cleaning Cost for Flash Memory -- VLSI Architecture for MRF Based Stereo Matching -- Low-Power Twiddle Factor Unit for FFT Computation -- Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors -- Scheduling & Programming Models -- An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code -- Improving TriMedia Cache Performance by Profile Guided Code Reordering -- A Streaming Machine Description and Programming Model -- Multi-processor Architectures -- Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via Packing -- Strategies for Compiling ?TC to Novel Chip Multiprocessors -- Image Quantisation on a Massively Parallel Embedded Processor -- Stream Image Processing on a Dual-Core Embedded System -- Reconfigurable Architectures -- MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing -- FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder -- Evaluating Large System-on-Chip on Multi-FPGA Platform -- Design Space Exploration -- Efficiency Measures for Multimedia SOCs -- On-Chip Bus Modeling for Power and Performance Estimation -- A Framework Introducing Model Reversibility in SoC Design Space Exploration -- Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration -- Processor Components -- Resource Conflict Detection in Simulation of Function Unit Pipelines -- A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing -- High-Bandwidth Address Generation Unit -- An IP Core for Embedded Java Systems -- Embedded Processors -- Parallel Memory Architecture for TTA Processor -- A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size -- Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction -- A Study of Energy Saving in Customizable Processors -- SoC for SDR -- Trends in Low Power Handset Software Defined Radio -- Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals -- Area Efficient Fully Programmable Baseband Processors -- The Next Generation Challenge for Software Defined Radio -- Design Methodology for Software Radio Systems -- Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC -- A Comparative Study of Different FFT Architectures for Software Defined Radio -- Wireless Sensors -- Design of 100 ?W Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring -- Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network -- System Architecture Modeling of an UWB Receiver for Wireless Sensor Network -- An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks -- SensorOS: A New Operating System for Time Critical WSN Applications -- Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks -- k ?+? Neigh: An Energy Efficient Topology Control for Wireless Sensor Networks. |
| Record Nr. | UNINA-9910483294803321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings / / edited by Stamatis Vassiliadis, Stephan Wong, Timo D. Hämäläinen
| Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings / / edited by Stamatis Vassiliadis, Stephan Wong, Timo D. Hämäläinen |
| Edizione | [1st ed. 2006.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 |
| Descrizione fisica | 1 online resource (XV, 492 p.) |
| Disciplina | 004.2/2 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer System Implementation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation |
| ISBN | 3-540-36411-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- Reconfigurable Platform for Digital Convergence Terminals -- European Research in Embedded Systems -- System Design and Modeling -- Interface Overheads in Embedded Multimedia Software -- A UML Profile for Asynchronous Hardware Design -- Automated Distribution of UML 2.0 Designed Applications to a Configurable Multiprocessor Platform -- Towards a Transformation Chain Modeling Language -- Key Research Challenges for Successfully Applying MDD Within Real-Time Embedded Software Development -- Domain-Specific Modeling of Power Aware Distributed Real-Time Embedded Systems -- Mining Dynamic Document Spaces with Massively Parallel Embedded Processors -- Efficient Automated Clock Gating Using CoDeL -- An Optimization Methodology for Memory Allocation and Task Scheduling in SoCs Via Linear Programming -- Wireless Sensor Networks -- Designing Wireless Sensor Nodes -- Design, Implementation, and Experiments on Outdoor Deployment of Wireless Sensor Network for Environmental Monitoring -- LATONA: An Advanced Server Architecture for Ubiquitous Sensor Network -- An Approach for the Reduction of Power Consumption in Sensor Nodes of Wireless Sensor Networks: Case Analysis of Mica2 -- Energy-Driven Partitioning of Signal Processing Algorithms in Sensor Networks -- Preamble Sense Multiple Access (PSMA) for Impulse Radio Ultra Wideband Sensor Networks -- Security in Wireless Sensor Networks: Considerations and Experiments -- On Security of PAN Wireless Systems -- Processor Design -- Code Size Reduction by Compiler Tuning -- Energy Optimization of a Multi-bank Main Memory -- Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems -- Hybrid Functional and Instruction Level Power Modeling for Embedded Processors -- Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform -- Software Pipelining Support for Transport Triggered Architecture Processors -- SAD Prefetching for MPEG4 Using Flux Caches -- Effects of Program Compression -- Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors -- Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations -- A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme -- Reducing Execution Unit Leakage Power in Embedded Processors -- Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors -- Advantages of Java Processors in Cache Performance and Power for Embedded Applications -- Dependable Computing -- CARROT – A Tool for Fast and Accurate Soft Error Rate Estimation -- A Scheduling Strategy for a Real-Time Dependable Organic Middleware -- Autonomous Construction Technology of Community for Achieving High Assurance Service -- Preventing Denial-of-Service Attacks in Shared CMP Caches -- Architectures and Implementations -- A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures -- Real-Time Embedded System for Rear-View Mirror Overtaking Car Monitoring -- Design of Asynchronous Embedded Processor with New Ternary Data Encoding Scheme -- Hardware-Based IP Lookup Using n-Way Set Associative Memory and LPM Comparator -- A Flash File System to Support Fast Mounting for NAND Flash Memory Based Embedded Systems -- Rescheduling for Optimized SHA-1 Calculation -- Software Implementation of WiMAX on the Sandbridge SandBlaster Platform -- High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology -- Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box -- Embedded Sensor Systems -- Integrated Microsystems in Industrial Applications -- A Solid-State 2-D Wind Sensor -- Fault-Tolerant Bus System for Airbag Sensors and Actuators. |
| Record Nr. | UNISA-996465573703316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Embedded Computer Systems: Architectures, Modeling, and Simulation : 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings / / edited by Stamatis Vassiliadis, Stephan Wong, Timo D. Hämäläinen
| Embedded Computer Systems: Architectures, Modeling, and Simulation : 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings / / edited by Stamatis Vassiliadis, Stephan Wong, Timo D. Hämäläinen |
| Edizione | [1st ed. 2006.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 |
| Descrizione fisica | 1 online resource (XV, 492 p.) |
| Disciplina | 004.2/2 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computers Microprocessors Computer architecture Computer networks Electronic digital computers - Evaluation Computer System Implementation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation |
| ISBN | 3-540-36411-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- Reconfigurable Platform for Digital Convergence Terminals -- European Research in Embedded Systems -- System Design and Modeling -- Interface Overheads in Embedded Multimedia Software -- A UML Profile for Asynchronous Hardware Design -- Automated Distribution of UML 2.0 Designed Applications to a Configurable Multiprocessor Platform -- Towards a Transformation Chain Modeling Language -- Key Research Challenges for Successfully Applying MDD Within Real-Time Embedded Software Development -- Domain-Specific Modeling of Power Aware Distributed Real-Time Embedded Systems -- Mining Dynamic Document Spaces with Massively Parallel Embedded Processors -- Efficient Automated Clock Gating Using CoDeL -- An Optimization Methodology for Memory Allocation and Task Scheduling in SoCs Via Linear Programming -- Wireless Sensor Networks -- Designing Wireless Sensor Nodes -- Design, Implementation, and Experiments on Outdoor Deployment of Wireless Sensor Network for Environmental Monitoring -- LATONA: An Advanced Server Architecture for Ubiquitous Sensor Network -- An Approach for the Reduction of Power Consumption in Sensor Nodes of Wireless Sensor Networks: Case Analysis of Mica2 -- Energy-Driven Partitioning of Signal Processing Algorithms in Sensor Networks -- Preamble Sense Multiple Access (PSMA) for Impulse Radio Ultra Wideband Sensor Networks -- Security in Wireless Sensor Networks: Considerations and Experiments -- On Security of PAN Wireless Systems -- Processor Design -- Code Size Reduction by Compiler Tuning -- Energy Optimization of a Multi-bank Main Memory -- Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems -- Hybrid Functional and Instruction Level Power Modeling for Embedded Processors -- Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform -- Software Pipelining Support for Transport Triggered Architecture Processors -- SAD Prefetching for MPEG4 Using Flux Caches -- Effects of Program Compression -- Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors -- Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations -- A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme -- Reducing Execution Unit Leakage Power in Embedded Processors -- Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors -- Advantages of Java Processors in Cache Performance and Power for Embedded Applications -- Dependable Computing -- CARROT – A Tool for Fast and Accurate Soft Error Rate Estimation -- A Scheduling Strategy for a Real-Time Dependable Organic Middleware -- Autonomous Construction Technology of Community for Achieving High Assurance Service -- Preventing Denial-of-Service Attacks in Shared CMP Caches -- Architectures and Implementations -- A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures -- Real-Time Embedded System for Rear-View Mirror Overtaking Car Monitoring -- Design of Asynchronous Embedded Processor with New Ternary Data Encoding Scheme -- Hardware-Based IP Lookup Using n-Way Set Associative Memory and LPM Comparator -- A Flash File System to Support Fast Mounting for NAND Flash Memory Based Embedded Systems -- Rescheduling for Optimized SHA-1 Calculation -- Software Implementation of WiMAX on the Sandbridge SandBlaster Platform -- High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology -- Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box -- Embedded Sensor Systems -- Integrated Microsystems in Industrial Applications -- A Solid-State 2-D Wind Sensor -- Fault-Tolerant Bus System for Airbag Sensors and Actuators. |
| Record Nr. | UNINA-9910484336903321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings / / edited by Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, Stamatis Vassiliadis
| Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings / / edited by Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, Stamatis Vassiliadis |
| Edizione | [1st ed. 2005.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 |
| Descrizione fisica | 1 online resource (XV, 476 p.) |
| Disciplina | 004.2/2 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynote -- Platform Thinking in Embedded Systems -- Reconfigurable System Design and Implementations -- Interprocedural Optimization for Dynamic Hardware Configurations -- Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques -- Reconfigurable Multiple Operation Array -- RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration -- Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping -- Automatic FIR Filter Generation for FPGAs -- Two-Dimensional Fast Cosine Transform for Vector-STA Architectures -- Configurable Computing for High-Security/High-Performance Ambient Systems -- FPL-3E: Towards Language Support for Reconfigurable Packet Processing -- Processor Architectures, Design and Simulation -- Flux Caches: What Are They and Are They Useful? -- First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption -- A Novel JAVA Processor for Embedded Devices -- Formal Specification of a Protocol Processor -- Tuning a Protocol Processor Architecture Towards DSP Operations -- Observations on Power-Efficiency Trends in Mobile Communication Devices -- CORDIC-Augmented Sandbridge Processor for Channel Equalization -- Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic -- Exploiting Intra-function Correlation with the Global History Stack -- Power Efficient Instruction Caches for Embedded Systems -- Micro-architecture Performance Estimation by Formula -- Offline Phase Analysis and Optimization for Multi-configuration Processors -- Hardware Cost Estimation for Application-Specific Processor Design -- Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures -- Generating Stream Based Code from Plain C -- Fast Real-Time Job Selection with Resource Constraints Under Earliest Deadline First -- A Programming Model for an Embedded Media Processing Architecture -- Automatic ADL-Based Assembler Generation for ASIP Programming Support -- Sandbridge Software Tools -- Architectures and Implementations -- A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems -- Pattern Matching Acceleration for Network Intrusion Detection Systems -- Real-Time Stereo Vision on a Reconfigurable System -- Application of Very Fast Simulated Reannealing (VFSR) to Low Power Design -- Compressed Swapping for NAND Flash Memory Based Embedded Systems -- A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms -- A Scalable Embedded JPEG2000 Architecture -- A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design -- Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context -- DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor -- System Level Design, Modeling and Simulation -- Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets -- High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks -- The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models -- Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design Flow -- Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms -- DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context -- SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC -- Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications -- A Case for Visualization-Integrated System-Level Design Space Exploration -- Mixed Virtual/Real Prototypes for Incremental System Design – A Proof of Concept. |
| Record Nr. | UNISA-996465831203316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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