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Autonomic and Trusted Computing [[electronic resource] ] : Third International Conference, ATC 2006, Wuhan, China, September 3-6, 2006 / / edited by Laurence T. Yang, Hai Jin, Theo Ungerer
| Autonomic and Trusted Computing [[electronic resource] ] : Third International Conference, ATC 2006, Wuhan, China, September 3-6, 2006 / / edited by Laurence T. Yang, Hai Jin, Theo Ungerer |
| Edizione | [1st ed. 2006.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 |
| Descrizione fisica | 1 online resource (XVI, 616 p.) |
| Disciplina | 004 |
| Collana | Programming and Software Engineering |
| Soggetto topico |
Computers
Operating systems (Computers) Software engineering Computer communication systems Data encryption (Computer science) Application software Theory of Computation Operating Systems Software Engineering Computer Communication Networks Cryptology Information Systems Applications (incl. Internet) |
| Soggetto non controllato | Trusted computing |
| ISBN | 3-540-38622-X |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynote Speech -- Emergence in Organic Computing Systems: Discussion of a Controversial Concept -- Managing Trust in Distributed Agent Systems -- Track 1: Autonomic/Organic Computing and Communications -- Towards a Standards-Based Autonomic Context Management System -- Formal Modeling and Verification of Systems with Self-x Properties -- A Novel Autonomic Rapid Application Composition Scheme for Ubiquitous Systems -- Autonomic Interference Avoidance with Extended Shortest Path Algorithm -- Multi-level Model-Based Self-diagnosis of Distributed Object-Oriented Systems -- From Components to Autonomic Elements Using Negotiable Contracts -- Self-configuration Via Cooperative Social Behavior -- Towards Ontology-Based Embedded Services -- TOBAB: A Trend-Oriented Bandwidth Adaptive Buffering in Peer-to-Peer Streaming System -- Interference-Aware Selfish Routing in Multi-ratio Multi-channel Wireless Mesh Networks -- Autonomic Group Location Update for Mobile Networks -- Autonomic and Trusted Computing Paradigms -- Autonomic K-Interleaving Construction Scheme for P2P Overlay Networks -- Self Awareness and Adaptive Traffic Signal Control System for Smart World -- Development and Runtime Support for Situation-Aware Security in Autonomic Computing -- Track 2: Trust Models and Trustworthy Systems/Services -- A Social Network-Based Trust Model for the Semantic Web -- Fuzzy Model Tuning for Intrusion Detection Systems -- PATROL-F – A Comprehensive Reputation-Based Trust Model with Fuzzy Subsystems -- An Integration Framework for Trustworthy Transactions -- Daonity: An Experience on Enhancing Grid Security by Trusted Computing Technology -- Toward Trust Management in Autonomic and Coordination Applications -- Bayesian Network Based Trust Management -- An Improved Global Trust Value Computing Method in P2P System -- Trusted Priority Control Design for Information Networks Based on Sociotechnology -- Autonomic Trust Management in a Component Based Software System -- A Risk Assessment Model for Enterprise Network Security -- A Security Management Framework with Roaming Coordinator for Pervasive Services -- A Dynamic Trust Model Based on Feedback Control Mechanism for P2P Applications -- Automatic Composition of Secure Workflows -- TPOD: A Trust-Based Incentive Mechanism for Peer-to-Peer Live Broadcasting -- A Group Based Reputation System for P2P Networks -- An Approach for Trusted Interoperation in a Multidomain Environment -- Extracting Trust from Domain Analysis: A Case Study on the Wikipedia Project -- MTrust: A Reputation-Based Trust Model for a Mobile Agent System -- Ubisafe Computing: Vision and Challenges (I) -- Track 3: Cryptography, Security and Privacy -- Source Authentication of Media Streaming Based on Chains of Iso-hash Clusters -- Self-certified Mutual Authentication and Key Exchange Protocol for Roaming Services -- Remote Authentication with Forward Security -- A Parallel GNFS Algorithm with the Biorthogonal Block Lanczos Method for Integer Factorization -- An Access-Control Policy Based on Sharing Resource Management for a Multi-domains Environment -- Efficient Signcryption Without Random Oracles -- Two Novel Packet Marking Schemes for IP Traceback -- A Novel Rate Limit Algorithm Against Meek DDoS Attacks -- Resistance Analysis to Intruders’ Evasion of a Novel Algorithm to Detect Stepping-Stone -- A New ID-Based Broadcast Encryption Scheme -- Automated Abduction for Computer Forensics -- A Framework for Specifying and Managing Security Requirements in Collaborative Systems -- System Architecture and Economic Value-Chain Models for Healthcare Privacy and Security Control in Large-Scale Wireless Sensor Networks -- On Email Spamming Under the Shadow of Large Scale Use of Identity-Based Encryption -- Zero-Knowledge Proof of Generalized Compact Knapsacks (or A Novel Identification/Signature Scheme) -- Track 4: Reliability, Fault Tolerance and Dependable Systems -- A Real-Time and Reliable Approach to Detecting Traffic Variations at Abnormally High and Low Rates -- A SCORM-Based Caching Strategy for Supporting Ubiquitous Learning Environment -- FTCM: Fault-Tolerant Cluster Management for Cluster-Based DBMS -- Fault-Tolerant Scheduling Based on Periodic Tasks for Heterogeneous Systems -- Active Fault-Tolerant System for Open Distributed Computing -- A Time-Cognizant Dynamic Crash Recovery Scheme Suitable for Distributed Real-Time Main Memory Databases -- An Efficient Fault-Tolerant Digital Signature Scheme Based on the Discrete Logarithm Problem. |
| Record Nr. | UNISA-996466162303316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Autonomic and Trusted Computing : Third International Conference, ATC 2006, Wuhan, China, September 3-6, 2006 / / edited by Laurence T. Yang, Hai Jin, Theo Ungerer
| Autonomic and Trusted Computing : Third International Conference, ATC 2006, Wuhan, China, September 3-6, 2006 / / edited by Laurence T. Yang, Hai Jin, Theo Ungerer |
| Edizione | [1st ed. 2006.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 |
| Descrizione fisica | 1 online resource (XVI, 616 p.) |
| Disciplina | 004 |
| Collana | Programming and Software Engineering |
| Soggetto topico |
Computers
Operating systems (Computers) Software engineering Computer communication systems Data encryption (Computer science) Application software Theory of Computation Operating Systems Software Engineering Computer Communication Networks Cryptology Information Systems Applications (incl. Internet) |
| Soggetto non controllato | Trusted computing |
| ISBN | 3-540-38622-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynote Speech -- Emergence in Organic Computing Systems: Discussion of a Controversial Concept -- Managing Trust in Distributed Agent Systems -- Track 1: Autonomic/Organic Computing and Communications -- Towards a Standards-Based Autonomic Context Management System -- Formal Modeling and Verification of Systems with Self-x Properties -- A Novel Autonomic Rapid Application Composition Scheme for Ubiquitous Systems -- Autonomic Interference Avoidance with Extended Shortest Path Algorithm -- Multi-level Model-Based Self-diagnosis of Distributed Object-Oriented Systems -- From Components to Autonomic Elements Using Negotiable Contracts -- Self-configuration Via Cooperative Social Behavior -- Towards Ontology-Based Embedded Services -- TOBAB: A Trend-Oriented Bandwidth Adaptive Buffering in Peer-to-Peer Streaming System -- Interference-Aware Selfish Routing in Multi-ratio Multi-channel Wireless Mesh Networks -- Autonomic Group Location Update for Mobile Networks -- Autonomic and Trusted Computing Paradigms -- Autonomic K-Interleaving Construction Scheme for P2P Overlay Networks -- Self Awareness and Adaptive Traffic Signal Control System for Smart World -- Development and Runtime Support for Situation-Aware Security in Autonomic Computing -- Track 2: Trust Models and Trustworthy Systems/Services -- A Social Network-Based Trust Model for the Semantic Web -- Fuzzy Model Tuning for Intrusion Detection Systems -- PATROL-F – A Comprehensive Reputation-Based Trust Model with Fuzzy Subsystems -- An Integration Framework for Trustworthy Transactions -- Daonity: An Experience on Enhancing Grid Security by Trusted Computing Technology -- Toward Trust Management in Autonomic and Coordination Applications -- Bayesian Network Based Trust Management -- An Improved Global Trust Value Computing Method in P2P System -- Trusted Priority Control Design for Information Networks Based on Sociotechnology -- Autonomic Trust Management in a Component Based Software System -- A Risk Assessment Model for Enterprise Network Security -- A Security Management Framework with Roaming Coordinator for Pervasive Services -- A Dynamic Trust Model Based on Feedback Control Mechanism for P2P Applications -- Automatic Composition of Secure Workflows -- TPOD: A Trust-Based Incentive Mechanism for Peer-to-Peer Live Broadcasting -- A Group Based Reputation System for P2P Networks -- An Approach for Trusted Interoperation in a Multidomain Environment -- Extracting Trust from Domain Analysis: A Case Study on the Wikipedia Project -- MTrust: A Reputation-Based Trust Model for a Mobile Agent System -- Ubisafe Computing: Vision and Challenges (I) -- Track 3: Cryptography, Security and Privacy -- Source Authentication of Media Streaming Based on Chains of Iso-hash Clusters -- Self-certified Mutual Authentication and Key Exchange Protocol for Roaming Services -- Remote Authentication with Forward Security -- A Parallel GNFS Algorithm with the Biorthogonal Block Lanczos Method for Integer Factorization -- An Access-Control Policy Based on Sharing Resource Management for a Multi-domains Environment -- Efficient Signcryption Without Random Oracles -- Two Novel Packet Marking Schemes for IP Traceback -- A Novel Rate Limit Algorithm Against Meek DDoS Attacks -- Resistance Analysis to Intruders’ Evasion of a Novel Algorithm to Detect Stepping-Stone -- A New ID-Based Broadcast Encryption Scheme -- Automated Abduction for Computer Forensics -- A Framework for Specifying and Managing Security Requirements in Collaborative Systems -- System Architecture and Economic Value-Chain Models for Healthcare Privacy and Security Control in Large-Scale Wireless Sensor Networks -- On Email Spamming Under the Shadow of Large Scale Use of Identity-Based Encryption -- Zero-Knowledge Proof of Generalized Compact Knapsacks (or A Novel Identification/Signature Scheme) -- Track 4: Reliability, Fault Tolerance and Dependable Systems -- A Real-Time and Reliable Approach to Detecting Traffic Variations at Abnormally High and Low Rates -- A SCORM-Based Caching Strategy for Supporting Ubiquitous Learning Environment -- FTCM: Fault-Tolerant Cluster Management for Cluster-Based DBMS -- Fault-Tolerant Scheduling Based on Periodic Tasks for Heterogeneous Systems -- Active Fault-Tolerant System for Open Distributed Computing -- A Time-Cognizant Dynamic Crash Recovery Scheme Suitable for Distributed Real-Time Main Memory Databases -- An Efficient Fault-Tolerant Digital Signature Scheme Based on the Discrete Logarithm Problem. |
| Record Nr. | UNINA-9910484258803321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
High Performance Embedded Architectures and Compilers [[electronic resource] ] : Fourth International Conference, HiPEAC 2009 / / edited by André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : Fourth International Conference, HiPEAC 2009 / / edited by André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XIII, 420 p.) |
| Disciplina | 003.3 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computer arithmetic and logic units Microprocessors Computer architecture Computer input-output equipment Logic design Computer networks Computer System Implementation Arithmetic and Logic Structures Processor Architectures Input/Output and Data Communications Logic Design Computer Communication Networks |
| ISBN | 3-540-92990-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote: Challenges on the Road to Exascale Computing -- Keynote: Compilers in the Manycore Era -- I Dynamic Translation and Optimisation -- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering -- Predictive Runtime Code Scheduling for Heterogeneous Architectures -- Collective Optimization -- High Speed CPU Simulation Using LTU Dynamic Binary Translation -- II Low Level Scheduling -- Integrated Modulo Scheduling for Clustered VLIW Architectures -- Software Pipelining in Nested Loops with Prolog-Epilog Merging -- A Flexible Code Compression Scheme Using Partitioned Look-Up Tables -- III Parallelism and Resource Control -- MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor -- IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor -- A Hardware Task Scheduler for Embedded Video Processing -- Finding Stress Patterns in Microprocessor Workloads -- IV Communication -- Deriving Efficient Data Movement from Decoupled Access/Execute Specifications -- MPSoC Design Using Application-Specific Architecturally Visible Communication -- Communication Based Proactive Link Power Management -- V Mapping for CMPs -- Mapping and Synchronizing Streaming Applications on Cell Processors -- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors -- Accomodating Diversity in CMPs with Heterogeneous Frequencies -- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip -- VI Power -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines -- HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic -- Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures -- VII Cache Issues -- Revisiting Cache Block Superloading -- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors -- In-Network Caching for Chip Multiprocessors -- VIII Parallel Embedded Applications -- Parallel LDPC Decoding on the Cell/B.E. Processor -- Parallel H.264 Decoding on an Embedded Multicore Processor. |
| Record Nr. | UNISA-996466362503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
High Performance Embedded Architectures and Compilers : Fourth International Conference, HiPEAC 2009 / / edited by André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer
| High Performance Embedded Architectures and Compilers : Fourth International Conference, HiPEAC 2009 / / edited by André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XIII, 420 p.) |
| Disciplina | 003.3 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computer arithmetic and logic units Microprocessors Computer architecture Computer input-output equipment Logic design Computer networks Computer System Implementation Arithmetic and Logic Structures Processor Architectures Input/Output and Data Communications Logic Design Computer Communication Networks |
| ISBN | 3-540-92990-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote: Challenges on the Road to Exascale Computing -- Keynote: Compilers in the Manycore Era -- I Dynamic Translation and Optimisation -- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering -- Predictive Runtime Code Scheduling for Heterogeneous Architectures -- Collective Optimization -- High Speed CPU Simulation Using LTU Dynamic Binary Translation -- II Low Level Scheduling -- Integrated Modulo Scheduling for Clustered VLIW Architectures -- Software Pipelining in Nested Loops with Prolog-Epilog Merging -- A Flexible Code Compression Scheme Using Partitioned Look-Up Tables -- III Parallelism and Resource Control -- MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor -- IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor -- A Hardware Task Scheduler for Embedded Video Processing -- Finding Stress Patterns in Microprocessor Workloads -- IV Communication -- Deriving Efficient Data Movement from Decoupled Access/Execute Specifications -- MPSoC Design Using Application-Specific Architecturally Visible Communication -- Communication Based Proactive Link Power Management -- V Mapping for CMPs -- Mapping and Synchronizing Streaming Applications on Cell Processors -- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors -- Accomodating Diversity in CMPs with Heterogeneous Frequencies -- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip -- VI Power -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines -- HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic -- Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures -- VII Cache Issues -- Revisiting Cache Block Superloading -- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors -- In-Network Caching for Chip Multiprocessors -- VIII Parallel Embedded Applications -- Parallel LDPC Decoding on the Cell/B.E. Processor -- Parallel H.264 Decoding on an Embedded Multicore Processor. |
| Record Nr. | UNINA-9910483766303321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
High Performance Embedded Architectures and Compilers [[electronic resource] ] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (297 p.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computer arithmetic and logic units Microprocessors Computer architecture Computer input-output equipment Logic design Computer networks Theory of Computation Arithmetic and Logic Structures Processor Architectures Input/Output and Data Communications Logic Design Computer Communication Networks |
| ISBN | 3-540-69338-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints. |
| Record Nr. | UNISA-996466023003316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
High Performance Embedded Architectures and Compilers [[electronic resource] ] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (297 p.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computer arithmetic and logic units Microprocessors Computer architecture Computer input-output equipment Logic design Computer networks Theory of Computation Arithmetic and Logic Structures Processor Architectures Input/Output and Data Communications Logic Design Computer Communication Networks |
| ISBN | 3-540-69338-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints. |
| Record Nr. | UNINA-9910484914503321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
High Performance Embedded Architectures and Compilers [[electronic resource] ] : First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings / / edited by Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings / / edited by Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer |
| Edizione | [1st ed. 2005.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 |
| Descrizione fisica | 1 online resource (XIV, 318 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer arithmetic and logic units
Computer systems Compilers (Computer programs) Computer input-output equipment Logic design Microprocessors Computer architecture Arithmetic and Logic Structures Computer System Implementation Compilers and Interpreters Input/Output and Data Communications Logic Design Processor Architectures |
| Classificazione | 54.31 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications -- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges -- Software Defined Radio – A High Performance Embedded Challenge -- I Analysis and Evaluation Techniques -- A Practical Method for Quickly Evaluating Program Optimizations -- Efficient Sampling Startup for Sampled Processor Simulation -- Enhancing Network Processor Simulation Speed with Statistical Input Sampling -- II Novel Memory and Interconnect Architectures -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation -- Streaming Sparse Matrix Compression/Decompression -- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs -- III Security Architecture -- Memory-Centric Security Architecture -- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management -- Arc3D: A 3D Obfuscation Architecture -- IV Novel Compiler and Runtime Techniques -- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations -- Induction Variable Analysis with Delayed Abstractions -- Garbage Collection Hints -- V DomainSpecificArchitectures -- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors -- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture -- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems -- A Low-Power DSP-Enhanced 32-Bit EISC Processor. |
| Record Nr. | UNISA-996465731103316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
High Performance Embedded Architectures and Compilers : First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings / / edited by Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer
| High Performance Embedded Architectures and Compilers : First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings / / edited by Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer |
| Edizione | [1st ed. 2005.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 |
| Descrizione fisica | 1 online resource (XIV, 318 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer arithmetic and logic units
Computer systems Compilers (Computer programs) Computer input-output equipment Logic design Microprocessors Computer architecture Arithmetic and Logic Structures Computer System Implementation Compilers and Interpreters Input/Output and Data Communications Logic Design Processor Architectures |
| Classificazione | 54.31 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications -- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges -- Software Defined Radio – A High Performance Embedded Challenge -- I Analysis and Evaluation Techniques -- A Practical Method for Quickly Evaluating Program Optimizations -- Efficient Sampling Startup for Sampled Processor Simulation -- Enhancing Network Processor Simulation Speed with Statistical Input Sampling -- II Novel Memory and Interconnect Architectures -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation -- Streaming Sparse Matrix Compression/Decompression -- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs -- III Security Architecture -- Memory-Centric Security Architecture -- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management -- Arc3D: A 3D Obfuscation Architecture -- IV Novel Compiler and Runtime Techniques -- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations -- Induction Variable Analysis with Delayed Abstractions -- Garbage Collection Hints -- V DomainSpecificArchitectures -- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors -- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture -- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems -- A Low-Power DSP-Enhanced 32-Bit EISC Processor. |
| Record Nr. | UNINA-9910484308803321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Organic and Pervasive Computing -- ARCS 2004 [[electronic resource] ] : International Conference on Architecture of Computing Systems, Augsburg, Germany, March 23-26, 2004, Proceedings / / edited by Christian Müller-Schloer, Theo Ungerer, Bernhard Bauer
| Organic and Pervasive Computing -- ARCS 2004 [[electronic resource] ] : International Conference on Architecture of Computing Systems, Augsburg, Germany, March 23-26, 2004, Proceedings / / edited by Christian Müller-Schloer, Theo Ungerer, Bernhard Bauer |
| Edizione | [1st ed. 2004.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004 |
| Descrizione fisica | 1 online resource (XI, 329 p.) |
| Disciplina | 004.2/2 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Computer networks Software engineering Operating systems (Computers) Information organization Application software Computer System Implementation Computer Communication Networks Software Engineering Operating Systems Information Storage and Retrieval Information Systems Applications (incl. Internet) |
| ISBN |
1-280-30708-0
9786610307081 3-540-24714-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote Autonomic Computing Initiative -- Keynote Multithreading for Low-Cost, Low-Power Applications -- I Organic Computing -- The SDVM: A Self Distributing Virtual Machine for Computer Clusters -- Heterogenous Data Fusion via a Probabilistic Latent-Variable Model -- Self-Stabilizing Microprocessor -- Enforcement of Architectural Safety Guards to Deter Malicious Code Attacks through Buffer Overflow Vulnerabilities -- II Peer-to-Peer -- Latent Semantic Indexing in Peer-to-Peer Networks -- A Taxonomy for Resource Discovery -- Oasis: An Architecture for Simplified Data Management and Disconnected Operation -- Towards a General Approach to Mobile Profile Based Distributed Grouping -- III Reconfigurable Hardware -- A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware -- Definition of a Configurable Architecture for Implementation of Global Cellular Automaton -- RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures -- IV Hardware -- Component-Based Hardware-Software Co-design -- Cryptonite – A Programmable Crypto Processor Architecture for High-Bandwidth Applications -- STAFF: State Transition Applied Fast Flash Translation Layer -- Simultaneously Exploiting Dynamic Voltage Scaling, Execution Time Variations, and Multiple Methods in Energy-Aware Hard Real-Time Scheduling -- V Wireless Architectures and Networking -- Application Characterization for Wireless Network Power Management -- Frame of Interest Approach on Quality of Prediction for Agent-Based Network Monitoring -- Bluetooth Scatternet Formation – State of the Art and a New Approach -- A Note on Certificate Path Verification in Next Generation Mobile Communications -- VI Applications -- The Value of Handhelds in Smart Environments -- Extending the MVC Design Pattern towards a Task-Oriented Development Approach for Pervasive Computing Applications -- Adaptive Workload Balancing for Storage Management Applications in Multi Node Environments. |
| Record Nr. | UNISA-996465549203316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Organic and Pervasive Computing -- ARCS 2004 : International Conference on Architecture of Computing Systems, Augsburg, Germany, March 23-26, 2004, Proceedings / / edited by Christian Müller-Schloer, Theo Ungerer, Bernhard Bauer
| Organic and Pervasive Computing -- ARCS 2004 : International Conference on Architecture of Computing Systems, Augsburg, Germany, March 23-26, 2004, Proceedings / / edited by Christian Müller-Schloer, Theo Ungerer, Bernhard Bauer |
| Edizione | [1st ed. 2004.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004 |
| Descrizione fisica | 1 online resource (XI, 329 p.) |
| Disciplina | 004.2/2 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Computer networks Software engineering Operating systems (Computers) Information organization Application software Computer System Implementation Computer Communication Networks Software Engineering Operating Systems Information Storage and Retrieval Information Systems Applications (incl. Internet) |
| ISBN |
1-280-30708-0
9786610307081 3-540-24714-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote Autonomic Computing Initiative -- Keynote Multithreading for Low-Cost, Low-Power Applications -- I Organic Computing -- The SDVM: A Self Distributing Virtual Machine for Computer Clusters -- Heterogenous Data Fusion via a Probabilistic Latent-Variable Model -- Self-Stabilizing Microprocessor -- Enforcement of Architectural Safety Guards to Deter Malicious Code Attacks through Buffer Overflow Vulnerabilities -- II Peer-to-Peer -- Latent Semantic Indexing in Peer-to-Peer Networks -- A Taxonomy for Resource Discovery -- Oasis: An Architecture for Simplified Data Management and Disconnected Operation -- Towards a General Approach to Mobile Profile Based Distributed Grouping -- III Reconfigurable Hardware -- A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware -- Definition of a Configurable Architecture for Implementation of Global Cellular Automaton -- RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures -- IV Hardware -- Component-Based Hardware-Software Co-design -- Cryptonite – A Programmable Crypto Processor Architecture for High-Bandwidth Applications -- STAFF: State Transition Applied Fast Flash Translation Layer -- Simultaneously Exploiting Dynamic Voltage Scaling, Execution Time Variations, and Multiple Methods in Energy-Aware Hard Real-Time Scheduling -- V Wireless Architectures and Networking -- Application Characterization for Wireless Network Power Management -- Frame of Interest Approach on Quality of Prediction for Agent-Based Network Monitoring -- Bluetooth Scatternet Formation – State of the Art and a New Approach -- A Note on Certificate Path Verification in Next Generation Mobile Communications -- VI Applications -- The Value of Handhelds in Smart Environments -- Extending the MVC Design Pattern towards a Task-Oriented Development Approach for Pervasive Computing Applications -- Adaptive Workload Balancing for Storage Management Applications in Multi Node Environments. |
| Record Nr. | UNINA-9910144205303321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
