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Architecture of Computing Systems – ARCS 2019 [[electronic resource] ] : 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings / / edited by Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck
| Architecture of Computing Systems – ARCS 2019 [[electronic resource] ] : 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings / / edited by Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIX, 335 p. 212 illus., 88 illus. in color.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Operating systems (Computers) Logic design Computer systems Computer input-output equipment Microprocessors Computer architecture Computer Communication Networks Operating Systems Logic Design Computer System Implementation Input/Output and Data Communications Processor Architectures |
| ISBN | 3-030-18656-3 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Dependable Systems -- Hardware/Software Co-designed Security Extensions for Embedded Devices -- SDES - Scalable Software Support for Dependable Embedded Systems -- Real-Time Systems -- Asynchronous Critical Sections in Real-Time Multiprocessor Systems -- Resource-Aware Parameter Tuning for Real-Time Applications -- A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC -- Special Applications -- DSL-based Acceleration of Automotive Environment Perception and Mapping Algorithms for embedded CPUs, GPUs, and FPGAs -- Applying the Concept of Artificial DNA and Hormone System to a Low-Performance Automotive Environment -- A Parallel Adaptive Swarm Search Framework for Solving Black-Box Optimization Problems -- Architecture -- Leros: the Return of the Accumulator Machine -- A Generic Functional Simulation of Heterogeneous Systems -- Evaluating Dynamic Task Scheduling in a Task-based Runtime System for Heterogeneous Architectures -- Dynamic Scheduling of Pipelined Functional Units in Coarse-Grained Reconfigurable Array Elements -- Memory Hierarchy -- CyPhOS { A Component-based Cache-Aware Multi-Core Operating System -- Investigation of L2-Cache interferences in a NXP QorIQ T4240 multicore processor -- MEMPower: Data-Aware GPU Memory Power Model -- FPGA -- Effective FPGA Architecture for General CRC -- Receive-Side Notification for Enhanced RDMA in FPGA Based Networks -- An Efficient FPGA Accelerator Design for Optimized CNNs using OpenCL -- Energy Awareness -- The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures -- A Heterogeneous and Reconfigurable Embedded Architecture for Energy-efficient Execution of Convolutional Neural Networks -- An energy efficient embedded processor for hard real-time Java applications -- NoC/SoC -- A Minimal Network Interface for a Simple Network-on-Chip -- Network Coding in Networks-on-Chip with Lossy Links -- Application Specific Reconfigurable SoC Interconnection Network Architectures. |
| Record Nr. | UNISA-996466197103316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Architecture of Computing Systems – ARCS 2019 : 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings / / edited by Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck
| Architecture of Computing Systems – ARCS 2019 : 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings / / edited by Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIX, 335 p. 212 illus., 88 illus. in color.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Operating systems (Computers) Logic design Computer systems Computer input-output equipment Microprocessors Computer architecture Computer Communication Networks Operating Systems Logic Design Computer System Implementation Input/Output and Data Communications Processor Architectures |
| ISBN | 3-030-18656-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Dependable Systems -- Hardware/Software Co-designed Security Extensions for Embedded Devices -- SDES - Scalable Software Support for Dependable Embedded Systems -- Real-Time Systems -- Asynchronous Critical Sections in Real-Time Multiprocessor Systems -- Resource-Aware Parameter Tuning for Real-Time Applications -- A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC -- Special Applications -- DSL-based Acceleration of Automotive Environment Perception and Mapping Algorithms for embedded CPUs, GPUs, and FPGAs -- Applying the Concept of Artificial DNA and Hormone System to a Low-Performance Automotive Environment -- A Parallel Adaptive Swarm Search Framework for Solving Black-Box Optimization Problems -- Architecture -- Leros: the Return of the Accumulator Machine -- A Generic Functional Simulation of Heterogeneous Systems -- Evaluating Dynamic Task Scheduling in a Task-based Runtime System for Heterogeneous Architectures -- Dynamic Scheduling of Pipelined Functional Units in Coarse-Grained Reconfigurable Array Elements -- Memory Hierarchy -- CyPhOS { A Component-based Cache-Aware Multi-Core Operating System -- Investigation of L2-Cache interferences in a NXP QorIQ T4240 multicore processor -- MEMPower: Data-Aware GPU Memory Power Model -- FPGA -- Effective FPGA Architecture for General CRC -- Receive-Side Notification for Enhanced RDMA in FPGA Based Networks -- An Efficient FPGA Accelerator Design for Optimized CNNs using OpenCL -- Energy Awareness -- The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures -- A Heterogeneous and Reconfigurable Embedded Architecture for Energy-efficient Execution of Convolutional Neural Networks -- An energy efficient embedded processor for hard real-time Java applications -- NoC/SoC -- A Minimal Network Interface for a Simple Network-on-Chip -- Network Coding in Networks-on-Chip with Lossy Links -- Application Specific Reconfigurable SoC Interconnection Network Architectures. |
| Record Nr. | UNINA-9910337841203321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Time-predictable architectures / / Christine Rochange, Sascha Uhrig, Pascal Sainrat
| Time-predictable architectures / / Christine Rochange, Sascha Uhrig, Pascal Sainrat |
| Autore | Rochange Christine |
| Pubbl/distr/stampa | London, England ; ; Hoboken, New Jersey : , : ISTE Ltd : , : John Wiley & Sons, , 2014 |
| Descrizione fisica | 1 online resource (192 p.) |
| Disciplina | 004.33 |
| Altri autori (Persone) |
UhrigSascha
SainratPascal |
| Collana | Focus Computer Engineering Series |
| Soggetto topico |
Real-time data processing
Computer architecture |
| ISBN |
1-118-79026-X
1-118-79022-7 1-118-79013-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Title Page; Contents; Preface; CHAPTER 1. REAL-TIME SYSTEMS AND TIME PREDICTABILITY; 1.1. Real-time systems; 1.1.1. Introduction; 1.1.2. Soft, firm and hard real-time systems; 1.1.3. Safety standards; 1.1.4. Examples; 1.2. Time predictability; 1.3. Book outline; CHAPTER 2. TIMING ANALYSIS OF REAL-TIME SYSTEMS; 2.1. Real-time task scheduling; 2.1.1. Task model; 2.1.2. Objectives of task scheduling algorithms; 2.1.3. Mono-processor scheduling for periodic tasks; 2.1.4. Scheduling sporadic and aperiodic tasks; 2.1.5. Multiprocessor scheduling for periodic tasks; 2.2. Task-level analysis
2.2.1. Flow analysis: identifying possible paths2.2.2. Low-level analysis: determining partial execution times; 2.2.3. WCET computation; 2.2.4. WCET analysis tools; 2.2.5. Alternative approaches to WCET analysis; 2.2.6. Time composability; CHAPTER 3. CURRENT PROCESSOR ARCHITECTURES; 3.1. Pipelining; 3.1.1. Pipeline effects; 3.1.2. Modeling for timing analysis; 3.1.3. Recommendations for predictability; 3.2. Superscalar architectures; 3.2.1. In-order execution; 3.2.2. Out-of-order execution; 3.2.3. Modeling for timing analysis; 3.2.4. Recommendations for predictability; 3.3. Multithreading 3.3.1. Time-predictability issues raised by multithreading3.3.2. Time-predictable example architectures; 3.4. Branch prediction; 3.4.1. State-of-the-art branch prediction; 3.4.2. Branch prediction in real-time systems; 3.4.3. Approaches to branch prediction modeling; CHAPTER 4. MEMORY HIERARCHY; 4.1. Caches; 4.1.1. Organization of cache memories; 4.1.2. Static analysis of the behavior of caches; 4.1.3. Recommendations for timing predictability; 4.2. Scratchpad memories; 4.2.1. Scratchpad RAM; 4.2.2. Data scratchpad; 4.2.3. Instruction scratchpad; 4.3. External memories; 4.3.1. Static RAM 4.3.2. Dynamic RAM4.3.3. Flash memory; CHAPTER 5. MULTICORES; 5.1. Impact of resource sharing on time predictability; 5.2. Timing analysis for multicores; 5.2.1. Analysis of temporal/bandwidth sharing; 5.2.2. Analysis of spatial sharing; 5.3. Local caches; 5.3.1. Coherence techniques; 5.3.2. Discussion on timing analyzability; 5.4. Conclusion; 5.5. Time-predictable architectures; 5.5.1. Uncached accesses to shared data; 5.5.2. On-demand coherent cache; CHAPTER 6. EXAMPLE ARCHITECTURES; 6.1. The multithreaded processor Komodo; 6.1.1. The Komodo architecture; 6.1.2. Integrated thread scheduling 6.1.3. Guaranteed percentage scheduling6.1.4. The jamuth IP core; 6.1.5. Conclusion; 6.2. The JOP architecture; 6.2.1. Conclusion; 6.3. The PRET architecture; 6.3.1. PRET pipeline architecture; 6.3.2. Instruction set extension; 6.3.3. DDR2 memory controller; 6.3.4. Conclusion; 6.4. The multi-issue CarCore processor; 6.4.1. The CarCore architecture; 6.4.2. Layered thread scheduling; 6.4.3. CarCore thread scheduling algorithms; 6.4.4. Conclusion; 6.5. The MERASA multicore processor; 6.5.1. The MERASA architecture; 6.5.2. The MERASA processor core; 6.5.3. Interconnection bus 6.5.4. Memory hierarchy |
| Record Nr. | UNINA-9910138962803321 |
Rochange Christine
|
||
| London, England ; ; Hoboken, New Jersey : , : ISTE Ltd : , : John Wiley & Sons, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Time-predictable architectures / / Christine Rochange, Sascha Uhrig, Pascal Sainrat
| Time-predictable architectures / / Christine Rochange, Sascha Uhrig, Pascal Sainrat |
| Autore | Rochange Christine |
| Pubbl/distr/stampa | London, England ; ; Hoboken, New Jersey : , : ISTE Ltd : , : John Wiley & Sons, , 2014 |
| Descrizione fisica | 1 online resource (192 p.) |
| Disciplina | 004.33 |
| Altri autori (Persone) |
UhrigSascha
SainratPascal |
| Collana | Focus Computer Engineering Series |
| Soggetto topico |
Real-time data processing
Computer architecture |
| ISBN |
1-118-79026-X
1-118-79022-7 1-118-79013-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Title Page; Contents; Preface; CHAPTER 1. REAL-TIME SYSTEMS AND TIME PREDICTABILITY; 1.1. Real-time systems; 1.1.1. Introduction; 1.1.2. Soft, firm and hard real-time systems; 1.1.3. Safety standards; 1.1.4. Examples; 1.2. Time predictability; 1.3. Book outline; CHAPTER 2. TIMING ANALYSIS OF REAL-TIME SYSTEMS; 2.1. Real-time task scheduling; 2.1.1. Task model; 2.1.2. Objectives of task scheduling algorithms; 2.1.3. Mono-processor scheduling for periodic tasks; 2.1.4. Scheduling sporadic and aperiodic tasks; 2.1.5. Multiprocessor scheduling for periodic tasks; 2.2. Task-level analysis
2.2.1. Flow analysis: identifying possible paths2.2.2. Low-level analysis: determining partial execution times; 2.2.3. WCET computation; 2.2.4. WCET analysis tools; 2.2.5. Alternative approaches to WCET analysis; 2.2.6. Time composability; CHAPTER 3. CURRENT PROCESSOR ARCHITECTURES; 3.1. Pipelining; 3.1.1. Pipeline effects; 3.1.2. Modeling for timing analysis; 3.1.3. Recommendations for predictability; 3.2. Superscalar architectures; 3.2.1. In-order execution; 3.2.2. Out-of-order execution; 3.2.3. Modeling for timing analysis; 3.2.4. Recommendations for predictability; 3.3. Multithreading 3.3.1. Time-predictability issues raised by multithreading3.3.2. Time-predictable example architectures; 3.4. Branch prediction; 3.4.1. State-of-the-art branch prediction; 3.4.2. Branch prediction in real-time systems; 3.4.3. Approaches to branch prediction modeling; CHAPTER 4. MEMORY HIERARCHY; 4.1. Caches; 4.1.1. Organization of cache memories; 4.1.2. Static analysis of the behavior of caches; 4.1.3. Recommendations for timing predictability; 4.2. Scratchpad memories; 4.2.1. Scratchpad RAM; 4.2.2. Data scratchpad; 4.2.3. Instruction scratchpad; 4.3. External memories; 4.3.1. Static RAM 4.3.2. Dynamic RAM4.3.3. Flash memory; CHAPTER 5. MULTICORES; 5.1. Impact of resource sharing on time predictability; 5.2. Timing analysis for multicores; 5.2.1. Analysis of temporal/bandwidth sharing; 5.2.2. Analysis of spatial sharing; 5.3. Local caches; 5.3.1. Coherence techniques; 5.3.2. Discussion on timing analyzability; 5.4. Conclusion; 5.5. Time-predictable architectures; 5.5.1. Uncached accesses to shared data; 5.5.2. On-demand coherent cache; CHAPTER 6. EXAMPLE ARCHITECTURES; 6.1. The multithreaded processor Komodo; 6.1.1. The Komodo architecture; 6.1.2. Integrated thread scheduling 6.1.3. Guaranteed percentage scheduling6.1.4. The jamuth IP core; 6.1.5. Conclusion; 6.2. The JOP architecture; 6.2.1. Conclusion; 6.3. The PRET architecture; 6.3.1. PRET pipeline architecture; 6.3.2. Instruction set extension; 6.3.3. DDR2 memory controller; 6.3.4. Conclusion; 6.4. The multi-issue CarCore processor; 6.4.1. The CarCore architecture; 6.4.2. Layered thread scheduling; 6.4.3. CarCore thread scheduling algorithms; 6.4.4. Conclusion; 6.5. The MERASA multicore processor; 6.5.1. The MERASA architecture; 6.5.2. The MERASA processor core; 6.5.3. Interconnection bus 6.5.4. Memory hierarchy |
| Record Nr. | UNINA-9910813510003321 |
|
Rochange Christine
|
||
| London, England ; ; Hoboken, New Jersey : , : ISTE Ltd : , : John Wiley & Sons, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||