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Architecture of Computing Systems -- ARCS 2016 [[electronic resource] ] : 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings / / edited by Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich
| Architecture of Computing Systems -- ARCS 2016 [[electronic resource] ] : 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings / / edited by Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich |
| Edizione | [1st ed. 2016.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 |
| Descrizione fisica | 1 online resource (XX, 402 p. 164 illus.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Computer systems Algorithms Software engineering Application software Computer science Computer Communication Networks Computer System Implementation Software Engineering Computer and Information Systems Applications Theory of Computation |
| ISBN | 3-319-30695-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Configurable and In-Memory Accelerators -- Towards Multicore Performance with Configurable Computing Units -- Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube -- Network-on-Chip and Secure Computing Architectures -- CASCADE: Congestion Aware Switchable Cycle Adaptive Detection Router -- An Alternating Transmission Scheme for Detection Routing based Network-on-Chips -- Exzess: Hardware-based RAM Encryption against Physical Memory Disclosure -- Hardware-Assisted Context Management for Accelerator Virtualization: A Case Study with RSA -- Cache Architectures and Protocols Adaptive Cache Structures -- Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence -- Mapping of Applications on Heterogeneous -- Architectures and Real-Time Tasks on Multiprocessors Generic algorithmic scheme for 2D stencil applications on heterogeneous hybrid machines -- GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing -- Task Variants with Different Scratchpad Memory Consumption in Multi-Task Environments -- Feedback-Based Admission Control for Hard Real-Time Task Allocation under Dynamic Workload on Many-core Systems -- All About Time: Timing, Tracing, and Performance Modeling Data Age Diminution in the Logical Execution Time Model -- Accurate Sample Time Reconstruction for Sensor Data Synchronization -- DiaSys: On-Chip Trace Analysis for Multi-Processor System-on-Chip -- Analysis of Intel's Haswell Microarchitecture Using The ECM Model and Microbenchmarks -- Measurement-Based Probabilistic Timing Analysis for Graphics Processor Units -- Approximate and Energy-Efficient Computing -- Reducing Energy Consumption of Data Transfers using Runtime Data Type Conversion -- Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector -- Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-based Modeling -- Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting -- Allocation: From Memories to FPGA Hardware Modules Reducing NoC and Memory Contention for Manycores -- An Efficient Data Structure for Dynamic Two-Dimensional Reconfiguration -- Organic Computing Systems Runtime Clustering of Similarly Behaving Agents in Open Organic Computing Systems -- Comparison of Dependency Measures for the Detection of Mutual Influences in Organic Computing Systems -- Augmenting the Algorithmic Structure of XCS by Means of Interpolation -- Reliability Aspects in NoCs, Caches, and GPUs Estimation of End-to-end Packet Error Rates for NoC Multicasts -- Protecting Code Regions on Asymmetrically Reliable Caches -- A New Simulation-based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs. |
| Record Nr. | UNISA-996466022303316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Architecture of Computing Systems -- ARCS 2016 : 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings / / edited by Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich
| Architecture of Computing Systems -- ARCS 2016 : 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings / / edited by Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich |
| Edizione | [1st ed. 2016.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 |
| Descrizione fisica | 1 online resource (XX, 402 p. 164 illus.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Computer systems Algorithms Software engineering Application software Computer science Computer Communication Networks Computer System Implementation Software Engineering Computer and Information Systems Applications Theory of Computation |
| ISBN | 3-319-30695-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Configurable and In-Memory Accelerators -- Towards Multicore Performance with Configurable Computing Units -- Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube -- Network-on-Chip and Secure Computing Architectures -- CASCADE: Congestion Aware Switchable Cycle Adaptive Detection Router -- An Alternating Transmission Scheme for Detection Routing based Network-on-Chips -- Exzess: Hardware-based RAM Encryption against Physical Memory Disclosure -- Hardware-Assisted Context Management for Accelerator Virtualization: A Case Study with RSA -- Cache Architectures and Protocols Adaptive Cache Structures -- Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence -- Mapping of Applications on Heterogeneous -- Architectures and Real-Time Tasks on Multiprocessors Generic algorithmic scheme for 2D stencil applications on heterogeneous hybrid machines -- GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing -- Task Variants with Different Scratchpad Memory Consumption in Multi-Task Environments -- Feedback-Based Admission Control for Hard Real-Time Task Allocation under Dynamic Workload on Many-core Systems -- All About Time: Timing, Tracing, and Performance Modeling Data Age Diminution in the Logical Execution Time Model -- Accurate Sample Time Reconstruction for Sensor Data Synchronization -- DiaSys: On-Chip Trace Analysis for Multi-Processor System-on-Chip -- Analysis of Intel's Haswell Microarchitecture Using The ECM Model and Microbenchmarks -- Measurement-Based Probabilistic Timing Analysis for Graphics Processor Units -- Approximate and Energy-Efficient Computing -- Reducing Energy Consumption of Data Transfers using Runtime Data Type Conversion -- Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector -- Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-based Modeling -- Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting -- Allocation: From Memories to FPGA Hardware Modules Reducing NoC and Memory Contention for Manycores -- An Efficient Data Structure for Dynamic Two-Dimensional Reconfiguration -- Organic Computing Systems Runtime Clustering of Similarly Behaving Agents in Open Organic Computing Systems -- Comparison of Dependency Measures for the Detection of Mutual Influences in Organic Computing Systems -- Augmenting the Algorithmic Structure of XCS by Means of Interpolation -- Reliability Aspects in NoCs, Caches, and GPUs Estimation of End-to-end Packet Error Rates for NoC Multicasts -- Protecting Code Regions on Asymmetrically Reliable Caches -- A New Simulation-based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs. |
| Record Nr. | UNINA-9910483949703321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
CODES+ISSS 2007 : Embedded Systems Week 2007 : International Conference on Hardware/Software Codesign and System Synthesis : Sept. 30 - Oct. 3, 2007, Salzburg, Austria
| CODES+ISSS 2007 : Embedded Systems Week 2007 : International Conference on Hardware/Software Codesign and System Synthesis : Sept. 30 - Oct. 3, 2007, Salzburg, Austria |
| Autore | Ha Soonhoi |
| Pubbl/distr/stampa | [Place of publication not identified], : ACM, 2007 |
| Descrizione fisica | 1 online resource (266 pages) |
| Collana | ACM Conferences |
| Soggetto topico |
Electrical & Computer Engineering
Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | CODES+ISSS '07 |
| Record Nr. | UNINA-9910138565603321 |
Ha Soonhoi
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| [Place of publication not identified], : ACM, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
CODES+ISSS 2007 : Embedded Systems Week 2007 : International Conference on Hardware/Software Codesign and System Synthesis : Sept. 30 - Oct. 3, 2007, Salzburg, Austria
| CODES+ISSS 2007 : Embedded Systems Week 2007 : International Conference on Hardware/Software Codesign and System Synthesis : Sept. 30 - Oct. 3, 2007, Salzburg, Austria |
| Autore | Ha Soonhoi |
| Pubbl/distr/stampa | [Place of publication not identified], : ACM, 2007 |
| Descrizione fisica | 1 online resource (266 pages) |
| Collana | ACM Conferences |
| Soggetto topico |
Electrical & Computer Engineering
Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | CODES+ISSS '07 |
| Record Nr. | UNISA-996199660303316 |
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Ha Soonhoi
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| [Place of publication not identified], : ACM, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Handbook of Hardware/Software Codesign [[electronic resource] /] / edited by Soonhoi Ha, Jürgen Teich
| Handbook of Hardware/Software Codesign [[electronic resource] /] / edited by Soonhoi Ha, Jürgen Teich |
| Pubbl/distr/stampa | Dordrecht : , : Springer Netherlands : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (1100 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Software engineering Microprocessors Electronics Microelectronics Circuits and Systems Software Engineering Processor Architectures Electronics and Microelectronics, Instrumentation |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to HW/SW Codesign -- Models and Languages for Codesign -- Hardware/Software Partitioning and Scheduling -- HW/SW Cosimulation and Prototyping -- Design Space Exploration -- Performance Estimation and Verification -- Hardware/Software synthesis -- Codesign Tools and Environments -- Case Studies. |
| Record Nr. | UNINA-9910337620303321 |
| Dordrecht : , : Springer Netherlands : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Invasive Computing for Mapping Parallel Programs to Many-Core Architectures / / by Andreas Weichslgartner, Stefan Wildermann, Michael Glaß, Jürgen Teich
| Invasive Computing for Mapping Parallel Programs to Many-Core Architectures / / by Andreas Weichslgartner, Stefan Wildermann, Michael Glaß, Jürgen Teich |
| Autore | Weichslgartner Andreas |
| Edizione | [1st ed. 2018.] |
| Pubbl/distr/stampa | Singapore : , : Springer Singapore : , : Imprint : Springer, , 2018 |
| Descrizione fisica | 1 online resource (XXII, 164 p. 80 illus., 77 illus. in color.) |
| Disciplina | 005.275 |
| Collana | Computer Architecture and Design Methodologies |
| Soggetto topico |
Electronic circuits
Microprocessors Circuits and Systems Processor Architectures Electronic Circuits and Devices |
| ISBN | 981-10-7356-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Invasive Computing -- Fundamentals -- Self-Embedding -- Hybrid Application Mapping -- Hybrid Mapping for Increased Security -- Conclusions and Future Work. |
| Record Nr. | UNINA-9910299898603321 |
|
Weichslgartner Andreas
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| Singapore : , : Springer Singapore : , : Imprint : Springer, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Modeling and Simulation of Invasive Applications and Architectures / / by Sascha Roloff, Frank Hannig, Jürgen Teich
| Modeling and Simulation of Invasive Applications and Architectures / / by Sascha Roloff, Frank Hannig, Jürgen Teich |
| Autore | Roloff Sascha |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Singapore : , : Springer Singapore : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XV, 168 p. 68 illus., 49 illus. in color.) |
| Disciplina | 621.3815 |
| Collana | Computer Architecture and Design Methodologies |
| Soggetto topico |
Electronic circuits
Microprocessors Circuits and Systems Processor Architectures Electronic Circuits and Devices |
| ISBN | 981-13-8387-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Fundamentals -- InvadeSIM–A Simulation Framework for Invasive Parallel Programs and Architectures -- Hybrid Network-on-Chip Simulation -- Parallel MPSoC Simulation and Architecture Evaluation -- ActorX10 and Run-Time Application Embedding -- Conclusions and Future Directions. |
| Record Nr. | UNINA-9910350293803321 |
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Roloff Sascha
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| Singapore : , : Springer Singapore : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Symbolic Parallelization of Nested Loop Programs / / by Alexandru-Petru Tanase, Frank Hannig, Jürgen Teich
| Symbolic Parallelization of Nested Loop Programs / / by Alexandru-Petru Tanase, Frank Hannig, Jürgen Teich |
| Autore | Tanase Alexandru-Petru |
| Edizione | [1st ed. 2018.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 |
| Descrizione fisica | 1 online resource (184 pages) : illustrations (some color) |
| Disciplina | 005.275 |
| Soggetto topico |
Electronic circuits
Microprocessors Electronics Microelectronics Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
| ISBN | 3-319-73909-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Fundamentals and Compiler Framework -- Symbolic Parallelization -- Symbolic Multi‐level Parallelization -- On‐demand Fault‐tolerant Loop Processing -- Conclusions. |
| Record Nr. | UNINA-9910299944003321 |
|
Tanase Alexandru-Petru
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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