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CAD for Hardware Security [[electronic resource] /] / by Farimah Farahmandi, M. Sazadur Rahman, Sree Ranjani Rajendran, Mark Tehranipoor
| CAD for Hardware Security [[electronic resource] /] / by Farimah Farahmandi, M. Sazadur Rahman, Sree Ranjani Rajendran, Mark Tehranipoor |
| Autore | Farahmandi Farimah |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (415 pages) |
| Disciplina | 005.8 |
| Soggetto topico |
Electronic circuits
Internet of things Microprocessors Computer architecture Electronic Circuits and Systems Internet of Things Processor Architectures |
| Soggetto non controllato | Mathematics |
| ISBN | 3-031-26896-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- CAD for Information Leakage Assessment -- CAD for Power Side Channel Leakage Assessment -- CAD for Electromagnetic Radiation Leakage Assessment -- CAD for Timing Leakage Assessment -- CAD for Fault Injection Attack Analysis -- CAD for Obfuscation -- CAD for Watermarking -- CAD for HW Metering -- CAD for Detecting HLS Vulnerabilities -- CAD for Counterfeit Detection and Prevention -- CAD for Trojan Detection and Prevention -- CAD for Physical Assurance -- CAD for Anti-Probing -- CAD for Formal Security Verification -- CAD for Reverse Engineering. |
| Record Nr. | UNINA-9910726295403321 |
Farahmandi Farimah
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Hardware IP Security and Trust [[electronic resource] /] / edited by Prabhat Mishra, Swarup Bhunia, Mark Tehranipoor
| Hardware IP Security and Trust [[electronic resource] /] / edited by Prabhat Mishra, Swarup Bhunia, Mark Tehranipoor |
| Edizione | [1st ed. 2017.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017 |
| Descrizione fisica | 1 online resource (XII, 353 p. 131 illus., 78 illus. in color.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Data encryption (Computer science) Computer security Electronics Microelectronics Microprocessors Circuits and Systems Cryptology Systems and Data Security Electronics and Microelectronics, Instrumentation Processor Architectures |
| ISBN | 3-319-49025-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Part I. Introduction -- Chapter 1.Security and Trust Vulnerabilities in Third-party IPs -- PArt II.Trust Analysis -- Chapter 2.Security Rule Check -- Chapter 3.Digital Circuit Vulnerabilities to Hardware Trojans -- Chapter 4.Code Coverage Analysis for IP Trust Verification -- Chapter 5.Analyzing Circuit Layout to Probing Attack -- Chapter 6.Testing of Side Channel Leakage of Cryptographic IPs: Metrics and Evaluations -- Part III -- Effective Countermeasures -- Chapter 7.Hardware Hardening Approaches using Camouflaging, Encryption and Obfuscation -- Chapter 8.A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Passive Side Channel Attacks -- Part IV -- Chapter 9.Validation of IP Security and Trust -- Chapter 10.IP Trust Validation using Proof-carrying Hardware -- Chapter 11. Hardware Trust Verification -- Chapter 12.Verification of Unspecified IP Functionality -- Chapter 13.Verifying Security Properties in Modern SoCs using Instruction-level Abstractions -- Chapter 14. Test Generation for Detection of Malicious Parametric Variations -- Part V. Conclusions -- Chapter 15.The Future of Trustworthy SoC Design. |
| Record Nr. | UNINA-9910157473003321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Understanding Logic Locking [[electronic resource] /] / by Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor
| Understanding Logic Locking [[electronic resource] /] / by Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor |
| Autore | Zamiri Azar Kimia |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (385 pages) |
| Disciplina | 005.8 |
| Altri autori (Persone) |
Mardani KamaliHadi
FarahmandiFarimah TehranipoorMark |
| Soggetto topico |
Electronic circuit design
Embedded computer systems Electronic circuits Electronics Design and Verification Embedded Systems Electronic Circuits and Systems |
| ISBN | 3-031-37989-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Basics of VLSI Design -- Basics of VLSI Testing and Debug -- IP Protection in VLSI Design: A Historical View -- Making a Case for Logic Locking -- Fundamentals of Logic Locking -- Infrastructure around Logic Locking -- Impact of Satisfiability Solvers on Logic Locking -- Post-Satisfiability Era: Countermeasures and Threats -- Design-for-Testability and its Impact on Logic Locking -- Emergence of Cutting-edge Technologies on Logic Locking -- Logic Locking in Future IC Supply Chain Environments -- Multilayer Approach to Logic Locking -- A Step-by-Step Guide for Protecting/Locking Your IP -- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP. |
| Record Nr. | UNINA-9910760263503321 |
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Zamiri Azar Kimia
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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