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Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog / / by Vaibbhav Taraate
Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog / / by Vaibbhav Taraate
Autore Taraate Vaibbhav
Edizione [1st ed. 2019.]
Pubbl/distr/stampa Singapore : , : Springer Singapore : , : Imprint : Springer, , 2019
Descrizione fisica 1 online resource (xxi, 307 pages)
Disciplina 621.3815
Soggetto topico Electronic circuits
Microprogramming 
Logic design
Circuits and Systems
Control Structures and Microprogramming
Logic Design
ISBN 981-10-8776-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.
Record Nr. UNINA-9910337620903321
Taraate Vaibbhav  
Singapore : , : Springer Singapore : , : Imprint : Springer, , 2019
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
ASIC design and synthesis : RTL design using Verilog / / Vaibbhav Taraate
ASIC design and synthesis : RTL design using Verilog / / Vaibbhav Taraate
Autore Taraate Vaibbhav
Edizione [1st ed. 2021.]
Pubbl/distr/stampa Singapore : , : Springer, , [2021]
Descrizione fisica 1 online resource (XXI, 330 p. 311 illus., 184 illus. in color.)
Disciplina 621.395
Soggetto topico Application-specific integrated circuits - Design
Verilog (Computer hardware description language)
ISBN 981-334-642-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.
Record Nr. UNINA-9910483227103321
Taraate Vaibbhav  
Singapore : , : Springer, , [2021]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Digital design from the VLSI perspective : concepts for VLSI beginners / / Vaibbhav Taraate
Digital design from the VLSI perspective : concepts for VLSI beginners / / Vaibbhav Taraate
Autore Taraate Vaibbhav
Pubbl/distr/stampa Singapore : , : Springer, , [2023]
Descrizione fisica 1 online resource (309 pages)
Disciplina 621.3815
Soggetto topico Digital integrated circuits - Design and construction
Integrated circuits - Very large scale integration
Digital integrated circuits
ISBN 9789811946523
9789811946516
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Acknowledgements -- Contents -- About the Author -- 1 Introduction -- 1.1 Number Representation -- 1.2 Digital Systems: System Perspective -- 1.3 Processors and Their Role -- 1.4 The Important Terminology: System Perspective -- 1.5 System Design Components -- 1.6 Few Important Considerations -- 1.7 Summary -- 2 Basics of Design Elements -- 2.1 Combinational Design Elements -- 2.1.1 Logic Gates and Their Use in the Design -- 2.2 De Morgen's Theorems -- 2.2.1 NAND is Equal to Bubbled OR -- 2.2.2 NOR is Equal to Bubbled and -- 2.3 Level Versus Edge Sensitive Elements -- 2.3.1 Latches and Their Use in the Design -- 2.3.2 Edge Sensitive Elements and Their Role -- 2.4 Summary -- 3 System and Architecture Design -- 3.1 Architecture of the Design -- 3.2 Micro-Architecture of the Design -- 3.3 System Design Architecture -- 3.4 Design for the Glue Logic -- 3.5 Application of 2-variable Karnaugh Maps -- 3.6 Let Us Design Two Variable Function -- 3.7 SOP Terms and Boolean Expression -- 3.8 POS Terms and Expression -- 3.9 Design of Glue or Combinational Using Minimum Logic Gates -- 3.10 Summary -- 4 Combinational Logic and Design Techniques -- 4.1 Let Us Design Few Boolean Functions -- 4.2 Arithmetic Resources -- 4.2.1 Half Adder -- 4.2.2 Half Subtractor -- 4.2.3 Full Adder -- 4.2.4 Full Adder Using Half Adders -- 4.3 Role of Data Control Elements -- 4.4 The Multi-Bit Adder and Subtractor -- 4.5 The Multi-Bit Adder with Area Optimization -- 4.6 3-Variable K-Map and Code Converters -- 4.6.1 3-bit Binary to Gray Code Converter -- 4.6.2 3-Bit Gray to Binary Code Converter -- 4.7 Summary -- 5 Data Control Elements and Applications -- 5.1 Data and Control Paths in Design -- 5.2 Multiplexers to Control the Data -- 5.3 Lowest Order Mux in the Design -- 5.4 The 2:1 MUX Using NAND -- 5.5 The 4:1 MUX -- 5.6 The Design of 4:1 Mux Using 2:1 Mux.
5.7 Design Using Multiplexers -- 5.7.1 NOT Using 2:1 Mux -- 5.7.2 NAND Using Mux -- 5.7.3 NOR Using 2:1 Mux -- 5.7.4 Design of XOR Gate to Get the SUM Output Using Mux -- 5.7.5 Design of XNOR Gate to Get the Even Parity -- 5.8 Boolean Functions and Implementation Using Mux -- 5.9 Mux as Universal Logic -- 5.10 Summary -- 6 Decoders and Encoders -- 6.1 Demultiplexers and Use in the Design -- 6.2 Decoder 2 to 4 Having Active High Output -- 6.3 Decoder 2 to 4 Having Active Low Output -- 6.4 Design for the Given Specifications -- 6.5 Design of 3:8 Encoder Using 2:4 Decoders -- 6.6 Encoders and Their Applications -- 6.7 Practical Encoder Design -- 6.8 Priority Encoders -- 6.9 Practical Design Scenario -- 6.10 Summary -- 7 Combinational Design Scenarios -- 7.1 Mux-Based Designs and Optimization -- 7.2 Right and Left Shift Using Multiplexers -- 7.3 Design of 8:1 Mux Using 4:1 Mux -- 7.4 Design of 8:1 Mux Using 2:1 Mux -- 7.5 Boolean Expression from the Logic -- 7.6 Boolean Expression for Mux-Based Design -- 7.7 Stuck at Faults -- 7.8 Design Using Decoders -- 7.9 Design Using Decoder and NAND Gates -- 7.10 Summary -- 8 Synchronous Sequential Design -- 8.1 Sequential Design Elements -- 8.2 Synchronous Design -- 8.3 Why to Use Synchronous Design? -- 8.4 Asynchronous Design -- 8.4.1 D Flip-Flop and Use in the Design -- 8.5 Design of the Synchronous Counters -- 8.6 Design of the Synchronous Down-Counters -- 8.7 Design of the Synchronous Gray Counter -- 8.8 Few Important Guidelines -- 8.9 Summary -- 9 Logic Design Scenarios and Objectives -- 9.1 What is Asynchronous Design? -- 9.2 Synchronous Versus Asynchronous Reset -- 9.2.1 D Flip-Flop Having Asynchronous Reset -- 9.2.2 Synchronous Reset D Flip_flop -- 9.3 Asynchronous MOD Counters -- 9.3.1 Frequency Divider Network -- 9.3.2 Ripple Counter Design -- 9.4 Design Scenario -- 9.5 PIPO Register.
9.6 Shift Register -- 9.6.1 Shift Operation and Clock Cycles -- 9.7 Bidirectional Shift Register -- 9.8 Important Design Guidelines -- 9.9 Summary -- 10 Sequential Design Scenarios -- 10.1 Design Scenario I -- 10.2 Four-Bit Latch -- 10.3 Positive Edge Sensitive Flip-Flop Using Multiplexers -- 10.4 Flip-Flop Negative Edge Sensitive -- 10.5 Timing Sequence of Design -- 10.6 Load and Shift Register -- 10.7 Design Scenario II -- 10.8 Design Scenario III -- 10.9 Design Scenario III -- 10.10 Design Scenario IV -- 10.11 Design of 4-bit Ring Counter -- 10.12 Design of 4-bit Johnson Counter -- 10.13 Duty Cycle Control -- 10.13.1 Counter Design with 50% Duty Cycle -- 10.14 Summary -- 11 Timing Parameters and Maximum Frequency Calculations -- 11.1 What is Delay in the System? -- 11.1.1 Cascade Logic Elements in Design -- 11.1.2 Parallel Logic Elements in Design -- 11.2 How Delays Affect the Performance of the Design? -- 11.3 Sequential Circuit and Timing Parameters -- 11.4 Timing Paths in Design -- 11.4.1 Input to Register Path -- 11.4.2 Register to Output Path -- 11.4.3 Register to Register Path -- 11.4.4 Input to Output Path -- 11.5 Maximum Frequency Calculations -- 11.5.1 Design 1: Toggle Flip-Flop -- 11.5.2 Design II: The 2-bit Synchronous Up-Counter -- 11.6 Maximum Operating Frequency -- 11.6.1 Maximum Operating Frequency for Synchronous Designs -- 11.7 Clock Skew -- 11.7.1 Positive Clock Skew and Maximum Operating Frequency -- 11.7.2 Negative Clock Skew and Maximum Operating Frequency for the Design -- 11.8 VLSI Specific Scenarios -- 11.8.1 VLSI Specific Design Scenario I -- 11.8.2 VLSI Specific Design Scenario II -- 11.9 Hold Slack -- 11.9.1 VLSI Specific Design Scenario III -- 11.10 Summary -- 12 FSM Designs -- 12.1 Introduction to FSM -- 12.1.1 Moore FSM -- 12.1.2 Mealy FSM -- 12.1.3 Moore Versus Mealy FSM -- 12.2 State Encoding Methods.
12.3 Moore FSM Design -- 12.4 Mealy FSM Design -- 12.5 Applications and Design Strategies -- 12.6 State Diagrams -- 12.6.1 Moore Machine State Diagram -- 12.6.2 Mealy Machine State Diagram -- 12.7 Summary -- 13 Design of Sequence Detectors -- 13.1 Moore Machine Non-overlapping 101 Sequence Detector -- 13.2 Mealy Machine Non-overlapping 101 Sequence Detector -- 13.3 One-Hot Encoding -- 13.4 FSM Area and Power Optimization -- 13.5 Moore Sequence Detector for 101 Overlapping Sequence -- 13.6 Mealy Sequence Detector for 101 Overlapping Sequence -- 13.7 Mealy Sequence Detector for 1010 Overlapping Sequence -- 13.8 Various Paths in the Design -- 13.9 Data and Control Path Design Techniques -- 13.10 Summary -- 14 Performance Improvement for the Design -- 14.1 What Is Design Performance? -- 14.2 How to Use the Minimum Arithmetic Resources -- 14.3 Multibit Adders and Subtractors -- 14.4 Four-Bit Full Adder -- 14.4.1 4-Bit Full Subtractor -- 14.4.2 4-Bit Adder and Subtractor -- 14.4.3 Area Optimization of 4-Bit Adder and Subtractor -- 14.4.4 Optimization of Design Using Only Adders -- 14.4.5 Optimization by Tweaking the Logic to Have Least Area and Least Power -- 14.5 Optimization of the Design for Least Area and Power -- 14.6 Comparators and Parity Detectors with Lesser Area -- 14.6.1 Binary Comparator Design with Least Area -- 14.6.2 Parity Detector Design with Least Area -- 14.7 Processor Designs and Speed Improvement Techniques (Source: www.onerupeest.com) -- 14.8 Avoid Asynchronous Designs to Improve the Speed -- 14.9 Power Improvement -- 14.9.1 Gated Clocks and Dynamic Power Reduction -- 14.10 Summary -- 15 Optimization Techniques -- 15.1 Let Us Understand About the Area Optimization -- 15.2 Arithmetic Resource Sharing -- 15.3 Resource Sharing for Sequential Circuits -- 15.4 Logic Duplications -- 15.5 Design Scenario: Performance Improvement.
15.6 Use of Pipelining in Design -- 15.6.1 Design Without Pipelining -- 15.6.2 Speed Improvement Using Register Balancing or Pipelining -- 15.7 Power Improvement of Design -- 15.8 Dynamic Power Reduction -- 15.9 Summary -- 16 Case Study: Speed Improvement for the Design -- 16.1 Case Study: Speed Improvement at Logic-Level Case Study -- 16.2 Speed Improvement at Architecture Level (Source: www.onerupeest.com) -- 16.2.1 Top-Level Pin Interface -- 16.2.2 Pin Description -- 16.2.3 Case Study: Micro-architecture Design -- 16.3 Summary -- 17 Case Study: Multiple Clock Domains and FIFO Architecture Design -- 17.1 Single Clock Domain Designs -- 17.2 Multiple Clock Domain Designs -- 17.3 Metastability -- 17.4 Control Path Synchronizer -- 17.5 Data Path Synchronizers -- 17.5.1 Why We Need FIFO? -- 17.5.2 FIFO Depth Calculation -- 17.5.3 Case Study: FIFO as a Data Path Synchronizer -- 17.5.4 Micro-architecture of FIFO -- 17.6 Design Guidelines -- 17.7 Summary -- 18 Hardware Description for Design -- 18.1 Verilog HDL -- 18.2 Use of Continuous Assignments -- 18.3 The always Procedural Block -- 18.4 The Procedural Block always@* -- 18.5 Use of the case Construct -- 18.6 Continuous Versus Procedural Assignments -- 18.7 Multiple Blocking Assignments Within the always Block -- 18.8 Design Scenario I: Blocking Assignments -- 18.9 Non-blocking Assignments -- 18.10 Design Scenario II: Example Using Non-blocking Assignments -- 18.11 The 4-bit Register -- 18.12 Asynchronous Reset -- 18.13 Synchronous Reset -- 18.14 Design Guidelines and Summary -- 19 FPGA Architecture and Design Flow -- 19.1 Basics of Programmable Logic -- 19.2 CPLD Versus FPGA -- 19.3 ASIC Versus FPGA -- 19.4 FPGA Architecture -- 19.5 FPGA Design Flow -- 19.5.1 Design Planning -- 19.5.2 RTL Design -- 19.5.3 Design Verification and Synthesis -- 19.5.4 Design Implementation.
19.5.5 Device Programming and Testing.
Record Nr. UNINA-9910627238803321
Taraate Vaibbhav  
Singapore : , : Springer, , [2023]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Digital Design Techniques and Exercises : A Practice Book for Digital Logic Design
Digital Design Techniques and Exercises : A Practice Book for Digital Logic Design
Autore Taraate Vaibbhav
Pubbl/distr/stampa Singapore : , : Springer Singapore Pte. Limited, , 2022
Descrizione fisica 1 online resource (204 pages)
Soggetto genere / forma Electronic books.
ISBN 9789811659553
9789811659546
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Acknowledgements -- Contents -- About the Author -- 1 Basics of Digital Design -- 1.1 Digital Logic and the Evolution -- 1.2 The Important Considerations -- 1.2.1 Area of the Design -- 1.2.2 Speed of the Design -- 1.2.3 Power -- 1.3 Logic Gates -- 1.4 De Morgan's Theorems -- 1.4.1 NAND is Equal to Bubbled OR -- 1.4.2 NOR is Equal to Bubbled AND -- 1.5 Multiplexer as Universal Logic -- 1.6 Optimization Goals and Applications in VLSI Context -- 1.7 Exercises -- 1.7.1 Exercise 1: Use of the Logical Expressions to Get the Logic Equivalent -- 1.7.2 Exercise 2: Cascade Logic and How to Get Logic Expression? -- 1.7.3 Exercise 3: Complement Logic -- 1.7.4 Exercise 4: Logic Expression for the Cascade Logic -- 1.7.5 Exercise 5: Output Expression for the Cascade Logic -- 1.7.6 Exercise 6: Propagation Delay for the Cascade Logic -- 1.7.7 Exercise 7: Logic Gate Output Expression -- 1.7.8 Exercise 8: Propagation Delay for the Cascade Logic -- 1.7.9 Exercise 9: The Equivalent Logic Expression -- 1.7.10 Exercise 10: The Equivalent Logic Gate -- 1.8 Important Takeaways -- 2 Design Using Universal Logic -- 2.1 What Is Universal Logic? -- 2.2 Universal Gates -- 2.2.1 NAND -- 2.2.2 NOR -- 2.2.3 Other Application-Specific Universal Gates -- 2.3 Multiplexers -- 2.3.1 Design Using 2:1 Mux -- 2.3.2 4:1 MUX Using 2:1 Mux -- 2.3.3 Design Using Multiplexers -- 2.4 Exercises -- 2.4.1 Exercise 1: Design Using Universal Gates -- 2.4.2 Exercise 2: Design Using the MUX -- 2.4.3 Exercise 3: Design Using MUX -- 2.4.4 Exercise 4: Design Using Custom Gates -- 2.4.5 Exercise 5: Optimization Exercise -- 2.4.6 Exercise 7: Design Using the MUX -- 2.4.7 Exercise 8: Design Using MUX -- 2.4.8 Exercise 9: Design Using Custom Gates -- 2.5 Applications and Use in VLSI Context -- 2.6 Important Takeaways -- 3 Combinational Design Resources -- 3.1 Code Converters.
3.1.1 Three-Bit Binary-to-Gray Code Converter -- 3.1.2 3-Bit Gray-to-Binary Code Converter -- 3.2 Arithmetic Resources -- 3.2.1 Half-Adder -- 3.2.2 Half-Subtractor -- 3.2.3 Full-Adder -- 3.3 Use of Arithmetic Resources in the Design -- 3.4 Design Using Arithmetic Resources and Control Elements -- 3.5 Optimization Goals -- 3.6 Processor Logic and Need of Arithmetic Resources -- 3.7 Exercises -- 3.7.1 Exercise 1: Cascade Versus Parallel Logic -- 3.7.2 Exercise 2: Delay of the Design -- 3.7.3 Exercise 3: Speed -- 3.7.4 Exercise 4: Design to perform the Addition and Subtraction -- 3.7.5 Exercise 4: Design with the Goal to Use Resource Sharing -- 3.8 Important Takeaways -- 4 Case Study: ALU Design -- 4.1 Design Specifications and Their Role -- 4.2 What Is ALU? -- 4.3 Arithmetic Unit Design -- 4.3.1 Resources Required -- 4.3.2 How to Start Design of ALU? -- 4.3.3 How to Design the Logic -- 4.3.4 Exercise 1: Optimization of the Arithmetic Unit -- 4.3.5 Logic Unit Design -- 4.3.6 Resources Required -- 4.3.7 How to Design the Logic Unit to have Better Area? -- 4.4 ALU Design -- 4.4.1 Resource Requirement and How to Design Efficient ALU? -- 4.4.2 ALU Design to have Better Area -- 4.4.3 Exercise 2: Optimization of ALU -- 4.5 Few Important Design Guidelines -- 4.6 Important Takeaways -- 5 Practical Scenarios and the Design Techniques -- 5.1 Parallel Logic -- 5.1.1 Decoder 2 to 4 -- 5.2 Encoder -- 5.3 Encoder with Invalid Output Detection Logic -- 5.4 Exercises -- 5.4.1 Exercise 1: Design of Decoder Having Active-Low Output -- 5.4.2 Exercise 2: Design the Function Using Decoder -- 5.4.3 Exercise 3: Design Using Decoders -- 5.4.4 Exercise 4: Design Using Decoder and NAND Gates -- 5.4.5 Exercise 5: Design Using Decoders -- 5.4.6 Exercise 6: Priority Encoder Design -- 5.5 Important Takeaways -- 6 Basics of the Sequential Design.
6.1 What Is Sequential Logic Design? -- 6.2 Sequential Design Elements -- 6.3 Level Versus Edge-Triggered Logic -- 6.4 Latches and Their Use in the Design -- 6.4.1 Positive-Level-Sensitive D Latch -- 6.4.2 Negative-Level-Sensitive D Latch -- 6.5 Edge-Sensitive Elements and Their Role -- 6.5.1 Positive Edge-Sensitive D Flip-Flop -- 6.5.2 Negative Edge-Sensitive D Flip-Flop -- 6.6 Applications -- 6.6.1 Applications of the Latches -- 6.6.2 Applications of the Flip-Flop -- 6.7 Exercises -- 6.7.1 Exercise 1: Design Positive-Level-Sensitive Latch Using Multiplexers -- 6.7.2 Exercise 2: Design Negative-Level-Sensitive Latch Using Multiplexers -- 6.7.3 Exercise 3: What Is the Functionality of the Following Design? -- 6.7.4 Exercise 4: Design the Positive Edge-Sensitive Flip-Flop Using Latches -- 6.7.5 Exercise 5: Design the Negative Edge-Sensitive Flip-Flop Using Latches -- 6.7.6 Exercise 6: What Is the Operating Frequency of the Following Circuit? -- 6.7.7 Exercise 7: The Asynchronous Clear -- 6.7.8 Exercise 8: The Synchronous Clear -- 6.8 Important Takeaways -- 7 Sequential Design Techniques -- 7.1 Synchronous Design -- 7.2 Asynchronous Design -- 7.3 Why to Use Synchronous Design? -- 7.3.1 Which Elements We Should Use During Design? -- 7.4 D Flip-Flop and Use in the Design -- 7.5 Design for the given specifications -- 7.6 Design of the Synchronous Counters -- 7.7 Exercise 1: Design of the Synchronous Down-Counters -- 7.8 Exercise 2: Design of the Synchronous Gray Counter -- 7.9 Few Important Guidelines -- 7.10 Important Takeaways -- 8 Important Design Scenarios -- 8.1 MOD-3 Counter -- 8.2 The Design of MOD-3 Counter with 50% Duty Cycle -- 8.3 Applications and Use of Counters -- 8.3.1 Ring Counter -- 8.3.2 Johnson Counter -- 8.4 Exercises -- 8.4.1 Exercise 1: The Counter Output -- 8.4.2 Exercise 2: Find the Output Sequence.
8.4.3 Exercise 3: Operating Frequency of Design -- 8.4.4 Exercise 4: Output on 1024th Clock Cycle -- 8.4.5 Exercise 5: Output on the 4th Clock Cycle -- 8.4.6 Exercise 6: Output at 10th Clock Pulse -- 8.4.7 Exercise 7: Design the Serial Input Serial Output Shift Register -- 8.5 Important Takeaways -- 9 FSM Design Techniques -- 9.1 What Is FSM? -- 9.1.1 Moore FSM -- 9.1.2 Mealy FSM -- 9.1.3 Moore Versus Mealy FSM -- 9.2 State Encoding Methods -- 9.3 Moore FSM Design -- 9.4 Mealy FSM Design -- 9.5 Applications and Design Strategies -- 9.6 Exercises -- 9.6.1 Exercise 1: Moore Machine State Diagram -- 9.6.2 Exercise 2: Mealy Machine -- 9.6.3 Exercise 3: One-Hot Encoding -- 9.6.4 Exercise 4: FSM Area and Power Optimization -- 9.7 Important Takeaways -- 10 Advanced Design Techniques-1 -- 10.1 Various Paths in the Design -- 10.2 Data and Control Paths -- 10.3 Mealy Sequence Detector Design -- 10.4 Data and Control Path Design Techniques -- 10.5 Flip-Flop Timing Parameters -- 10.6 Example on Performance Improvement of the Design -- 10.7 Exercises -- 10.7.1 Exercise 1: Maximum Operating Frequency -- 10.7.2 Exercise 2: Timing Paths -- 10.7.3 Exercise 3: Maximum Operating Frequency -- 10.7.4 Exercise 4: Positive Clock Skew and Maximum Operating Frequency for the Design -- 10.7.5 Exercise 5: Negative Clock Skew and Maximum Operating Frequency for the Design -- 10.8 Important Takeaways -- 11 Advanced Design Techniques-2 -- 11.1 Multiple Clock Domain Designs -- 11.2 Metastability -- 11.3 Control Path Synchronizer -- 11.4 Data Path Synchronizer -- 11.5 Multiple Power Domain Designs -- 11.6 Architecture-Level Designs -- 11.7 How We Can Improve the Design Performance -- 11.8 The Digital Systems and Design -- 11.9 Exercises -- 11.9.1 Exercise 1: FIFO Depth Calculation -- 11.9.2 Exercise 2: FIFO Depth Calculation -- 11.9.3 Exercise 3: FIFO Depth Calculation.
11.9.4 Exercise 4: FIFO Depth Calculation -- 11.9.5 Exercise 5: FIFO Depth Calculation -- 11.10 Important Takeaways -- 12 System Design and Considerations -- 12.1 System Design -- 12.2 What We Need to Think About? -- 12.3 Important Considerations -- 12.4 Let Us Understand the Microprocessor Capabilities -- 12.5 Control Signal Generation Logic -- 12.6 IO Devices and Communication with the Processor -- 12.7 Memory Devices and Communication with the Processor -- 12.8 Design Scenarios and Optimization -- 12.9 Concluding Comments -- Index.
Record Nr. UNINA-9910512156003321
Taraate Vaibbhav  
Singapore : , : Springer Singapore Pte. Limited, , 2022
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Digital design techniques and exercises : a practice book for digital logic design / / Vaibbhav Taraate
Digital design techniques and exercises : a practice book for digital logic design / / Vaibbhav Taraate
Autore Taraate Vaibbhav
Pubbl/distr/stampa Gateway East, Singapore : , : Springer, , [2022]
Descrizione fisica 1 online resource (204 pages)
Disciplina 621.395
Soggetto topico Logic design - Data processing
Logic design
ISBN 981-16-5955-9
981-16-5954-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Acknowledgements -- Contents -- About the Author -- 1 Basics of Digital Design -- 1.1 Digital Logic and the Evolution -- 1.2 The Important Considerations -- 1.2.1 Area of the Design -- 1.2.2 Speed of the Design -- 1.2.3 Power -- 1.3 Logic Gates -- 1.4 De Morgan's Theorems -- 1.4.1 NAND is Equal to Bubbled OR -- 1.4.2 NOR is Equal to Bubbled AND -- 1.5 Multiplexer as Universal Logic -- 1.6 Optimization Goals and Applications in VLSI Context -- 1.7 Exercises -- 1.7.1 Exercise 1: Use of the Logical Expressions to Get the Logic Equivalent -- 1.7.2 Exercise 2: Cascade Logic and How to Get Logic Expression? -- 1.7.3 Exercise 3: Complement Logic -- 1.7.4 Exercise 4: Logic Expression for the Cascade Logic -- 1.7.5 Exercise 5: Output Expression for the Cascade Logic -- 1.7.6 Exercise 6: Propagation Delay for the Cascade Logic -- 1.7.7 Exercise 7: Logic Gate Output Expression -- 1.7.8 Exercise 8: Propagation Delay for the Cascade Logic -- 1.7.9 Exercise 9: The Equivalent Logic Expression -- 1.7.10 Exercise 10: The Equivalent Logic Gate -- 1.8 Important Takeaways -- 2 Design Using Universal Logic -- 2.1 What Is Universal Logic? -- 2.2 Universal Gates -- 2.2.1 NAND -- 2.2.2 NOR -- 2.2.3 Other Application-Specific Universal Gates -- 2.3 Multiplexers -- 2.3.1 Design Using 2:1 Mux -- 2.3.2 4:1 MUX Using 2:1 Mux -- 2.3.3 Design Using Multiplexers -- 2.4 Exercises -- 2.4.1 Exercise 1: Design Using Universal Gates -- 2.4.2 Exercise 2: Design Using the MUX -- 2.4.3 Exercise 3: Design Using MUX -- 2.4.4 Exercise 4: Design Using Custom Gates -- 2.4.5 Exercise 5: Optimization Exercise -- 2.4.6 Exercise 7: Design Using the MUX -- 2.4.7 Exercise 8: Design Using MUX -- 2.4.8 Exercise 9: Design Using Custom Gates -- 2.5 Applications and Use in VLSI Context -- 2.6 Important Takeaways -- 3 Combinational Design Resources -- 3.1 Code Converters.
3.1.1 Three-Bit Binary-to-Gray Code Converter -- 3.1.2 3-Bit Gray-to-Binary Code Converter -- 3.2 Arithmetic Resources -- 3.2.1 Half-Adder -- 3.2.2 Half-Subtractor -- 3.2.3 Full-Adder -- 3.3 Use of Arithmetic Resources in the Design -- 3.4 Design Using Arithmetic Resources and Control Elements -- 3.5 Optimization Goals -- 3.6 Processor Logic and Need of Arithmetic Resources -- 3.7 Exercises -- 3.7.1 Exercise 1: Cascade Versus Parallel Logic -- 3.7.2 Exercise 2: Delay of the Design -- 3.7.3 Exercise 3: Speed -- 3.7.4 Exercise 4: Design to perform the Addition and Subtraction -- 3.7.5 Exercise 4: Design with the Goal to Use Resource Sharing -- 3.8 Important Takeaways -- 4 Case Study: ALU Design -- 4.1 Design Specifications and Their Role -- 4.2 What Is ALU? -- 4.3 Arithmetic Unit Design -- 4.3.1 Resources Required -- 4.3.2 How to Start Design of ALU? -- 4.3.3 How to Design the Logic -- 4.3.4 Exercise 1: Optimization of the Arithmetic Unit -- 4.3.5 Logic Unit Design -- 4.3.6 Resources Required -- 4.3.7 How to Design the Logic Unit to have Better Area? -- 4.4 ALU Design -- 4.4.1 Resource Requirement and How to Design Efficient ALU? -- 4.4.2 ALU Design to have Better Area -- 4.4.3 Exercise 2: Optimization of ALU -- 4.5 Few Important Design Guidelines -- 4.6 Important Takeaways -- 5 Practical Scenarios and the Design Techniques -- 5.1 Parallel Logic -- 5.1.1 Decoder 2 to 4 -- 5.2 Encoder -- 5.3 Encoder with Invalid Output Detection Logic -- 5.4 Exercises -- 5.4.1 Exercise 1: Design of Decoder Having Active-Low Output -- 5.4.2 Exercise 2: Design the Function Using Decoder -- 5.4.3 Exercise 3: Design Using Decoders -- 5.4.4 Exercise 4: Design Using Decoder and NAND Gates -- 5.4.5 Exercise 5: Design Using Decoders -- 5.4.6 Exercise 6: Priority Encoder Design -- 5.5 Important Takeaways -- 6 Basics of the Sequential Design.
6.1 What Is Sequential Logic Design? -- 6.2 Sequential Design Elements -- 6.3 Level Versus Edge-Triggered Logic -- 6.4 Latches and Their Use in the Design -- 6.4.1 Positive-Level-Sensitive D Latch -- 6.4.2 Negative-Level-Sensitive D Latch -- 6.5 Edge-Sensitive Elements and Their Role -- 6.5.1 Positive Edge-Sensitive D Flip-Flop -- 6.5.2 Negative Edge-Sensitive D Flip-Flop -- 6.6 Applications -- 6.6.1 Applications of the Latches -- 6.6.2 Applications of the Flip-Flop -- 6.7 Exercises -- 6.7.1 Exercise 1: Design Positive-Level-Sensitive Latch Using Multiplexers -- 6.7.2 Exercise 2: Design Negative-Level-Sensitive Latch Using Multiplexers -- 6.7.3 Exercise 3: What Is the Functionality of the Following Design? -- 6.7.4 Exercise 4: Design the Positive Edge-Sensitive Flip-Flop Using Latches -- 6.7.5 Exercise 5: Design the Negative Edge-Sensitive Flip-Flop Using Latches -- 6.7.6 Exercise 6: What Is the Operating Frequency of the Following Circuit? -- 6.7.7 Exercise 7: The Asynchronous Clear -- 6.7.8 Exercise 8: The Synchronous Clear -- 6.8 Important Takeaways -- 7 Sequential Design Techniques -- 7.1 Synchronous Design -- 7.2 Asynchronous Design -- 7.3 Why to Use Synchronous Design? -- 7.3.1 Which Elements We Should Use During Design? -- 7.4 D Flip-Flop and Use in the Design -- 7.5 Design for the given specifications -- 7.6 Design of the Synchronous Counters -- 7.7 Exercise 1: Design of the Synchronous Down-Counters -- 7.8 Exercise 2: Design of the Synchronous Gray Counter -- 7.9 Few Important Guidelines -- 7.10 Important Takeaways -- 8 Important Design Scenarios -- 8.1 MOD-3 Counter -- 8.2 The Design of MOD-3 Counter with 50% Duty Cycle -- 8.3 Applications and Use of Counters -- 8.3.1 Ring Counter -- 8.3.2 Johnson Counter -- 8.4 Exercises -- 8.4.1 Exercise 1: The Counter Output -- 8.4.2 Exercise 2: Find the Output Sequence.
8.4.3 Exercise 3: Operating Frequency of Design -- 8.4.4 Exercise 4: Output on 1024th Clock Cycle -- 8.4.5 Exercise 5: Output on the 4th Clock Cycle -- 8.4.6 Exercise 6: Output at 10th Clock Pulse -- 8.4.7 Exercise 7: Design the Serial Input Serial Output Shift Register -- 8.5 Important Takeaways -- 9 FSM Design Techniques -- 9.1 What Is FSM? -- 9.1.1 Moore FSM -- 9.1.2 Mealy FSM -- 9.1.3 Moore Versus Mealy FSM -- 9.2 State Encoding Methods -- 9.3 Moore FSM Design -- 9.4 Mealy FSM Design -- 9.5 Applications and Design Strategies -- 9.6 Exercises -- 9.6.1 Exercise 1: Moore Machine State Diagram -- 9.6.2 Exercise 2: Mealy Machine -- 9.6.3 Exercise 3: One-Hot Encoding -- 9.6.4 Exercise 4: FSM Area and Power Optimization -- 9.7 Important Takeaways -- 10 Advanced Design Techniques-1 -- 10.1 Various Paths in the Design -- 10.2 Data and Control Paths -- 10.3 Mealy Sequence Detector Design -- 10.4 Data and Control Path Design Techniques -- 10.5 Flip-Flop Timing Parameters -- 10.6 Example on Performance Improvement of the Design -- 10.7 Exercises -- 10.7.1 Exercise 1: Maximum Operating Frequency -- 10.7.2 Exercise 2: Timing Paths -- 10.7.3 Exercise 3: Maximum Operating Frequency -- 10.7.4 Exercise 4: Positive Clock Skew and Maximum Operating Frequency for the Design -- 10.7.5 Exercise 5: Negative Clock Skew and Maximum Operating Frequency for the Design -- 10.8 Important Takeaways -- 11 Advanced Design Techniques-2 -- 11.1 Multiple Clock Domain Designs -- 11.2 Metastability -- 11.3 Control Path Synchronizer -- 11.4 Data Path Synchronizer -- 11.5 Multiple Power Domain Designs -- 11.6 Architecture-Level Designs -- 11.7 How We Can Improve the Design Performance -- 11.8 The Digital Systems and Design -- 11.9 Exercises -- 11.9.1 Exercise 1: FIFO Depth Calculation -- 11.9.2 Exercise 2: FIFO Depth Calculation -- 11.9.3 Exercise 3: FIFO Depth Calculation.
11.9.4 Exercise 4: FIFO Depth Calculation -- 11.9.5 Exercise 5: FIFO Depth Calculation -- 11.10 Important Takeaways -- 12 System Design and Considerations -- 12.1 System Design -- 12.2 What We Need to Think About? -- 12.3 Important Considerations -- 12.4 Let Us Understand the Microprocessor Capabilities -- 12.5 Control Signal Generation Logic -- 12.6 IO Devices and Communication with the Processor -- 12.7 Memory Devices and Communication with the Processor -- 12.8 Design Scenarios and Optimization -- 12.9 Concluding Comments -- Index.
Record Nr. UNINA-9910743257703321
Taraate Vaibbhav  
Gateway East, Singapore : , : Springer, , [2022]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Digital logic design using Verilog : coding and RTL synthesis / / Vaibbhav Taraate
Digital logic design using Verilog : coding and RTL synthesis / / Vaibbhav Taraate
Autore Taraate Vaibbhav
Edizione [2nd ed.]
Pubbl/distr/stampa Singapore : , : Springer, , [2022]
Descrizione fisica 1 online resource (607 pages)
Disciplina 371.320973
Soggetto topico Logic design - Data processing
Verilog (Computer hardware description language)
ISBN 981-16-3199-9
981-16-3198-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Acknowledgements -- Contents -- About the Author -- 1 Introduction -- 1.1 Evolution of Logic Design -- 1.2 System and Logic Design Abstractions -- 1.2.1 Architecture Design -- 1.2.2 Micro-architecture Design -- 1.2.3 RTL Design and Synthesis -- 1.2.4 Switch Level Design -- 1.3 Integrated Circuit Design and Methodologies -- 1.3.1 RTL Design -- 1.3.2 Functional Verification -- 1.3.3 Synthesis -- 1.3.4 Physical Design -- 1.4 Verilog as Hardware Description Language -- 1.5 Verilog Design Description -- 1.5.1 Structural Design -- 1.5.2 Behavior Design -- 1.5.3 Synthesizable Design -- 1.6 Few Important Verilog Terminologies -- 1.7 Exercises -- 1.8 Summary -- 2 Concept of Concurrency and Verilog Operators -- 2.1 Use of Continuous Assignment to Model Design -- 2.2 Use of always Procedural Block to Implement Combinational Design -- 2.3 Concept of Concurrency -- 2.4 Verilog Arithmetic Operators -- 2.5 Verilog Logical Operators -- 2.6 Verilog Equality and Inequality Operators -- 2.7 Verilog Sign Operators -- 2.8 Verilog Bitwise Operators -- 2.9 Verilog Relational Operators -- 2.10 Verilog Concatenation and Replication Operators -- 2.11 Verilog Reduction Operators -- 2.12 Verilog Shift Operators -- 2.13 Exercises -- 2.14 Summary -- 3 Verilog Constructs and Combinational Design-I -- 3.1 The Role of Constructs -- 3.2 Logic Gates and Synthesizable RTL -- 3.2.1 NOT or Invert Logic -- 3.2.2 OR Logic -- 3.2.3 NOR Logic -- 3.2.4 AND Logic -- 3.2.5 NAND Logic -- 3.2.6 Two Input XOR Logic -- 3.2.7 Two Input XNOR Logic -- 3.3 Tristate Logic -- 3.4 Arithmetic Circuits -- 3.4.1 Adder -- 3.4.1.1 Half Adder -- 3.4.1.2 Full Adder -- 3.4.2 Subtractor -- 3.4.2.1 Half Subtractor -- 3.4.2.2 Full Subtractor -- 3.5 Exercises -- 3.6 Summary -- 4 Verilog Constructs and Combinational Design-II -- 4.1 Procedural Block always @*.
4.2 Multi-bit Adders and Subtractors -- 4.2.1 Four-Bit Full Adder -- 4.2.2 4-Bit Full Subtractor -- 4.2.3 4-Bit Adder and Subtractor -- 4.3 Optimization of Resources -- 4.3.1 Optimization Using Only Adders -- 4.3.2 Optimization by Tweaking the Logic to Have Better Data and Control Path -- 4.4 Procedural Block initial -- 4.5 Simulation Concepts: Basic Testbench -- 4.6 Comparators and Parity Detectors -- 4.6.1 Binary Comparators -- 4.6.2 Parity Detector -- 4.7 Code Converters -- 4.7.1 Binary to Gray Code Converter -- 4.7.2 Gray to Binary Code Converter -- 4.8 Let Us Think About the Design from Specifications -- 4.9 Exercises -- 4.10 Summary -- 5 Multiplexers as Universal Logic -- 5.1 Multiplexers -- 5.2 Multiplexer as Universal logic -- 5.2.1 2:1 MUX -- 5.3 The if...else Versus case Construct -- 5.4 The 4:1 MUX Using if...else -- 5.5 The 4:1 MUX Using case Construct -- 5.6 The 4:1 Mux Using 2:1 MUX -- 5.7 Let Us Design Combinational Logic Using Multiplexers -- 5.8 Optimization Strategies Using RTL Tweaks -- 5.9 Exercises -- 5.10 Summary -- 6 Decoders and Encoders -- 6.1 Decoders -- 6.1.1 1 Line to 2 Decoder Using case construct -- 6.1.2 1 Line to 2 Decoder Having Enable Using case -- 6.1.3 2 Line to 4 Decoder with Enable Using case -- 6.1.4 2 Line to 4 Decoder with Active Low Enable Using case -- 6.1.5 2 to 4 Decoder Using Continuous Assignments -- 6.1.6 Decoder Using Shift Operator -- 6.1.7 Testbench of 2:4 Decoder -- 6.1.8 4 Line to 16 Decoder Using 2:4 Decoder -- 6.2 Testbench for 4:16 Decoder -- 6.3 Encoders -- 6.3.1 Priority Encoders -- 6.4 Testbench of 4:2 Priority encoder -- 6.5 Exercises -- 6.6 Summary -- 7 Event Queue and Design Guidelines -- 7.1 Verilog Stratified Event Queue -- 7.2 Verilog Blocking Assignments -- 7.3 Incomplete Sensitivity List -- 7.4 Continuous Versus Procedural Assignments -- 7.5 Combinational Loops in Design.
7.6 Unintentional Latches in the Design -- 7.7 Use of Blocking Assignments -- 7.8 Use of if...else Versus case constructs -- 7.9 Nested Multiplexer or Priority Logic -- 7.10 Parallel Logic or Decoding Logic -- 7.11 Priority Encoding Structure -- 7.12 Missing default Condition in case construct -- 7.13 Nested if...else with Missing else Condition -- 7.14 Logical Equality Versus Case Equality -- 7.14.1 Logical Equality and Logical Inequality Operators -- 7.14.2 Case Equality and Case Inequality Operators -- 7.15 Multiple Driver Assignments -- 7.16 Exercises -- 7.17 Summary -- 8 Basics of Sequential Design Using Verilog -- 8.1 Sequential Logic -- 8.1.1 Positive-Level Sensitive D Latch -- 8.1.2 Negative-Level Sensitive D Latch -- 8.2 Flip-Flop -- 8.2.1 Positive Edge-Triggered D Flip-Flop -- 8.2.2 Negative Edge-Triggered D Flip-Flop -- 8.2.3 Synchronous and Asynchronous Reset -- 8.2.3.1 D Flip-Flop Having Asynchronous Reset -- 8.2.4 D Flip-Flop Having Synchronous Reset -- 8.2.5 Flip-Flop Having Synchronous Load Enable and Asynchronous Reset -- 8.2.6 Flip-Flop with Synchronous Load and Synchronous Reset -- 8.3 Exercises -- 8.4 Summary -- 9 Synchronous Counter Design Using Synthesizable Constructs -- 9.1 Synchronous Counters -- 9.1.1 Three-Bit Up Counter -- 9.1.2 Three-Bit Down Counter -- 9.1.3 Three-Bit Up-Down Counter -- 9.2 Gray Counters -- 9.2.1 Gray and Binary Counter -- 9.2.2 Ring Counters -- 9.2.3 Johnson Counters -- 9.3 BCD Up-Down Counter -- 9.4 Exercises -- 9.5 Summary -- 10 RTL Design of Registers and Memories -- 10.1 Parallel Input and Parallel Output (PIPO) Register -- 10.2 Shift Register -- 10.3 Right and Left Shift Operation -- 10.4 Timing and Performance Evaluation -- 10.5 Asynchronous Counter Design -- 10.5.1 Ripple Counters -- 10.6 RTL Design of Memories -- 10.7 Parameterized Read-Write Memory -- 10.8 Exercises -- 10.9 Summary.
11 Sequential Circuit Design Guidelines -- 11.1 What Happens If Blocking Assignments Are Used to Code Sequential Logic? -- 11.1.1 Blocking Assignments and Multiple always Blocks -- 11.1.2 Multiple Blocking Assignments Used in the Single always Block -- 11.1.3 Example Blocking Assignment -- 11.2 Non-blocking Assignments -- 11.2.1 Example Non-blocking Assignments -- 11.2.2 Example Non-blocking Assignment -- 11.2.3 Example Using Non-blocking Assignments -- 11.3 Latch Versus Flip-Flop -- 11.3.1 D Flip-Flop -- 11.3.2 Latch -- 11.4 Use of Synchronous Versus Asynchronous Reset -- 11.4.1 D Flip-Flop Having Asynchronous Reset -- 11.4.2 Synchronous Reset D Flip-Flop -- 11.5 Use of if...else Versus case constructs -- 11.6 Internally Generated Clocks -- 11.7 Guidelines for Modeling Synchronous Designs -- 11.8 Multiple Clocks in the Same module -- 11.9 Multi-phase Clocks in the Design -- 11.10 Guidelines for Modeling Asynchronous Designs -- 11.11 Exercises -- 11.12 Summary -- 12 RTL Design Strategies for Complex Designs -- 12.1 ALU Design -- 12.1.1 Logic Unit Design -- 12.1.1.1 Logic Unit to Infer Parallel Logic -- 12.1.1.2 Logic Unit Having Registered Inputs and Outputs -- 12.1.2 Arithmetic Unit -- 12.1.3 Arithmetic and Logic Unit -- 12.2 Functions and Tasks -- 12.2.1 Counting Number of 1's from the Given String -- 12.2.2 RTL Design Using function to Count Number of 1'S -- 12.3 Synthesis Result of RTL Using function -- 12.4 Synthesis Result of RTL Using task -- 12.5 Exercises -- 12.6 Summary -- 13 RTL Tweaks and Performance Improvement Techniques -- 13.1 Arithmetic Resource Sharing -- 13.1.1 RTL Design Using Resource Sharing to Have Area Optimization -- 13.2 Gated Clocks and Dynamic Power Reduction -- 13.3 Use of Pipelining in Design -- 13.3.1 Design Without Pipelining -- 13.3.2 Speed Improvement Using Register Balancing or Pipelining.
13.4 Counter Design and Duty Cycle Control -- 13.5 MOD-3 Counter RTL Design to Have 50% Duty Cycle -- 13.6 Exercise -- 13.7 Summary -- 14 Finite State Machines Using Verilog -- 14.1 Moore Versus Mealy Machines -- 14.1.1 Level to Pulse Converter -- 14.2 FSM Encoding Styles -- 14.2.1 Binary Encoding -- 14.2.1.1 Two-Bit Binary Counter FSM -- 14.2.2 Gray Encoding -- 14.2.2.1 Two-Bit Gray Counter FSM -- 14.3 One-Hot Encoding -- 14.4 Sequence Detectors Using FSMs -- 14.4.1 Mealy Sequence Detector Using Two always Procedural Blocks -- 14.4.2 Mealy Machine: Sequence Detector to Detect 101 Overlapping Sequence -- 14.5 Improving the Design Performance for FSMs -- 14.6 Exercises -- 14.7 Summary -- 15 Non-synthesizable Verilog Constructs and Testbenches -- 15.1 Intra-delay and Inter-delay Assignments -- 15.1.1 Simulation for Blocking Assignments -- 15.1.2 Simulation of Non-blocking Assignments -- 15.2 The always and initial Procedural Block -- 15.2.1 Blocking Assignments with Inter-assignment Delays -- 15.2.2 Blocking Assignments with Intra-assignment Delays -- 15.2.3 Non-blocking Assignments with Inter-assignment Delays -- 15.2.4 Non-blocking Assignments with Intra-assignment Delays -- 15.3 Role of Testbenches -- 15.4 Multiple Assignments Within the begin-end -- 15.5 Multiple Assignments Within the fork-join -- 15.6 Display Tasks -- 15.7 Exercises -- 15.8 Summary -- 16 FPGA Architecture and Design Flow -- 16.1 Introduction to PLD -- 16.2 FPGA as Programmable ASIC -- 16.2.1 SRAM Based FPGA -- 16.2.2 Flash Based FPGA -- 16.2.3 Antifuse FPGAS -- 16.2.4 Important FPGA Blocks -- 16.3 FPGA Design Flow -- 16.3.1 Design Entry -- 16.3.2 Design Simulation and Synthesis -- 16.3.3 Design Implementation -- 16.3.4 Device Programming -- 16.4 Logic Realization Using FPGA -- 16.4.1 Configurable Logic Block -- 16.4.2 Input Output Block (IOB) -- 16.4.3 Block RAM.
16.4.4 Digital Clock Manager (DCM) Block.
Record Nr. UNINA-9910743250303321
Taraate Vaibbhav  
Singapore : , : Springer, , [2022]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Digital Logic Design Using Verilog : Coding and RTL Synthesis
Digital Logic Design Using Verilog : Coding and RTL Synthesis
Autore Taraate Vaibbhav
Edizione [2nd ed.]
Pubbl/distr/stampa Singapore : , : Springer Singapore Pte. Limited, , 2021
Descrizione fisica 1 online resource (607 pages)
Disciplina 621.395
Soggetto genere / forma Electronic books.
ISBN 981-16-3199-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Acknowledgements -- Contents -- About the Author -- 1 Introduction -- 1.1 Evolution of Logic Design -- 1.2 System and Logic Design Abstractions -- 1.2.1 Architecture Design -- 1.2.2 Micro-architecture Design -- 1.2.3 RTL Design and Synthesis -- 1.2.4 Switch Level Design -- 1.3 Integrated Circuit Design and Methodologies -- 1.3.1 RTL Design -- 1.3.2 Functional Verification -- 1.3.3 Synthesis -- 1.3.4 Physical Design -- 1.4 Verilog as Hardware Description Language -- 1.5 Verilog Design Description -- 1.5.1 Structural Design -- 1.5.2 Behavior Design -- 1.5.3 Synthesizable Design -- 1.6 Few Important Verilog Terminologies -- 1.7 Exercises -- 1.8 Summary -- 2 Concept of Concurrency and Verilog Operators -- 2.1 Use of Continuous Assignment to Model Design -- 2.2 Use of always Procedural Block to Implement Combinational Design -- 2.3 Concept of Concurrency -- 2.4 Verilog Arithmetic Operators -- 2.5 Verilog Logical Operators -- 2.6 Verilog Equality and Inequality Operators -- 2.7 Verilog Sign Operators -- 2.8 Verilog Bitwise Operators -- 2.9 Verilog Relational Operators -- 2.10 Verilog Concatenation and Replication Operators -- 2.11 Verilog Reduction Operators -- 2.12 Verilog Shift Operators -- 2.13 Exercises -- 2.14 Summary -- 3 Verilog Constructs and Combinational Design-I -- 3.1 The Role of Constructs -- 3.2 Logic Gates and Synthesizable RTL -- 3.2.1 NOT or Invert Logic -- 3.2.2 OR Logic -- 3.2.3 NOR Logic -- 3.2.4 AND Logic -- 3.2.5 NAND Logic -- 3.2.6 Two Input XOR Logic -- 3.2.7 Two Input XNOR Logic -- 3.3 Tristate Logic -- 3.4 Arithmetic Circuits -- 3.4.1 Adder -- 3.4.1.1 Half Adder -- 3.4.1.2 Full Adder -- 3.4.2 Subtractor -- 3.4.2.1 Half Subtractor -- 3.4.2.2 Full Subtractor -- 3.5 Exercises -- 3.6 Summary -- 4 Verilog Constructs and Combinational Design-II -- 4.1 Procedural Block always @*.
4.2 Multi-bit Adders and Subtractors -- 4.2.1 Four-Bit Full Adder -- 4.2.2 4-Bit Full Subtractor -- 4.2.3 4-Bit Adder and Subtractor -- 4.3 Optimization of Resources -- 4.3.1 Optimization Using Only Adders -- 4.3.2 Optimization by Tweaking the Logic to Have Better Data and Control Path -- 4.4 Procedural Block initial -- 4.5 Simulation Concepts: Basic Testbench -- 4.6 Comparators and Parity Detectors -- 4.6.1 Binary Comparators -- 4.6.2 Parity Detector -- 4.7 Code Converters -- 4.7.1 Binary to Gray Code Converter -- 4.7.2 Gray to Binary Code Converter -- 4.8 Let Us Think About the Design from Specifications -- 4.9 Exercises -- 4.10 Summary -- 5 Multiplexers as Universal Logic -- 5.1 Multiplexers -- 5.2 Multiplexer as Universal logic -- 5.2.1 2:1 MUX -- 5.3 The if...else Versus case Construct -- 5.4 The 4:1 MUX Using if...else -- 5.5 The 4:1 MUX Using case Construct -- 5.6 The 4:1 Mux Using 2:1 MUX -- 5.7 Let Us Design Combinational Logic Using Multiplexers -- 5.8 Optimization Strategies Using RTL Tweaks -- 5.9 Exercises -- 5.10 Summary -- 6 Decoders and Encoders -- 6.1 Decoders -- 6.1.1 1 Line to 2 Decoder Using case construct -- 6.1.2 1 Line to 2 Decoder Having Enable Using case -- 6.1.3 2 Line to 4 Decoder with Enable Using case -- 6.1.4 2 Line to 4 Decoder with Active Low Enable Using case -- 6.1.5 2 to 4 Decoder Using Continuous Assignments -- 6.1.6 Decoder Using Shift Operator -- 6.1.7 Testbench of 2:4 Decoder -- 6.1.8 4 Line to 16 Decoder Using 2:4 Decoder -- 6.2 Testbench for 4:16 Decoder -- 6.3 Encoders -- 6.3.1 Priority Encoders -- 6.4 Testbench of 4:2 Priority encoder -- 6.5 Exercises -- 6.6 Summary -- 7 Event Queue and Design Guidelines -- 7.1 Verilog Stratified Event Queue -- 7.2 Verilog Blocking Assignments -- 7.3 Incomplete Sensitivity List -- 7.4 Continuous Versus Procedural Assignments -- 7.5 Combinational Loops in Design.
7.6 Unintentional Latches in the Design -- 7.7 Use of Blocking Assignments -- 7.8 Use of if...else Versus case constructs -- 7.9 Nested Multiplexer or Priority Logic -- 7.10 Parallel Logic or Decoding Logic -- 7.11 Priority Encoding Structure -- 7.12 Missing default Condition in case construct -- 7.13 Nested if...else with Missing else Condition -- 7.14 Logical Equality Versus Case Equality -- 7.14.1 Logical Equality and Logical Inequality Operators -- 7.14.2 Case Equality and Case Inequality Operators -- 7.15 Multiple Driver Assignments -- 7.16 Exercises -- 7.17 Summary -- 8 Basics of Sequential Design Using Verilog -- 8.1 Sequential Logic -- 8.1.1 Positive-Level Sensitive D Latch -- 8.1.2 Negative-Level Sensitive D Latch -- 8.2 Flip-Flop -- 8.2.1 Positive Edge-Triggered D Flip-Flop -- 8.2.2 Negative Edge-Triggered D Flip-Flop -- 8.2.3 Synchronous and Asynchronous Reset -- 8.2.3.1 D Flip-Flop Having Asynchronous Reset -- 8.2.4 D Flip-Flop Having Synchronous Reset -- 8.2.5 Flip-Flop Having Synchronous Load Enable and Asynchronous Reset -- 8.2.6 Flip-Flop with Synchronous Load and Synchronous Reset -- 8.3 Exercises -- 8.4 Summary -- 9 Synchronous Counter Design Using Synthesizable Constructs -- 9.1 Synchronous Counters -- 9.1.1 Three-Bit Up Counter -- 9.1.2 Three-Bit Down Counter -- 9.1.3 Three-Bit Up-Down Counter -- 9.2 Gray Counters -- 9.2.1 Gray and Binary Counter -- 9.2.2 Ring Counters -- 9.2.3 Johnson Counters -- 9.3 BCD Up-Down Counter -- 9.4 Exercises -- 9.5 Summary -- 10 RTL Design of Registers and Memories -- 10.1 Parallel Input and Parallel Output (PIPO) Register -- 10.2 Shift Register -- 10.3 Right and Left Shift Operation -- 10.4 Timing and Performance Evaluation -- 10.5 Asynchronous Counter Design -- 10.5.1 Ripple Counters -- 10.6 RTL Design of Memories -- 10.7 Parameterized Read-Write Memory -- 10.8 Exercises -- 10.9 Summary.
11 Sequential Circuit Design Guidelines -- 11.1 What Happens If Blocking Assignments Are Used to Code Sequential Logic? -- 11.1.1 Blocking Assignments and Multiple always Blocks -- 11.1.2 Multiple Blocking Assignments Used in the Single always Block -- 11.1.3 Example Blocking Assignment -- 11.2 Non-blocking Assignments -- 11.2.1 Example Non-blocking Assignments -- 11.2.2 Example Non-blocking Assignment -- 11.2.3 Example Using Non-blocking Assignments -- 11.3 Latch Versus Flip-Flop -- 11.3.1 D Flip-Flop -- 11.3.2 Latch -- 11.4 Use of Synchronous Versus Asynchronous Reset -- 11.4.1 D Flip-Flop Having Asynchronous Reset -- 11.4.2 Synchronous Reset D Flip-Flop -- 11.5 Use of if...else Versus case constructs -- 11.6 Internally Generated Clocks -- 11.7 Guidelines for Modeling Synchronous Designs -- 11.8 Multiple Clocks in the Same module -- 11.9 Multi-phase Clocks in the Design -- 11.10 Guidelines for Modeling Asynchronous Designs -- 11.11 Exercises -- 11.12 Summary -- 12 RTL Design Strategies for Complex Designs -- 12.1 ALU Design -- 12.1.1 Logic Unit Design -- 12.1.1.1 Logic Unit to Infer Parallel Logic -- 12.1.1.2 Logic Unit Having Registered Inputs and Outputs -- 12.1.2 Arithmetic Unit -- 12.1.3 Arithmetic and Logic Unit -- 12.2 Functions and Tasks -- 12.2.1 Counting Number of 1's from the Given String -- 12.2.2 RTL Design Using function to Count Number of 1'S -- 12.3 Synthesis Result of RTL Using function -- 12.4 Synthesis Result of RTL Using task -- 12.5 Exercises -- 12.6 Summary -- 13 RTL Tweaks and Performance Improvement Techniques -- 13.1 Arithmetic Resource Sharing -- 13.1.1 RTL Design Using Resource Sharing to Have Area Optimization -- 13.2 Gated Clocks and Dynamic Power Reduction -- 13.3 Use of Pipelining in Design -- 13.3.1 Design Without Pipelining -- 13.3.2 Speed Improvement Using Register Balancing or Pipelining.
13.4 Counter Design and Duty Cycle Control -- 13.5 MOD-3 Counter RTL Design to Have 50% Duty Cycle -- 13.6 Exercise -- 13.7 Summary -- 14 Finite State Machines Using Verilog -- 14.1 Moore Versus Mealy Machines -- 14.1.1 Level to Pulse Converter -- 14.2 FSM Encoding Styles -- 14.2.1 Binary Encoding -- 14.2.1.1 Two-Bit Binary Counter FSM -- 14.2.2 Gray Encoding -- 14.2.2.1 Two-Bit Gray Counter FSM -- 14.3 One-Hot Encoding -- 14.4 Sequence Detectors Using FSMs -- 14.4.1 Mealy Sequence Detector Using Two always Procedural Blocks -- 14.4.2 Mealy Machine: Sequence Detector to Detect 101 Overlapping Sequence -- 14.5 Improving the Design Performance for FSMs -- 14.6 Exercises -- 14.7 Summary -- 15 Non-synthesizable Verilog Constructs and Testbenches -- 15.1 Intra-delay and Inter-delay Assignments -- 15.1.1 Simulation for Blocking Assignments -- 15.1.2 Simulation of Non-blocking Assignments -- 15.2 The always and initial Procedural Block -- 15.2.1 Blocking Assignments with Inter-assignment Delays -- 15.2.2 Blocking Assignments with Intra-assignment Delays -- 15.2.3 Non-blocking Assignments with Inter-assignment Delays -- 15.2.4 Non-blocking Assignments with Intra-assignment Delays -- 15.3 Role of Testbenches -- 15.4 Multiple Assignments Within the begin-end -- 15.5 Multiple Assignments Within the fork-join -- 15.6 Display Tasks -- 15.7 Exercises -- 15.8 Summary -- 16 FPGA Architecture and Design Flow -- 16.1 Introduction to PLD -- 16.2 FPGA as Programmable ASIC -- 16.2.1 SRAM Based FPGA -- 16.2.2 Flash Based FPGA -- 16.2.3 Antifuse FPGAS -- 16.2.4 Important FPGA Blocks -- 16.3 FPGA Design Flow -- 16.3.1 Design Entry -- 16.3.2 Design Simulation and Synthesis -- 16.3.3 Design Implementation -- 16.3.4 Device Programming -- 16.4 Logic Realization Using FPGA -- 16.4.1 Configurable Logic Block -- 16.4.2 Input Output Block (IOB) -- 16.4.3 Block RAM.
16.4.4 Digital Clock Manager (DCM) Block.
Record Nr. UNINA-9910508440903321
Taraate Vaibbhav  
Singapore : , : Springer Singapore Pte. Limited, , 2021
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Digital Logic Design Using Verilog [[electronic resource] ] : Coding and RTL Synthesis / / by Vaibbhav Taraate
Digital Logic Design Using Verilog [[electronic resource] ] : Coding and RTL Synthesis / / by Vaibbhav Taraate
Autore Taraate Vaibbhav
Edizione [1st ed. 2016.]
Pubbl/distr/stampa New Delhi : , : Springer India : , : Imprint : Springer, , 2016
Descrizione fisica 1 online resource (431 p.)
Disciplina 620
Soggetto topico Electronic circuits
Electronics
Microelectronics
Logic design
Circuits and Systems
Electronics and Microelectronics, Instrumentation
Logic Design
ISBN 81-322-2791-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.
Record Nr. UNINA-9910254218503321
Taraate Vaibbhav  
New Delhi : , : Springer India : , : Imprint : Springer, , 2016
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Logic Synthesis and SOC Prototyping : RTL Design using VHDL / / by Vaibbhav Taraate
Logic Synthesis and SOC Prototyping : RTL Design using VHDL / / by Vaibbhav Taraate
Autore Taraate Vaibbhav
Edizione [1st ed. 2020.]
Pubbl/distr/stampa Singapore : , : Springer Singapore : , : Imprint : Springer, , 2020
Descrizione fisica 1 online resource (XIX, 251 p.)
Disciplina 621.3815
Soggetto topico Electronic circuits
Microprogramming 
Logic design
Circuits and Systems
Control Structures and Microprogramming
Logic Design
ISBN 981-15-1314-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- ASIC Design and SOC prototype -- Design using VHDL & Guidelines -- Design using VHDL & Guidelines -- Design and Verification Strategies -- VHDL Design and RTL Tweaks -- ASIC Synthesis and Design Constraints -- Design optimization -- Design optimization -- FPGA for SOC Prototype -- Prototype using Single and Multiple FPGA. .
Record Nr. UNINA-9910373898603321
Taraate Vaibbhav  
Singapore : , : Springer Singapore : , : Imprint : Springer, , 2020
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
PLD Based Design with VHDL : RTL Design, Synthesis and Implementation / / by Vaibbhav Taraate
PLD Based Design with VHDL : RTL Design, Synthesis and Implementation / / by Vaibbhav Taraate
Autore Taraate Vaibbhav
Edizione [1st ed. 2017.]
Pubbl/distr/stampa Singapore : , : Springer Singapore : , : Imprint : Springer, , 2017
Descrizione fisica 1 online resource (XXI, 423 p. 246 illus.)
Disciplina 621.3815
Soggetto topico Electronic circuits
Electronics
Microelectronics
Microprogramming 
Circuits and Systems
Electronics and Microelectronics, Instrumentation
Control Structures and Microprogramming
ISBN 981-10-3296-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction to HDL -- Basic Logic Circuits and VHDL Description -- VHDL and Key Important Constructs -- 4 Combinational Logic Design Using VHDL Constructs -- Sequential Logic Design -- Introduction to PLD -- Design and simulation using VHDL constructs -- PLD Based Design Guidelines -- Finite State Machines -- Synthesis Optimization using VHDL -- Design Implementation Using Xilinx Vivado.
Record Nr. UNINA-9910254168703321
Taraate Vaibbhav  
Singapore : , : Springer Singapore : , : Imprint : Springer, , 2017
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui