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Computer networks / / Andrew S. Tanenbaum, David J. Wetherall
| Computer networks / / Andrew S. Tanenbaum, David J. Wetherall |
| Autore | Tanenbaum Andrew S. <1944-> |
| Edizione | [5th ed.] |
| Pubbl/distr/stampa | Harlow, : Pearson, 2014 |
| Descrizione fisica | 1 online resource (ii, 803 p.) : ill |
| Disciplina | 004.6 |
| Altri autori (Persone) | WetherallDavid J |
| Collana | Pearson Custom Library |
| Soggetto topico | Computer networks |
| Soggetto genere / forma | Libros electrónicos. |
| ISBN |
9781299961784
1299961789 9781292037189 1292037180 9780133485936 0133485935 9780133048377 0133048373 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | 1. Introduction -- 2. The physical layer -- 3. The data link layer -- 4. The medium access control sublayer -- 5. The Network layer -- 6. The transport layer -- 7. The application layer -- 8. Reading list and bibliography. |
| Record Nr. | UNINA-9910153105403321 |
Tanenbaum Andrew S. <1944->
|
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| Harlow, : Pearson, 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Modern operating systems / / Andrew S. Tanenbaum and Herbert Bos
| Modern operating systems / / Andrew S. Tanenbaum and Herbert Bos |
| Autore | Tanenbaum Andrew S. <1944-> |
| Edizione | [Global edition, Fourth edition.] |
| Pubbl/distr/stampa | Harlow, England : , : Pearson, , [2014] |
| Descrizione fisica | 1 online resource (1,106 pages) |
| Disciplina | 005.4469 |
| Collana | Always Learning |
| Soggetto topico |
Sistemes operatius (Ordinadors)
Operating systems (Computers) |
| Soggetto genere / forma | Llibres electrònics |
| ISBN |
9781292061955
1-292-06195-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Title -- Content -- PREFACE -- 1 INTRODUCTION -- 1.1 WHAT IS AN OPERATING SYSTEM? -- 1.1.1 The Operating System as an Extended Machine -- 1.1.2 The Operating System as a Resource Manager -- 1.2 HISTORY OF OPERATING SYSTEMS -- 1.2.1 The First Generation (1945-55): Vacuum Tubes -- 1.2.2 The Second Generation (1955-65): Transistors and Batch Systems -- 1.2.3 The Third Generation (1965-1980): ICs and Multiprogramming -- 1.2.4 The Fourth Generation (1980-Present): Personal Computers -- 1.2.5 The Fifth Generation (1990-Present): Mobile Computers -- 1.3 COMPUTER HARDWARE REVIEW -- 1.3.1 Processors -- 1.3.2 Memory -- 1.3.3 Disks -- 1.3.4 I/O Devices -- 1.3.5 Buses -- 1.3.6 Booting the Computer -- 1.4 THE OPERATING SYSTEM ZOO -- 1.4.1 Mainframe Operating Systems -- 1.4.2 Server Operating Systems -- 1.4.3 Multiprocessor Operating Systems -- 1.4.4 Personal Computer Operating Systems -- 1.4.5 Handheld Computer Operating Systems -- 1.4.6 Embedded Operating Systems -- 1.4.7 Sensor-Node Operating Systems -- 1.4.8 Real-Time Operating Systems -- 1.4.9 Smart Card Operating Systems -- 1.5 OPERATING SYSTEM CONCEPTS -- 1.5.1 Processes -- 1.5.2 Address Spaces -- 1.5.3 Files -- 1.5.4 Input/Output -- 1.5.5 Protection -- 1.5.6 The Shell -- 1.5.7 Ontogeny Recapitulates Phylogeny -- 1.6 SYSTEM CALLS -- 1.6.1 System Calls for Process Management -- 1.6.2 System Calls for File Management -- 1.6.3 System Calls for Directory Management -- 1.6.4 Miscellaneous System Calls -- 1.6.5 The Windows Win32 API -- 1.7 OPERATING SYSTEM STRUCTURE -- 1.7.1 Monolithic Systems -- 1.7.2 Layered Systems -- 1.7.3 Microkernels -- 1.7.4 Client-Server Model -- 1.7.5 Virtual Machines -- 1.8 THE WORLD ACCORDING TO C -- 1.8.1 The C Language -- 1.8.2 Header Files -- 1.8.3 Large Programming Projects -- 1.8.4 The Model of Run Time -- 1.9 RESEARCH ON OPERATING SYSTEMS.
1.10 OUTLINE OF THE REST OF THIS BOOK -- 1.11 METRIC UNITS -- 1.12 SUMMARY -- 2 PROCESSES AND THREADS -- 2.1 PROCESSES -- 2.1.1 The Process Model -- 2.1.2 Process Creation -- 2.1.3 Process Termination -- 2.1.4 Process Hierarchies -- 2.1.5 Process States -- 2.1.6 Implementation of Processes -- 2.1.7 Modeling Multiprogramming -- 2.2 THREADS -- 2.2.1 Thread Usage -- 2.2.2 The Classical Thread Model -- 2.2.3 POSIX Threads -- 2.2.4 Implementing Threads in User Space -- 2.2.5 Implementing Threads in the Kernel -- 2.2.6 Hybrid Implementations -- 2.2.7 Scheduler Activations -- 2.2.8 Pop-Up Threads -- 2.2.9 Making Single-Threaded Code Multithreaded -- 2.3 INTERPROCESS COMMUNICATION -- 2.3.1 Race Conditions -- 2.3.2 Critical Regions -- 2.3.3 Mutual Exclusion with Busy Waiting -- 2.3.4 Sleep and Wakeup -- 2.3.5 Semaphores -- 2.3.6 Mutexes -- 2.3.7 Monitors -- 2.3.8 Message Passing -- 2.3.9 Barriers -- 2.3.10 Avoiding Locks: Read-Copy-Update -- 2.4 SCHEDULING -- 2.4.1 Introduction to Scheduling -- 2.4.2 Scheduling in Batch Systems -- 2.4.3 Scheduling in Interactive Systems -- 2.4.4 Scheduling in Real-Time Systems -- 2.4.5 Policy Versus Mechanism -- 2.4.6 Thread Scheduling -- 2.5 CLASSICAL IPC PROBLEMS -- 2.5.1 The Dining Philosophers Problem -- 2.5.2 The Readers and Writers Problem -- 2.6 RESEARCH ON PROCESSES AND THREADS -- 2.7 SUMMARY -- 3 MEMORY MANAGEMENT -- 3.1 NO MEMORY ABSTRACTION -- 3.2 A MEMORY ABSTRACTION: ADDRESS SPACES -- 3.2.1 The Notion of an Address Space -- 3.2.2 Swapping -- 3.2.3 Managing Free Memory -- 3.3 VIRTUAL MEMORY -- 3.3.1 Paging -- 3.3.2 Page Tables -- 3.3.3 Speeding Up Paging -- 3.3.4 Page Tables for Large Memories -- 3.4 PAGE REPLACEMENT ALGORITHMS -- 3.4.1 The Optimal Page Replacement Algorithm -- 3.4.2 The Not Recently Used Page Replacement Algorithm -- 3.4.3 The First-In, First-Out (FIFO) Page Replacement Algorithm. 3.4.4 The Second-Chance Page Replacement Algorithm -- 3.4.5 The Clock Page Replacement Algorithm -- 3.4.6 The Least Recently Used (LRU) Page Replacement Algorithm -- 3.4.7 Simulating LRU in Software -- 3.4.8 The Working Set Page Replacement Algorithm -- 3.4.9 The WSClock Page Replacement Algorithm -- 3.4.10 Summary of Page Replacement Algorithms -- 3.5 DESIGN ISSUES FOR PAGING SYSTEMS -- 3.5.1 Local versus Global Allocation Policies -- 3.5.2 Load Control -- 3.5.3 Page Size -- 3.5.4 Separate Instruction and Data Spaces -- 3.5.5 Shared Pages -- 3.5.6 Shared Libraries -- 3.5.7 Mapped Files -- 3.5.8 Cleaning Policy -- 3.5.9 Virtual Memory Interface -- 3.6 IMPLEMENTATION ISSUES -- 3.6.1 Operating System Involvement with Paging -- 3.6.2 Page Fault Handling -- 3.6.3 Instruction Backup -- 3.6.4 Locking Pages in Memory -- 3.6.5 Backing Store -- 3.6.6 Separation of Policy and Mechanism -- 3.7 SEGMENTATION -- 3.7.1 Implementation of Pure Segmentation -- 3.7.2 Segmentation with Paging: MULTICS -- 3.7.3 Segmentation with Paging: The Intel x86 -- 3.8 RESEARCH ON MEMORY MANAGEMENT -- 3.9 SUMMARY -- 4 FILE SYSTEMS -- 4.1 FILES -- 4.1.1 File Naming -- 4.1.2 File Structure -- 4.1.3 File Types -- 4.1.4 File Access -- 4.1.5 File Attributes -- 4.1.6 File Operations -- 4.1.7 An Example Program Using File-System Calls -- 4.2 DIRECTORIES -- 4.2.1 Single-Level Directory Systems -- 4.2.2 Hierarchical Directory Systems -- 4.2.3 Path Names -- 4.2.4 Directory Operations -- 4.3 FILE-SYSTEM IMPLEMENTATION -- 4.3.1 File-System Layout -- 4.3.2 Implementing Files -- 4.3.3 Implementing Directories -- 4.3.4 Shared Files -- 4.3.5 Log-Structured File Systems -- 4.3.6 Journaling File Systems -- 4.3.7 Virtual File Systems -- 4.4 FILE-SYSTEM MANAGEMENT AND OPTIMIZATION -- 4.4.1 Disk-Space Management -- 4.4.2 File-System Backups -- 4.4.3 File-System Consistency. 4.4.4 File-System Performance -- 4.4.5 Defragmenting Disks -- 4.5 EXAMPLE FILE SYSTEMS -- 4.5.1 The MS-DOS File System -- 4.5.2 The UNIX V7 File System -- 4.5.3 CD-ROM File Systems -- 4.6 RESEARCH ON FILE SYSTEMS -- 4.7 SUMMARY -- 5 INPUT/OUTPUT -- 5.1 PRINCIPLES OF I/O HARDWARE -- 5.1.1 I/O Devices -- 5.1.2 Device Controllers -- 5.1.3 Memory-Mapped I/O -- 5.1.4 Direct Memory Access -- 5.1.5 Interrupts Revisited -- 5.2 PRINCIPLES OF I/O SOFTWARE -- 5.2.1 Goals of the I/O Software -- 5.2.2 Programmed I/O -- 5.2.3 Interrupt-Driven I/O -- 5.2.4 I/O Using DMA -- 5.3 I/O SOFTWARE LAYERS -- 5.3.1 Interrupt Handlers -- 5.3.2 Device Drivers -- 5.3.3 Device-Independent I/O Software -- 5.3.4 User-Space I/O Software -- 5.4 DISKS -- 5.4.1 Disk Hardware -- 5.4.2 Disk Formatting -- 5.4.3 Disk Arm Scheduling Algorithms -- 5.4.4 Error Handling -- 5.4.5 Stable Storage -- 5.5 CLOCKS -- 5.5.1 Clock Hardware -- 5.5.2 Clock Software -- 5.5.3 Soft Timers -- 5.6 USER INTERFACES: KEYBOARD, MOUSE, MONITOR -- 5.6.1 Input Software -- 5.6.2 Output Software -- 5.7 THIN CLIENTS -- 5.8 POWER MANAGEMENT -- 5.8.1 Hardware Issues -- 5.8.2 Operating System Issues -- 5.8.3 Application Program Issues -- 5.9 RESEARCH ON INPUT/OUTPUT -- 5.10 SUMMARY -- 6 DEADLOCKS -- 6.1 RESOURCES -- 6.1.1 Preemptable and Nonpreemptable Resources -- 6.1.2 Resource Acquisition -- 6.2 INTRODUCTION TO DEADLOCKS -- 6.2.1 Conditions for Resource Deadlocks -- 6.2.2 Deadlock Modeling -- 6.3 THE OSTRICH ALGORITHM -- 6.4 DEADLOCK DETECTION AND RECOVERY -- 6.4.1 Deadlock Detection with One Resource of Each Type -- 6.4.2 Deadlock Detection with Multiple Resources of Each Type -- 6.4.3 Recovery from Deadlock -- 6.5 DEADLOCK AVOIDANCE -- 6.5.1 Resource Trajectories -- 6.5.2 Safe and Unsafe States -- 6.5.3 The Banker's Algorithm for a Single Resource -- 6.5.4 The Banker's Algorithm for Multiple Resources. 6.6 DEADLOCK PREVENTION -- 6.6.1 Attacking the Mutual-Exclusion Condition -- 6.6.2 Attacking the Hold-and-Wait Condition -- 6.6.3 Attacking the No-Preemption Condition -- 6.6.4 Attacking the Circular Wait Condition -- 6.7 OTHER ISSUES -- 6.7.1 Two-Phase Locking -- 6.7.2 Communication Deadlocks -- 6.7.3 Livelock -- 6.7.4 Starvation -- 6.8 RESEARCH ON DEADLOCKS -- 6.9 SUMMARY -- 7 VIRTUALIZATION AND THE CLOUD -- 7.1 HISTORY -- 7.2 REQUIREMENTS FOR VIRTUALIZATION -- 7.3 TYPE 1 AND TYPE 2 HYPERVISORS -- 7.4 TECHNIQUES FOR EFFICIENT VIRTUALIZATION -- 7.4.1 Virtualizing the Unvirtualizable -- 7.4.2 The Cost of Virtualization -- 7.5 ARE HYPERVISORS MICROKERNELS DONE RIGHT? -- 7.6 MEMORY VIRTUALIZATION -- 7.7 I/O VIRTUALIZATION -- 7.8 VIRTUAL APPLIANCES -- 7.9 VIRTUAL MACHINES ON MULTICORE CPUS -- 7.10 LICENSING ISSUES -- 7.11 CLOUDS -- 7.11.1 Clouds as a Service -- 7.11.2 Virtual Machine Migration -- 7.11.3 Checkpointing -- 7.12 CASE STUDY: VMWARE -- 7.12.1 The Early History of VMware -- 7.12.2 VMware Workstation -- 7.12.3 Challenges in Bringing Virtualization to the x86 -- 7.12.4 VMware Workstation: Solution Overview -- 7.12.5 The Evolution of VMware Workstation -- 7.12.6 ESX Server: VMware's type 1 Hypervisor -- 7.13 RESEARCH ON VIRTUALIZATION AND THE CLOUD -- 8 MULTIPLE PROCESSOR SYSTEMS -- 8.1 MULTIPROCESSORS -- 8.1.1 Multiprocessor Hardware -- 8.1.2 Multiprocessor Operating System Types -- 8.1.3 Multiprocessor Synchronization -- 8.1.4 Multiprocessor Scheduling -- 8.2 MULTICOMPUTERS -- 8.2.1 Multicomputer Hardware -- 8.2.2 Low-Level Communication Software -- 8.2.3 User-Level Communication Software -- 8.2.4 Remote Procedure Call -- 8.2.5 Distributed Shared Memory -- 8.2.6 Multicomputer Scheduling -- 8.3 DISTRIBUTED SYSTEMS -- 8.3.1 Network Hardware -- 8.3.2 Network Services and Protocols -- 8.3.3 Document-Based Middleware. 8.3.4 File-System-Based Middleware. |
| Record Nr. | UNINA-9910153253803321 |
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Tanenbaum Andrew S. <1944->
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| Harlow, England : , : Pearson, , [2014] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Structured computer organization / / Andrew S. Tanenbaum, Todd Austin ; international edition contributions by B.R. Chandavarkar
| Structured computer organization / / Andrew S. Tanenbaum, Todd Austin ; international edition contributions by B.R. Chandavarkar |
| Autore | Tanenbaum Andrew S. <1944-> |
| Edizione | [Sixth, international edition.] |
| Pubbl/distr/stampa | Boston : , : Pearson, , [2013] |
| Descrizione fisica | 1 online resource (776 pages) |
| Disciplina | 001.642 |
| Collana | Always learning |
| Soggetto topico | Computer programming |
| ISBN | 0-273-77533-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- CONTENTS -- PREFACE -- 1 INTRODUCTION -- 1.1 STRUCTURED COMPUTER ORGANIZATION -- 1.1.1 Languages, Levels, and Virtual Machines -- 1.1.2 Contemporary Multilevel Machines -- 1.1.3 Evolution of Multilevel Machines -- 1.2 MILESTONES IN COMPUTER ARCHITECTURE -- 1.2.1 The Zeroth Generation-Mechanical Computers (1642-1945) -- 1.2.2 The First Generation-Vacuum Tubes (1945-1955) -- 1.2.3 The Second Generation-Transistors (1955-1965) -- 1.2.4 The Third Generation-Integrated Circuits (1965-1980) -- 1.2.5 The Fourth Generation-Very Large Scale Integration (1980-?) -- 1.2.6 The Fifth Generation-Low-Power and Invisible Computers -- 1.3 THE COMPUTER ZOO -- 1.3.1 Technological and Economic Forces -- 1.3.2 The Computer Spectrum -- 1.3.3 Disposable Computers -- 1.3.4 Microcontrollers -- 1.3.5 Mobile and Game Computers -- 1.3.6 Personal Computers -- 1.3.7 Servers -- 1.3.8 Mainframes -- 1.4 EXAMPLE COMPUTER FAMILIES -- 1.4.1 Introduction to the x86 Architecture -- 1.4.2 Introduction to the ARM Architecture -- 1.4.3 Introduction to the AVR Architecture -- 1.5 METRIC UNITS -- 1.6 OUTLINE OF THIS BOOK -- 2 COMPUTER SYSTEMS -- 2.1 PROCESSORS -- 2.1.1 CPU Organization -- 2.1.2 Instruction Execution -- 2.1.3 RISC versus CISC -- 2.1.4 Design Principles for Modern Computers -- 2.1.5 Instruction-Level Parallelism -- 2.1.6 Processor-Level Parallelism -- 2.2 PRIMARYMEMORY -- 2.2.1 Bits -- 2.2.2 Memory Addresses -- 2.2.3 Byte Ordering -- 2.2.4 Error-Correcting Codes -- 2.2.5 Cache Memory -- 2.2.6 Memory Packaging and Types -- 2.3 SECONDARYMEMORY -- 2.3.1 Memory Hierarchies -- 2.3.2 Magnetic Disks -- 2.3.3 IDE Disks -- 2.3.4 SCSI Disks -- 2.3.5 RAID -- 2.3.6 Solid-State Disks -- 2.3.7 CD-ROMs -- 2.3.8 CD-Recordables -- 2.3.9 CD-Rewritables -- 2.3.10 DVD -- 2.3.11 Blu-ray -- 2.4 INPUT/OUTPUT -- 2.4.1 Buses -- 2.4.2 Terminals -- 2.4.3 Mice -- 2.4.4 Game Controllers.
2.4.5 Printers -- 2.4.6 Telecommunications Equipment -- 2.4.7 Digital Cameras -- 2.4.8 Character Codes -- 2.5 SUMMARY -- 3 THE DIGITAL LOGIC LEVEL -- 3.1 GATES AND BOOLEAN ALGEBRA -- 3.1.1 Gates -- 3.1.2 Boolean Algebra -- 3.1.3 Implementation of Boolean Functions -- 3.1.4 Circuit Equivalence -- 3.2 BASIC DIGITAL LOGIC CIRCUITS -- 3.2.1 Integrated Circuits -- 3.2.2 Combinational Circuits -- 3.2.3 Arithmetic Circuits -- 3.2.4 Clocks -- 3.3 MEMORY -- 3.3.1 Latches -- 3.3.2 Flip-Flops -- 3.3.3 Registers -- 3.3.4 Memory Organization -- 3.3.5 Memory Chips -- 3.3.6 RAMs and ROMs -- 3.4 CPU CHIPS AND BUSES -- 3.4.1 CPU Chips -- 3.4.2 Computer Buses -- 3.4.3 Bus Width -- 3.4.4 Bus Clocking -- 3.4.5 Bus Arbitration -- 3.4.6 Bus Operations -- 3.5 EXAMPLE CPU CHIPS -- 3.5.1 The Intel Core i7 -- 3.5.2 The Texas Instruments OMAP4430 System-on-a-Chip -- 3.5.3 The Atmel ATmega168 Microcontroller -- 3.6 EXAMPLE BUSES -- 3.6.1 The PCI Bus -- 3.6.2 PCI Express -- 3.6.3 The Universal Serial Bus -- 3.7 INTERFACING -- 3.7.1 I/O Interfaces -- 3.7.2 Address Decoding -- 3.8 SUMMARY -- 4 THE MICROARCHITECTURE LEVEL -- 4.1 AN EXAMPLE MICROARCHITECTURE -- 4.1.1 The Data Path -- 4.1.2 Microinstructions -- 4.1.3 Microinstruction Control: The Mic-1 -- 4.2 AN EXAMPLE ISA: IJVM -- 4.2.1 Stacks -- 4.2.2 The IJVM Memory Model -- 4.2.3 The IJVM Instruction Set -- 4.2.4 Compiling Java to IJVM -- 4.3 AN EXAMPLE IMPLEMENTATION -- 4.3.1 Microinstructions and Notation -- 4.3.2 Implementation of IJVM Using the Mic-1 -- 4.4 DESIGN OF THE MICROARCHITECTURE LEVEL -- 4.4.1 Speed versus Cost -- 4.4.2 Reducing the Execution Path Length -- 4.4.3 A Design with Prefetching: The Mic-2 -- 4.4.4 A Pipelined Design: The Mic-3 -- 4.4.5 A Seven-Stage Pipeline: The Mic-4 -- 4.5 IMPROVING PERFORMANCE -- 4.5.1 Cache Memory -- 4.5.2 Branch Prediction -- 4.5.3 Out-of-Order Execution and Register Renaming. 4.5.4 Speculative Execution -- 4.6 EXAMPLES OF THE MICROARCHITECTURE LEVEL -- 4.6.1 The Microarchitecture of the Core i7 CPU -- 4.6.2 The Microarchitecture of the OMAP4430 CPU -- 4.6.3 The Microarchitecture of the ATmega168 Microcontroller -- 4.7 COMPARISON OF THE I7, OMAP4430, AND ATMEGA168 -- 4.8 SUMMARY -- 5 THE INSTRUCTION SET -- 5.1 OVERVIEW OF THE ISA LEVEL -- 5.1.1 Properties of the ISA Level -- 5.1.2 Memory Models -- 5.1.3 Registers -- 5.1.4 Instructions -- 5.1.5 Overview of the Core i7 ISA Level -- 5.1.6 Overview of the OMAP4430 ARM ISA Level -- 5.1.7 Overview of the ATmega168 AVR ISA Level -- 5.2 DATA TYPES -- 5.2.1 Numeric Data Types -- 5.2.2 Nonnumeric Data Types -- 5.2.3 Data Types on the Core i7 -- 5.2.4 Data Types on the OMAP4430 ARM CPU -- 5.2.5 Data Types on the ATmega168 AVR CPU -- 5.3 INSTRUCTION FORMATS -- 5.3.1 Design Criteria for Instruction Formats -- 5.3.2 Expanding Opcodes -- 5.3.3 The Core i7 Instruction Formats -- 5.3.4 The OMAP4430 ARM CPU Instruction Formats -- 5.3.5 The ATmega168 AVR Instruction Formats -- 5.4 ADDRESSING -- 5.4.1 Addressing Modes -- 5.4.2 Immediate Addressing -- 5.4.3 Direct Addressing -- 5.4.4 Register Addressing -- 5.4.5 Register Indirect Addressing -- 5.4.6 Indexed Addressing -- 5.4.7 Based-Indexed Addressing -- 5.4.8 Stack Addressing -- 5.4.9 Addressing Modes for Branch Instructions -- 5.4.10 Orthogonality of Opcodes and Addressing Modes -- 5.4.11 The Core i7 Addressing Modes -- 5.4.12 The OMAP4440 ARM CPU Addressing Modes -- 5.4.13 The ATmega168 AVR Addressing Modes -- 5.4.14 Discussion of Addressing Modes -- 5.5 INSTRUCTION TYPES -- 5.5.1 Data Movement Instructions -- 5.5.2 Dyadic Operations -- 5.5.3 Monadic Operations -- 5.5.4 Comparisons and Conditional Branches -- 5.5.5 Procedure Call Instructions -- 5.5.6 Loop Control -- 5.5.7 Input/Output -- 5.5.8 The Core i7 Instructions. 5.5.9 The OMAP4430 ARM CPU Instructions -- 5.5.10 The ATmega168 AVR Instructions -- 5.5.11 Comparison of Instruction Sets -- 5.6 FLOWOF CONTROL -- 5.6.1 Sequential Flow of Control and Branches -- 5.6.2 Procedures -- 5.6.3 Coroutines -- 5.6.4 Traps -- 5.6.5 Interrupts -- 5.7 A DETAILED EXAMPLE: THE TOWERS OF HANOI -- 5.7.1 The Towers of Hanoi in Core i7 Assembly Language -- 5.7.2 The Towers of Hanoi in OMAP4430 ARM Assembly Language -- 5.8 THE IA-64 ARCHITECTURE AND THE ITANIUM 2 -- 5.8.1 The Problem with the IA-32 ISA -- 5.8.2 The IA-64 Model: Explicitly Parallel Instruction Computing -- 5.8.3 Reducing Memory References -- 5.8.4 Instruction Scheduling -- 5.8.5 Reducing Conditional Branches: Predication -- 5.8.6 Speculative Loads -- 5.9 SUMMARY -- 6 THE OPERATING SYSTEM -- 6.1 VIRTUAL MEMORY -- 6.1.1 Paging -- 6.1.2 Implementation of Paging -- 6.1.3 Demand Paging and the Working-Set Model -- 6.1.4 Page-Replacement Policy -- 6.1.5 Page Size and Fragmentation -- 6.1.6 Segmentation -- 6.1.7 Implementation of Segmentation -- 6.1.8 Virtual Memory on the Core i7 -- 6.1.9 Virtual Memory on the OMAP4430 ARM CPU -- 6.1.10 Virtual Memory and Caching -- 6.2 HARDWARE VIRTUALIZATION -- 6.2.1 Hardware Virtualization on the Core I7 -- 6.3 OSM-LEVEL I/O INSTRUCTIONS -- 6.3.1 Files -- 6.3.2 Implementation of OSM-Level I/O Instructions -- 6.3.3 Directory Management Instructions -- 6.4 OSM-LEVEL INSTRUCTIONS FOR PARALLEL PROCESSING -- 6.4.1 Process Creation -- 6.4.2 Race Conditions -- 6.4.3 Process Synchronization Using Semaphores -- 6.5 EXAMPLE OPERATING SYSTEMS -- 6.5.1 Introduction -- 6.5.2 Examples of Virtual Memory -- 6.5.3 Examples of OS-Level I/O -- 6.5.4 Examples of Process Management -- 6.6 SUMMARY -- 7 THE ASSEMBLY LANGUAGE LEVEL -- 7.1 INTRODUCTION TO ASSEMBLY LANGUAGE -- 7.1.1 What Is an Assembly Language? -- 7.1.2 Why Use Assembly Language?. 7.1.3 Format of an Assembly Language Statement -- 7.1.4 Pseudoinstructions -- 7.2 MACROS -- 7.2.1 Macro Definition, Call, and Expansion -- 7.2.2 Macros with Parameters -- 7.2.3 Advanced Features -- 7.2.4 Implementation of a Macro Facility in an Assembler -- 7.3 THE ASSEMBLY PROCESS -- 7.3.1 Two-Pass Assemblers -- 7.3.2 Pass One -- 7.3.3 Pass Two -- 7.3.4 The Symbol Table -- 7.4 LINKING AND LOADING -- 7.4.1 Tasks Performed by the Linker -- 7.4.2 Structure of an Object Module -- 7.4.3 Binding Time and Dynamic Relocation -- 7.4.4 Dynamic Linking -- 7.5 SUMMARY -- 8 PARALLEL COMPUTER ARCHITECTURES -- 8.1 ON-CHIP PARALELLISM -- 8.1.1 Instruction-Level Parallelism -- 8.1.2 On-Chip Multithreading -- 8.1.3 Single-Chip Multiprocessors -- 8.2 COPROCESSORS -- 8.2.1 Network Processors -- 8.2.2 Graphics Processors -- 8.2.3 Cryptoprocessors -- 8.3 SHARED-MEMORY MULTIPROCESSORS -- 8.3.1 Multiprocessors vs. Multicomputers -- 8.3.2 Memory Semantics -- 8.3.3 UMA Symmetric Multiprocessor Architectures -- 8.3.4 NUMA Multiprocessors -- 8.3.5 COMA Multiprocessors -- 8.4 MESSAGE-PASSING MULTICOMPUTERS -- 8.4.1 Interconnection Networks -- 8.4.2 MPPs-Massively Parallel Processors -- 8.4.3 Cluster Computing -- 8.4.4 Communication Software for Multicomputers -- 8.4.5 Scheduling -- 8.4.6 Application-Level Shared Memory -- 8.4.7 Performance -- 8.5 GRID COMPUTING -- 8.6 SUMMARY -- 9 BIBLIOGRAPHY -- A: BINARY NUMBERS -- A.1 FINITE-PRECISION NUMBERS -- A.2 RADIX NUMBER SYSTEMS -- A.3 CONVERSION FROM ONE RADIX TO ANOTHER -- A.4 NEGATIVE BINARY NUMBERS -- A.5 BINARY ARITHMETIC -- B: FLOATING-POINT NUMBERS -- B.1 PRINCIPLES OF FLOATING POINT -- B.2 IEEE FLOATING-POINT STANDARD 754 -- C: ASSEMBLY LANGUAGE PROGRAMMING -- C.1 OVERVIEW -- C.1.1 Assembly Language -- C.1.2 A Small Assembly Language Program -- C.2 THE 8088 PROCESSOR -- C.2.1 The Processor Cycle -- C.2.2 The General Registers. C.2.3 Pointer Registers. |
| Record Nr. | UNINA-9910150213803321 |
|
Tanenbaum Andrew S. <1944->
|
||
| Boston : , : Pearson, , [2013] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||