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2003 International Symposium on System-on-Chip
| 2003 International Symposium on System-on-Chip |
| Pubbl/distr/stampa | [Place of publication not identified], : I E E E, 2003 |
| Disciplina | 004.16 |
| Altri autori (Persone) |
NurmiJari
TakalaJarmo HämäläinenTimo D |
| Soggetto topico |
Electrical & Computer Engineering
Electrical Engineering Engineering & Applied Sciences |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996202927103316 |
| [Place of publication not identified], : I E E E, 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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2003 International Symposium on System-on-Chip
| 2003 International Symposium on System-on-Chip |
| Pubbl/distr/stampa | [Place of publication not identified], : I E E E, 2003 |
| Disciplina | 004.16 |
| Altri autori (Persone) |
NurmiJari
TakalaJarmo HämäläinenTimo D |
| Soggetto topico |
Electrical & Computer Engineering
Electrical Engineering Engineering & Applied Sciences |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910872465703321 |
| [Place of publication not identified], : I E E E, 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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2004 International Symposium on System-on-Chip : proceedings : [November 16-18, 2004, Tampere, Finland
| 2004 International Symposium on System-on-Chip : proceedings : [November 16-18, 2004, Tampere, Finland |
| Pubbl/distr/stampa | [Place of publication not identified], : Tampere University of Technology, 2004 |
| Disciplina | 621.3815 |
| Soggetto topico |
Systems on a chip
Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996202167203316 |
| [Place of publication not identified], : Tampere University of Technology, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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2004 International Symposium on System-on-Chip : proceedings : [November 16-18, 2004, Tampere, Finland
| 2004 International Symposium on System-on-Chip : proceedings : [November 16-18, 2004, Tampere, Finland |
| Pubbl/distr/stampa | [Place of publication not identified], : Tampere University of Technology, 2004 |
| Disciplina | 621.3815 |
| Soggetto topico |
Systems on a chip
Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910872534703321 |
| [Place of publication not identified], : Tampere University of Technology, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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2006 International Conference on System-on-Chip
| 2006 International Conference on System-on-Chip |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2006 |
| Soggetto topico |
Systems on a chip
Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-5090-9355-9
1-4244-0622-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996215462503316 |
| [Place of publication not identified], : IEEE, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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2006 International Conference on System-on-Chip
| 2006 International Conference on System-on-Chip |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2006 |
| Soggetto topico |
Systems on a chip
Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-5090-9355-9
1-4244-0622-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910146676803321 |
| [Place of publication not identified], : IEEE, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings / / edited by Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, Stamatis Vassiliadis
| Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings / / edited by Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, Stamatis Vassiliadis |
| Edizione | [1st ed. 2005.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 |
| Descrizione fisica | 1 online resource (XV, 476 p.) |
| Disciplina | 004.2/2 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynote -- Platform Thinking in Embedded Systems -- Reconfigurable System Design and Implementations -- Interprocedural Optimization for Dynamic Hardware Configurations -- Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques -- Reconfigurable Multiple Operation Array -- RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration -- Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping -- Automatic FIR Filter Generation for FPGAs -- Two-Dimensional Fast Cosine Transform for Vector-STA Architectures -- Configurable Computing for High-Security/High-Performance Ambient Systems -- FPL-3E: Towards Language Support for Reconfigurable Packet Processing -- Processor Architectures, Design and Simulation -- Flux Caches: What Are They and Are They Useful? -- First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption -- A Novel JAVA Processor for Embedded Devices -- Formal Specification of a Protocol Processor -- Tuning a Protocol Processor Architecture Towards DSP Operations -- Observations on Power-Efficiency Trends in Mobile Communication Devices -- CORDIC-Augmented Sandbridge Processor for Channel Equalization -- Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic -- Exploiting Intra-function Correlation with the Global History Stack -- Power Efficient Instruction Caches for Embedded Systems -- Micro-architecture Performance Estimation by Formula -- Offline Phase Analysis and Optimization for Multi-configuration Processors -- Hardware Cost Estimation for Application-Specific Processor Design -- Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures -- Generating Stream Based Code from Plain C -- Fast Real-Time Job Selection with Resource Constraints Under Earliest Deadline First -- A Programming Model for an Embedded Media Processing Architecture -- Automatic ADL-Based Assembler Generation for ASIP Programming Support -- Sandbridge Software Tools -- Architectures and Implementations -- A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems -- Pattern Matching Acceleration for Network Intrusion Detection Systems -- Real-Time Stereo Vision on a Reconfigurable System -- Application of Very Fast Simulated Reannealing (VFSR) to Low Power Design -- Compressed Swapping for NAND Flash Memory Based Embedded Systems -- A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms -- A Scalable Embedded JPEG2000 Architecture -- A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design -- Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context -- DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor -- System Level Design, Modeling and Simulation -- Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets -- High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks -- The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models -- Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design Flow -- Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms -- DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context -- SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC -- Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications -- A Case for Visualization-Integrated System-Level Design Space Exploration -- Mixed Virtual/Real Prototypes for Incremental System Design – A Proof of Concept. |
| Record Nr. | UNISA-996465831203316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Handbook of Signal Processing Systems / / edited by Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala
| Handbook of Signal Processing Systems / / edited by Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala |
| Edizione | [3rd ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (1,203 pages) |
| Disciplina | 621.3822 |
| Soggetto topico |
Signal processing
Image processing Speech processing systems Electrical engineering Microprocessors Signal, Image and Speech Processing Communications Engineering, Networks Processor Architectures |
| ISBN | 3-319-91734-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | 1 Signal Processing Methods for Light Field Displays. 2 Inertial Sensors and Their Applications -- 3 Finding It Now: Construction and Configuration of Networked Classifiers in Real-Time Stream Mining Systems -- 4 Deep Neural Networks: A Signal Processing Perspective -- 5 High Dynamic Range Video Cooling -- 6 Signal Processing for Control -- 7 MPEG Reconfigurable Video Coding -- 8 Signal Processing for Wireless Transceivers -- 9 Signal Processing for Radio Astronomy -- 10 Distributed Smart Cameras and Distributed Computer Vision -- 11 Arithmetic -- 12 Coarse Grained Reconfigurable Array Architectures -- 13 High Performance Stream Processing on FPGA -- 14 Application-specific Accelerators for Communications -- 15 System-on-chip Architectures for Data Analytics -- 16 Architectures for Stereo Vision -- 17 Hardware Architectures for the Fast Fourier Transform -- 18 Programmable Architectures for Histogram of Oriented Gradients Processing -- 19 Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-on-chip -- 20 Intermediate Representations for Simulation and Implementation -- 21 Throughput Analysis of Dataflow Graphs -- 22 Dataflow Modeling for Reconfigurable Signal Processing Systems -- 23 Integrated Modeling Using Finite State Machines and Dataflow Graphs -- 24 Kahn Process Networks and a Reactive Extension -- 25 Decidable Signal Processing Dataflow Graphs -- 26 Systolic Arrays -- 27 Compiling for VLIW DSPs -- 28 Software Compilation Techniques for Heterogeneous Embedded Multi-Core Systems -- 29 Analysis of Finite Word-Length Effects in Fixed-Point Systems -- 30 Models of Architecture for DSP Systems -- 31 Optimization of Number Representations -- 32 Dynamic Dataflow Graphs. |
| Record Nr. | UNINA-9910337660403321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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