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ARM system developer's guide [[electronic resource] ] : designing and optimizing system software / / Andrew N. Sloss, Dominic Symes, Chris Wright, with a contribution by John Rayfield
| ARM system developer's guide [[electronic resource] ] : designing and optimizing system software / / Andrew N. Sloss, Dominic Symes, Chris Wright, with a contribution by John Rayfield |
| Autore | Sloss Andrew N |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/ Morgan Kaufman, c2004 |
| Descrizione fisica | 1 online resource (703 p.) |
| Disciplina | 005.1 |
| Altri autori (Persone) |
SymesDominic
WrightChris <1953-> |
| Collana | The Morgan Kaufmann Series in Computer Architecture and Design |
| Soggetto topico |
Computer software - Development
RISC microprocessors Computer architecture |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-00723-4
9786611007232 0-08-049049-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; About the Authors; ARM System Developer's Guide Designing and Optimizing System Software; Copyright Page; Contents; Preface; Chapter 1. ARM Embedded Systems; 1.1 The RISC design philosophy; 1.2 The ARM Design Philosophy; 1.3 Embedded System Hardware; 1.4 Embedded System Software; 1.5 Summary; Chapter 2. ARM Processor Fundamentals; 2.1 Registers; 2.2 Current Program Status Register; 2.3 Pipeline; 2.4 Exceptions, Interrupts, and the Vector Table; 2.5 Core Extensions; 2.6 Architecture Revisions; 2.7 ARM Processor Families; 2.8 Summary
Chapter 3. Introduction to the ARM Instruction Set3.1 Data Processing Instructions; 3.2 Branch Instructions; 3.3 Load-Store Instructions; 3.4 Software Interrupt Instruction; 3.5 Program Status Register Instructions; 3.6 Loading Constants; 3.7 ARMv5E Extensions; 3.8 Conditional Execution; 3.9 Summary; Chapter 4. Introduction to the Thumb Instruction Set; 4.1 Thumb Register Usage; 4.2 ARM-Thumb Interworking; 4.3 Other Branch Instructions; 4.4 Data Processing Instructions; 4.5 Single-Register Load-Store Instructions; 4.6 Multiple-Register Load-Store Instructions; 4.7 Stack Instructions 4.8 Software Interrupt Instruction4.9 Summary; Chapter 5. Efficient C Programming; 5.1 Overview of C Compilers and Optimization; 5.2 Basic C Data Types; 5.3 C Looping Structures; 5.4 Register Allocation; 5.5 Function Calls; 5.6 Pointer Aliasing; 5.7 Structure Arrangement; 5.8 Bit-fields; 5.9 Unaligned Data and Endianness; 5.10 Division; 5.11 Floating Point; 5.12 Inline Functions and Inline Assembly; 5.13 Portability Issues; 5.14 Summary; Chapter 6. Writing and Optimizing ARM Assembly Code; 6.1 Writing Assembly Code; 6.2 Profiling and Cycle Counting; 6.3 Instruction Scheduling 6.4 Register Allocation6.5 Conditional Execution; 6.6 Looping Constructs; 6.7 Bit Manipulation; 6.8 Efficient Switches; 6.9 Handling Unaligned Data; 6.10 Summary; Chapter 7. Optimized Primitives; 7.1 Double-Precision Integer Multiplication; 7.2 Integer Normalization and Count Leading Zeros; 7.3 Division; 7.4 Square Roots; 7.5 Transcendental Functions: log, exp, sin, cos; 7.6 Endian Reversal and Bit Operations; 7.7 Saturated and Rounded Arithmetic; 7.8 Random Number Generation; 7.9 Summary; Chapter 8. Digital Signal Processing; 8.1 Representing a Digital Signal 8.2 Introduction to DSP on the ARM8.3 FIR filters; 8.4 IIR Filters; 8.5 The Discrete Fourier Transform; 8.6 Summary; Chapter 9. Exception and Interrupt Handling; 9.1 Exception Handling; 9.2 Interrupts; 9.3 Interrupt Handling Schemes; 9.4 Summary; Chapter 10. Firmware; 10.1 Firmware and Bootloader; 10.2 Example: Sandstone; 10.3 Summary; Chapter 11. Embedded Operating Systems; 11.1 Fundamental Components; 11.2 Example: Simple Little Operating System; 11.3 Summary; Chapter 12. Caches; 12.1 The Memory Hierarchy and Cache Memory; 12.2 Cache Architecture; 12.3 Cache Policy 12.4 Coprocessor 15 and Caches |
| Record Nr. | UNINA-9910450501903321 |
Sloss Andrew N
|
||
| Amsterdam ; ; Boston, : Elsevier/ Morgan Kaufman, c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ARM system developer's guide [[electronic resource] ] : designing and optimizing system software / / Andrew N. Sloss, Dominic Symes, Chris Wright, with a contribution by John Rayfield
| ARM system developer's guide [[electronic resource] ] : designing and optimizing system software / / Andrew N. Sloss, Dominic Symes, Chris Wright, with a contribution by John Rayfield |
| Autore | Sloss Andrew N |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/ Morgan Kaufman, c2004 |
| Descrizione fisica | 1 online resource (703 p.) |
| Disciplina | 005.1 |
| Altri autori (Persone) |
SymesDominic
WrightChris <1953-> |
| Collana | The Morgan Kaufmann Series in Computer Architecture and Design |
| Soggetto topico |
Computer software - Development
RISC microprocessors Computer architecture |
| ISBN |
1-281-00723-4
9786611007232 0-08-049049-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; About the Authors; ARM System Developer's Guide Designing and Optimizing System Software; Copyright Page; Contents; Preface; Chapter 1. ARM Embedded Systems; 1.1 The RISC design philosophy; 1.2 The ARM Design Philosophy; 1.3 Embedded System Hardware; 1.4 Embedded System Software; 1.5 Summary; Chapter 2. ARM Processor Fundamentals; 2.1 Registers; 2.2 Current Program Status Register; 2.3 Pipeline; 2.4 Exceptions, Interrupts, and the Vector Table; 2.5 Core Extensions; 2.6 Architecture Revisions; 2.7 ARM Processor Families; 2.8 Summary
Chapter 3. Introduction to the ARM Instruction Set3.1 Data Processing Instructions; 3.2 Branch Instructions; 3.3 Load-Store Instructions; 3.4 Software Interrupt Instruction; 3.5 Program Status Register Instructions; 3.6 Loading Constants; 3.7 ARMv5E Extensions; 3.8 Conditional Execution; 3.9 Summary; Chapter 4. Introduction to the Thumb Instruction Set; 4.1 Thumb Register Usage; 4.2 ARM-Thumb Interworking; 4.3 Other Branch Instructions; 4.4 Data Processing Instructions; 4.5 Single-Register Load-Store Instructions; 4.6 Multiple-Register Load-Store Instructions; 4.7 Stack Instructions 4.8 Software Interrupt Instruction4.9 Summary; Chapter 5. Efficient C Programming; 5.1 Overview of C Compilers and Optimization; 5.2 Basic C Data Types; 5.3 C Looping Structures; 5.4 Register Allocation; 5.5 Function Calls; 5.6 Pointer Aliasing; 5.7 Structure Arrangement; 5.8 Bit-fields; 5.9 Unaligned Data and Endianness; 5.10 Division; 5.11 Floating Point; 5.12 Inline Functions and Inline Assembly; 5.13 Portability Issues; 5.14 Summary; Chapter 6. Writing and Optimizing ARM Assembly Code; 6.1 Writing Assembly Code; 6.2 Profiling and Cycle Counting; 6.3 Instruction Scheduling 6.4 Register Allocation6.5 Conditional Execution; 6.6 Looping Constructs; 6.7 Bit Manipulation; 6.8 Efficient Switches; 6.9 Handling Unaligned Data; 6.10 Summary; Chapter 7. Optimized Primitives; 7.1 Double-Precision Integer Multiplication; 7.2 Integer Normalization and Count Leading Zeros; 7.3 Division; 7.4 Square Roots; 7.5 Transcendental Functions: log, exp, sin, cos; 7.6 Endian Reversal and Bit Operations; 7.7 Saturated and Rounded Arithmetic; 7.8 Random Number Generation; 7.9 Summary; Chapter 8. Digital Signal Processing; 8.1 Representing a Digital Signal 8.2 Introduction to DSP on the ARM8.3 FIR filters; 8.4 IIR Filters; 8.5 The Discrete Fourier Transform; 8.6 Summary; Chapter 9. Exception and Interrupt Handling; 9.1 Exception Handling; 9.2 Interrupts; 9.3 Interrupt Handling Schemes; 9.4 Summary; Chapter 10. Firmware; 10.1 Firmware and Bootloader; 10.2 Example: Sandstone; 10.3 Summary; Chapter 11. Embedded Operating Systems; 11.1 Fundamental Components; 11.2 Example: Simple Little Operating System; 11.3 Summary; Chapter 12. Caches; 12.1 The Memory Hierarchy and Cache Memory; 12.2 Cache Architecture; 12.3 Cache Policy 12.4 Coprocessor 15 and Caches |
| Record Nr. | UNINA-9910783135403321 |
|
Sloss Andrew N
|
||
| Amsterdam ; ; Boston, : Elsevier/ Morgan Kaufman, c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ARM system developer's guide : designing and optimizing system software / / Andrew N. Sloss, Dominic Symes, Chris Wright, with a contribution by John Rayfield
| ARM system developer's guide : designing and optimizing system software / / Andrew N. Sloss, Dominic Symes, Chris Wright, with a contribution by John Rayfield |
| Autore | Sloss Andrew N |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/ Morgan Kaufman, c2004 |
| Descrizione fisica | 1 online resource (703 p.) |
| Disciplina | 005.1 |
| Altri autori (Persone) |
SymesDominic
WrightChris <1953-> |
| Collana | The Morgan Kaufmann Series in Computer Architecture and Design |
| Soggetto topico |
Computer software - Development
RISC microprocessors Computer architecture |
| ISBN |
1-281-00723-4
9786611007232 0-08-049049-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; About the Authors; ARM System Developer's Guide Designing and Optimizing System Software; Copyright Page; Contents; Preface; Chapter 1. ARM Embedded Systems; 1.1 The RISC design philosophy; 1.2 The ARM Design Philosophy; 1.3 Embedded System Hardware; 1.4 Embedded System Software; 1.5 Summary; Chapter 2. ARM Processor Fundamentals; 2.1 Registers; 2.2 Current Program Status Register; 2.3 Pipeline; 2.4 Exceptions, Interrupts, and the Vector Table; 2.5 Core Extensions; 2.6 Architecture Revisions; 2.7 ARM Processor Families; 2.8 Summary
Chapter 3. Introduction to the ARM Instruction Set3.1 Data Processing Instructions; 3.2 Branch Instructions; 3.3 Load-Store Instructions; 3.4 Software Interrupt Instruction; 3.5 Program Status Register Instructions; 3.6 Loading Constants; 3.7 ARMv5E Extensions; 3.8 Conditional Execution; 3.9 Summary; Chapter 4. Introduction to the Thumb Instruction Set; 4.1 Thumb Register Usage; 4.2 ARM-Thumb Interworking; 4.3 Other Branch Instructions; 4.4 Data Processing Instructions; 4.5 Single-Register Load-Store Instructions; 4.6 Multiple-Register Load-Store Instructions; 4.7 Stack Instructions 4.8 Software Interrupt Instruction4.9 Summary; Chapter 5. Efficient C Programming; 5.1 Overview of C Compilers and Optimization; 5.2 Basic C Data Types; 5.3 C Looping Structures; 5.4 Register Allocation; 5.5 Function Calls; 5.6 Pointer Aliasing; 5.7 Structure Arrangement; 5.8 Bit-fields; 5.9 Unaligned Data and Endianness; 5.10 Division; 5.11 Floating Point; 5.12 Inline Functions and Inline Assembly; 5.13 Portability Issues; 5.14 Summary; Chapter 6. Writing and Optimizing ARM Assembly Code; 6.1 Writing Assembly Code; 6.2 Profiling and Cycle Counting; 6.3 Instruction Scheduling 6.4 Register Allocation6.5 Conditional Execution; 6.6 Looping Constructs; 6.7 Bit Manipulation; 6.8 Efficient Switches; 6.9 Handling Unaligned Data; 6.10 Summary; Chapter 7. Optimized Primitives; 7.1 Double-Precision Integer Multiplication; 7.2 Integer Normalization and Count Leading Zeros; 7.3 Division; 7.4 Square Roots; 7.5 Transcendental Functions: log, exp, sin, cos; 7.6 Endian Reversal and Bit Operations; 7.7 Saturated and Rounded Arithmetic; 7.8 Random Number Generation; 7.9 Summary; Chapter 8. Digital Signal Processing; 8.1 Representing a Digital Signal 8.2 Introduction to DSP on the ARM8.3 FIR filters; 8.4 IIR Filters; 8.5 The Discrete Fourier Transform; 8.6 Summary; Chapter 9. Exception and Interrupt Handling; 9.1 Exception Handling; 9.2 Interrupts; 9.3 Interrupt Handling Schemes; 9.4 Summary; Chapter 10. Firmware; 10.1 Firmware and Bootloader; 10.2 Example: Sandstone; 10.3 Summary; Chapter 11. Embedded Operating Systems; 11.1 Fundamental Components; 11.2 Example: Simple Little Operating System; 11.3 Summary; Chapter 12. Caches; 12.1 The Memory Hierarchy and Cache Memory; 12.2 Cache Architecture; 12.3 Cache Policy 12.4 Coprocessor 15 and Caches |
| Record Nr. | UNINA-9910827091703321 |
|
Sloss Andrew N
|
||
| Amsterdam ; ; Boston, : Elsevier/ Morgan Kaufman, c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||