Arithmetic of Finite Fields [[electronic resource] ] : First International Workshop, WAIFI 2007, Madrid, Spain, June 21-22, 2007, Proceedings / / edited by Claude Carlet, Berk Sunar |
Edizione | [1st ed. 2007.] |
Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
Descrizione fisica | 1 online resource (XI, 360 p.) |
Disciplina | 512.3 |
Collana | Theoretical Computer Science and General Issues |
Soggetto topico |
Coding theory
Information theory Cryptography Data encryption (Computer science) Computer science—Mathematics Discrete mathematics Algorithms Coding and Information Theory Cryptology Discrete Mathematics in Computer Science Symbolic and Algebraic Manipulation |
ISBN | 3-540-73074-5 |
Formato | Materiale a stampa ![]() |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Structures in Finite Fields -- Explicit Factorizations of Cyclotomic and Dickson Polynomials over Finite Fields -- Some Notes on d-Form Functions with Difference-Balanced Property -- A Note on Modular Forms on Finite Upper Half Planes -- Efficient Implementation and Architectures -- A Coprocessor for the Final Exponentiation of the ? T Pairing in Characteristic Three -- VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors -- Efficient Multiplication Using Type 2 Optimal Normal Bases -- Efficient Finite Field Arithmetic -- Effects of Optimizations for Software Implementations of Small Binary Field Arithmetic -- Software Implementation of Arithmetic in -- Complexity Reduction of Constant Matrix Computations over the Binary Field -- Towards Optimal Toom-Cook Multiplication for Univariate and Multivariate Polynomials in Characteristic 2 and 0 -- Classification and Construction of Mappings over Finite Fields -- A Construction of Differentially 4-Uniform Functions from Commutative Semifields of Characteristic 2 -- Complete Mapping Polynomials over Finite Field F 16 -- On the Classification of 4 Bit S-Boxes -- The Simplest Method for Constructing APN Polynomials EA-Inequivalent to Power Functions -- Curve Algebra -- New Point Addition Formulae for ECC Applications -- Explicit Formulas for Real Hyperelliptic Curves of Genus 2 in Affine Representation -- The Quadratic Extension Extractor for (Hyper)Elliptic Curves in Odd Characteristic -- Cryptography -- On Kabatianskii-Krouk-Smeets Signatures -- Self-certified Signatures Based on Discrete Logarithms -- Attacking the Filter Generator over GF(2 m ) -- Codes -- Cyclic Additive and Quantum Stabilizer Codes -- Determining the Number of One-Weight Cyclic Codes When Length and Dimension Are Given -- Error Correcting Codes from Quasi-Hadamard Matrices -- Fast Computations of Gröbner Bases and Blind Recognitions of Convolutional Codes -- Discrete Structures -- A Twin for Euler’s ? Function in -- Discrete Phase-Space Structures and Mutually Unbiased Bases -- Some Novel Results of p-Adic Component of Primitive Sequences over Z/(p d ). |
Record Nr. | UNISA-996466075903316 |
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
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Lo trovi qui: Univ. di Salerno | ||
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Arithmetic of Finite Fields : First International Workshop, WAIFI 2007, Madrid, Spain, June 21-22, 2007, Proceedings / / edited by Claude Carlet, Berk Sunar |
Edizione | [1st ed. 2007.] |
Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
Descrizione fisica | 1 online resource (XI, 360 p.) |
Disciplina | 512.3 |
Collana | Theoretical Computer Science and General Issues |
Soggetto topico |
Coding theory
Information theory Cryptography Data encryption (Computer science) Computer science—Mathematics Discrete mathematics Algorithms Coding and Information Theory Cryptology Discrete Mathematics in Computer Science Symbolic and Algebraic Manipulation |
ISBN | 3-540-73074-5 |
Formato | Materiale a stampa ![]() |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Structures in Finite Fields -- Explicit Factorizations of Cyclotomic and Dickson Polynomials over Finite Fields -- Some Notes on d-Form Functions with Difference-Balanced Property -- A Note on Modular Forms on Finite Upper Half Planes -- Efficient Implementation and Architectures -- A Coprocessor for the Final Exponentiation of the ? T Pairing in Characteristic Three -- VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors -- Efficient Multiplication Using Type 2 Optimal Normal Bases -- Efficient Finite Field Arithmetic -- Effects of Optimizations for Software Implementations of Small Binary Field Arithmetic -- Software Implementation of Arithmetic in -- Complexity Reduction of Constant Matrix Computations over the Binary Field -- Towards Optimal Toom-Cook Multiplication for Univariate and Multivariate Polynomials in Characteristic 2 and 0 -- Classification and Construction of Mappings over Finite Fields -- A Construction of Differentially 4-Uniform Functions from Commutative Semifields of Characteristic 2 -- Complete Mapping Polynomials over Finite Field F 16 -- On the Classification of 4 Bit S-Boxes -- The Simplest Method for Constructing APN Polynomials EA-Inequivalent to Power Functions -- Curve Algebra -- New Point Addition Formulae for ECC Applications -- Explicit Formulas for Real Hyperelliptic Curves of Genus 2 in Affine Representation -- The Quadratic Extension Extractor for (Hyper)Elliptic Curves in Odd Characteristic -- Cryptography -- On Kabatianskii-Krouk-Smeets Signatures -- Self-certified Signatures Based on Discrete Logarithms -- Attacking the Filter Generator over GF(2 m ) -- Codes -- Cyclic Additive and Quantum Stabilizer Codes -- Determining the Number of One-Weight Cyclic Codes When Length and Dimension Are Given -- Error Correcting Codes from Quasi-Hadamard Matrices -- Fast Computations of Gröbner Bases and Blind Recognitions of Convolutional Codes -- Discrete Structures -- A Twin for Euler’s ? Function in -- Discrete Phase-Space Structures and Mutually Unbiased Bases -- Some Novel Results of p-Adic Component of Primitive Sequences over Z/(p d ). |
Record Nr. | UNINA-9910484408703321 |
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
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Lo trovi qui: Univ. Federico II | ||
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Cryptographic Hardware and Embedded Systems - CHES 2005 [[electronic resource] ] : 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings / / edited by Josyula R. Rao, Berk Sunar |
Edizione | [1st ed. 2005.] |
Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 |
Descrizione fisica | 1 online resource (XIV, 458 p.) |
Disciplina | 005.8/2 |
Collana | Security and Cryptology |
Soggetto topico |
Data encryption (Computer science)
Logic design Computer communication systems Special purpose computers Operating systems (Computers) Management information systems Computer science Cryptology Logic Design Computer Communication Networks Special Purpose and Application-Based Systems Operating Systems Management of Computing and Information Systems |
Formato | Materiale a stampa ![]() |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Side Channels I -- Resistance of Randomized Projective Coordinates Against Power Analysis -- Templates as Master Keys -- A Stochastic Model for Differential Side Channel Cryptanalysis -- Arithmetic for Cryptanalysis -- A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis -- Further Hidden Markov Model Cryptanalysis -- Low Resources -- Energy-Efficient Software Implementation of Long Integer Modular Arithmetic -- Short Memory Scalar Multiplication on Koblitz Curves -- Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 ?P -- Special Purpose Hardware -- SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers -- Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization -- Design of Testable Random Bit Generators -- Hardware Attacks and Countermeasures I -- Successfully Attacking Masked AES Hardware Implementations -- Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints -- Masking at Gate Level in the Presence of Glitches -- Arithmetic for Cryptography -- Bipartite Modular Multiplication -- Fast Truncated Multiplication for Cryptographic Applications -- Using an RSA Accelerator for Modular Inversion -- Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings -- Side Channel II (EM) -- EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA -- Security Limits for Compromising Emanations -- Security Evaluation Against Electromagnetic Analysis at Design Time -- Side Channel III -- On Second-Order Differential Power Analysis -- Improved Higher-Order Side-Channel Attacks with FPGA Experiments -- Trusted Computing -- Secure Data Management in Trusted Computing -- Hardware Attacks and Countermeasures II -- Data Remanence in Flash Memory Devices -- Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment -- Hardware Attacks and Countermeasures III -- DPA Leakage Models for CMOS Logic Circuits -- The “Backend Duplication” Method -- Efficient Hardware I -- Hardware Acceleration of the Tate Pairing in Characteristic Three -- Efficient Hardware for the Tate Pairing Calculation in Characteristic Three -- Efficient Hardware II -- AES on FPGA from the Fastest to the Smallest -- A Very Compact S-Box for AES. |
Record Nr. | UNISA-996465909203316 |
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 | ||
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Lo trovi qui: Univ. di Salerno | ||
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Cryptographic hardware and embedded systems-- CHES 2005 : 7th international workshop, Edinburgh, UK, August 29-September 1, 2005 : proceedings / / Josyula R. Rao, Berk Sunar (eds.) |
Edizione | [1st ed. 2005.] |
Pubbl/distr/stampa | Berlin ; ; New York, : Springer, c2005 |
Descrizione fisica | 1 online resource (XIV, 458 p.) |
Disciplina | 005.8/2 |
Altri autori (Persone) |
RaoJosyula Ramachandra <1962->
SunarBerk |
Collana | Lecture notes in computer science |
Soggetto topico |
Embedded computer systems
Cryptography Computer security |
Formato | Materiale a stampa ![]() |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Side Channels I -- Resistance of Randomized Projective Coordinates Against Power Analysis -- Templates as Master Keys -- A Stochastic Model for Differential Side Channel Cryptanalysis -- Arithmetic for Cryptanalysis -- A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis -- Further Hidden Markov Model Cryptanalysis -- Low Resources -- Energy-Efficient Software Implementation of Long Integer Modular Arithmetic -- Short Memory Scalar Multiplication on Koblitz Curves -- Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 ?P -- Special Purpose Hardware -- SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers -- Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization -- Design of Testable Random Bit Generators -- Hardware Attacks and Countermeasures I -- Successfully Attacking Masked AES Hardware Implementations -- Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints -- Masking at Gate Level in the Presence of Glitches -- Arithmetic for Cryptography -- Bipartite Modular Multiplication -- Fast Truncated Multiplication for Cryptographic Applications -- Using an RSA Accelerator for Modular Inversion -- Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings -- Side Channel II (EM) -- EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA -- Security Limits for Compromising Emanations -- Security Evaluation Against Electromagnetic Analysis at Design Time -- Side Channel III -- On Second-Order Differential Power Analysis -- Improved Higher-Order Side-Channel Attacks with FPGA Experiments -- Trusted Computing -- Secure Data Management in Trusted Computing -- Hardware Attacks and Countermeasures II -- Data Remanence in Flash Memory Devices -- Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment -- Hardware Attacks and Countermeasures III -- DPA Leakage Models for CMOS Logic Circuits -- The “Backend Duplication” Method -- Efficient Hardware I -- Hardware Acceleration of the Tate Pairing in Characteristic Three -- Efficient Hardware for the Tate Pairing Calculation in Characteristic Three -- Efficient Hardware II -- AES on FPGA from the Fastest to the Smallest -- A Very Compact S-Box for AES. |
Altri titoli varianti | CHES 2005 |
Record Nr. | UNINA-9910483219903321 |
Berlin ; ; New York, : Springer, c2005 | ||
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Lo trovi qui: Univ. Federico II | ||
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