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High performance embedded architectures and compilers : third international conference, HiPEAC 2008, Goteborg, Sweden, January 27-29, 2008 : proceedings / / Per Stenstrom ... [et al.] (eds.)
| High performance embedded architectures and compilers : third international conference, HiPEAC 2008, Goteborg, Sweden, January 27-29, 2008 : proceedings / / Per Stenstrom ... [et al.] (eds.) |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin ; ; New York, : Springer, 2008 |
| Descrizione fisica | 1 online resource (XIII, 420 p.) |
| Disciplina | 003.3 |
| Altri autori (Persone) | StenstromPer |
| Collana |
Lecture notes in computer science
LNCS sublibrary. SL 1, Theoretical computer science and general issues |
| Soggetto topico |
Embedded computer systems
Compilers (Computer programs) Computer architecture |
| ISBN | 3-540-92990-8 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote: Challenges on the Road to Exascale Computing -- Keynote: Compilers in the Manycore Era -- I Dynamic Translation and Optimisation -- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering -- Predictive Runtime Code Scheduling for Heterogeneous Architectures -- Collective Optimization -- High Speed CPU Simulation Using LTU Dynamic Binary Translation -- II Low Level Scheduling -- Integrated Modulo Scheduling for Clustered VLIW Architectures -- Software Pipelining in Nested Loops with Prolog-Epilog Merging -- A Flexible Code Compression Scheme Using Partitioned Look-Up Tables -- III Parallelism and Resource Control -- MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor -- IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor -- A Hardware Task Scheduler for Embedded Video Processing -- Finding Stress Patterns in Microprocessor Workloads -- IV Communication -- Deriving Efficient Data Movement from Decoupled Access/Execute Specifications -- MPSoC Design Using Application-Specific Architecturally Visible Communication -- Communication Based Proactive Link Power Management -- V Mapping for CMPs -- Mapping and Synchronizing Streaming Applications on Cell Processors -- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors -- Accomodating Diversity in CMPs with Heterogeneous Frequencies -- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip -- VI Power -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines -- HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic -- Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures -- VII Cache Issues -- Revisiting Cache Block Superloading -- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors -- In-Network Caching for Chip Multiprocessors -- VIII Parallel Embedded Applications -- Parallel LDPC Decoding on the Cell/B.E. Processor -- Parallel H.264 Decoding on an Embedded Multicore Processor. |
| Altri titoli varianti | HiPEAC 2008 |
| Record Nr. | UNINA-9910483766303321 |
| Berlin ; ; New York, : Springer, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Transactions on high-performance embedded architectures and compilers II / / Per Stenstrom (ed.)
| Transactions on high-performance embedded architectures and compilers II / / Per Stenstrom (ed.) |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin ; ; Heidelberg, : Springer-Verlag, c2009 |
| Descrizione fisica | 1 online resource (XIV, 327 p.) |
| Disciplina | 005.11 |
| Altri autori (Persone) | StenstromPer |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Embedded computer systems
Compilers (Computer programs) Computer architecture |
| ISBN | 3-642-00904-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Special Section on High-Performance Embedded Architectures and Compilers -- Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches -- Compiler-Assisted Memory Encryption for Embedded Processors -- Branch Predictor Warmup for Sampled Simulation through Branch History Matching -- Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems -- Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization -- Regular Papers -- Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors -- Fetch Gating Control through Speculative Instruction Window Weighting -- Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers -- Linux Kernel Compaction through Cold Code Swapping -- Complexity Effective Bypass Networks -- A Context-Parameterized Model for Static Analysis of Execution Times -- Reexecution and Selective Reuse in Checkpoint Processors -- Compiler Support for Code Size Reduction Using a Queue-Based Processor -- Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC -- Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories. |
| Record Nr. | UNINA-9910484887103321 |
| Berlin ; ; Heidelberg, : Springer-Verlag, c2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||