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Applied Reconfigurable Computing [[electronic resource] ] : 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings / / edited by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
| Applied Reconfigurable Computing [[electronic resource] ] : 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings / / edited by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz |
| Edizione | [1st ed. 2015.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 |
| Descrizione fisica | 1 online resource (XVIII, 557 p. 257 illus.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Computer engineering Computer networks Algorithms Artificial intelligence Application software Computer Hardware Computer Engineering and Networks Artificial Intelligence Computer and Information Systems Applications |
| ISBN | 3-319-16214-4 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Architecture and Modeling -- Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks -- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators -- Hierarchical Dynamic Power-Gating in FPGAs -- Tools and Compilers -- Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation -- ArchHDL: A Novel Hardware RTL Design Environment in C++ -- Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA -- Systems and Applications -- Preemptive Hardware Multitasking in ReconOS -- A Fully Parallel Particle Filter Architecture for FPGAs -- TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools -- Tools and Compilers -- Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures -- SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs -- Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties -- Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components -- Network-on-a-Chip Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays -- Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip -- Survey on Real-Time Network-on-Chip Architectures -- Cryptography Applications Efficient SR-Latch PUF -- Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study -- Dual CLEFIA/AES Cipher Core on FPGA -- Systems and Applications -- An Efficient and Flexible FPGA Implementation of a Face Detection System -- A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context -- A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank -- The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs -- Extended Abstracts (Posters) -- A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures -- Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA. -- A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware -- Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures -- Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects -- Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments -- DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems -- Acceleration of Data Streaming Classification Using Reconfigurable Technology -- On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach -- Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform -- A Challenge of Portable and High-Speed FPGA Accelerator -- Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array -- Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture -- Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization -- DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost -- A Flexible Multilayer Perceptron Co-processor for FPGAs -- Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs -- Towards Performance Modeling of 3D Memory Integrated FPGA Architectures -- Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL -- Special Session 1: Funded R&D Running and Completed Projects (Invited Papers) -- Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing -- SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms -- Hardware Task Scheduling for Partially Reconfigurable FPGAs -- SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring -- Special Session 2: Horizon 2020 Funded Projects (Invited Papers) -- DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications -- Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective -- Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach -- COSSIM : A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator. |
| Record Nr. | UNISA-996200347303316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Applied Reconfigurable Computing [[electronic resource] ] : 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings / / edited by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
| Applied Reconfigurable Computing [[electronic resource] ] : 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings / / edited by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz |
| Edizione | [1st ed. 2015.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 |
| Descrizione fisica | 1 online resource (XVIII, 557 p. 257 illus.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Computer engineering Computer networks Algorithms Artificial intelligence Application software Computer Hardware Computer Engineering and Networks Artificial Intelligence Computer and Information Systems Applications |
| ISBN | 3-319-16214-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Architecture and Modeling -- Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks -- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators -- Hierarchical Dynamic Power-Gating in FPGAs -- Tools and Compilers -- Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation -- ArchHDL: A Novel Hardware RTL Design Environment in C++ -- Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA -- Systems and Applications -- Preemptive Hardware Multitasking in ReconOS -- A Fully Parallel Particle Filter Architecture for FPGAs -- TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools -- Tools and Compilers -- Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures -- SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs -- Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties -- Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components -- Network-on-a-Chip Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays -- Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip -- Survey on Real-Time Network-on-Chip Architectures -- Cryptography Applications Efficient SR-Latch PUF -- Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study -- Dual CLEFIA/AES Cipher Core on FPGA -- Systems and Applications -- An Efficient and Flexible FPGA Implementation of a Face Detection System -- A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context -- A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank -- The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs -- Extended Abstracts (Posters) -- A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures -- Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA. -- A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware -- Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures -- Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects -- Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments -- DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems -- Acceleration of Data Streaming Classification Using Reconfigurable Technology -- On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach -- Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform -- A Challenge of Portable and High-Speed FPGA Accelerator -- Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array -- Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture -- Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization -- DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost -- A Flexible Multilayer Perceptron Co-processor for FPGAs -- Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs -- Towards Performance Modeling of 3D Memory Integrated FPGA Architectures -- Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL -- Special Session 1: Funded R&D Running and Completed Projects (Invited Papers) -- Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing -- SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms -- Hardware Task Scheduling for Partially Reconfigurable FPGAs -- SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring -- Special Session 2: Horizon 2020 Funded Projects (Invited Papers) -- DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications -- Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective -- Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach -- COSSIM : A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator. |
| Record Nr. | UNINA-9910485011303321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designing 2D and 3D network-on-chip architectures / / Konstantinos Tatas [and three others]
| Designing 2D and 3D network-on-chip architectures / / Konstantinos Tatas [and three others] |
| Autore | Tatas Konstantinos |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | New York : , : Springer, , 2014 |
| Descrizione fisica | 1 online resource (xiii, 265 pages) : illustrations (some color) |
| Disciplina | 621.392 |
| Collana | Gale eBooks |
| Soggetto topico | Networks on a chip - Design and construction |
| ISBN | 1-4614-4274-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Part I: Network-on-Chip Design Methodology -- Network-on-Chip Technology: A Paradigm Shift -- NoC Modeling and Topology Exploration -- Communication Architecture -- Power and Thermal Effects and Management -- NoC-based System Integration -- NoC Verification and Testing -- The Spidergon STNoC -- Middleware Memory Management in NoC -- On Designing 3-D Platforms -- The SYSMANTIC NoC Design and Prototyping Framework -- Part II: Suggested Projects.- Projects on Network-on Chip. |
| Record Nr. | UNINA-9910299760503321 |
Tatas Konstantinos
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| New York : , : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Dynamic Memory Management for Embedded Systems [[electronic resource] /] / by David Atienza Alonso, Stylianos Mamagkakis, Christophe Poucet, Miguel Peón-Quirós, Alexandros Bartzas, Francky Catthoor, Dimitrios Soudris
| Dynamic Memory Management for Embedded Systems [[electronic resource] /] / by David Atienza Alonso, Stylianos Mamagkakis, Christophe Poucet, Miguel Peón-Quirós, Alexandros Bartzas, Francky Catthoor, Dimitrios Soudris |
| Autore | Atienza Alonso David |
| Edizione | [1st ed. 2015.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 |
| Descrizione fisica | 1 online resource (251 p.) |
| Disciplina |
004.1
620 621.381 621.3815 |
| Soggetto topico |
Electronic circuits
Microprocessors Electronics Microelectronics Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
| ISBN | 3-319-10572-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Analysis and Characterization of Dynamic Multimedia Applications -- Profiling and Analysis of Dynamic Applications -- Dynamic Memory Management Optimization for Multimedia Applications -- Systematic Placement of Dynamic Objects across Heterogeneous Memory Hierarchies. |
| Record Nr. | UNINA-9910299843803321 |
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Atienza Alonso David
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Hardware Accelerators in Data Centers [[electronic resource] /] / edited by Christoforos Kachris, Babak Falsafi, Dimitrios Soudris
| Hardware Accelerators in Data Centers [[electronic resource] /] / edited by Christoforos Kachris, Babak Falsafi, Dimitrios Soudris |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (280 pages) : illustrations |
| Disciplina | 004.22 |
| Soggetto topico |
Electronic circuits
Microprocessors Signal processing Image processing Speech processing systems Circuits and Systems Processor Architectures Signal, Image and Speech Processing |
| ISBN | 3-319-92792-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Building the Infrastructure for Deploying FPGAs in the Cloud -- dReDBox: A Disaggregated Architectural Perspective for Data Centers -- The Green Computing Continuum: The OPERA Perspective -- SPynq: Acceleration of Machine Learning Applications over Spark on Pynq -- M2DC - A Novel Heterogeneous Hyperscale Microserver Platform -- Towards an Energy-aware Framework for Application Development and Execution in Heterogeneous Parallel Architectures -- Enabling Virtualized Programmable Logic Resources at the Edge and the Cloud -- Energy Efficient Servers and Cloud -- Towards Ubiquitous Low-power Image Processing Platforms -- Energy-efficient Heterogeneous COmputing at exaSCALE - ECOSCALE -- On Optimizing the Energy Consumption of Urban Data Centers. |
| Record Nr. | UNINA-9910337466403321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms [[electronic resource] ] : A Cross-layer Approach / / edited by William Fornaciari, Dimitrios Soudris
| Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms [[electronic resource] ] : A Cross-layer Approach / / edited by William Fornaciari, Dimitrios Soudris |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (320 pages) : illustrations |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Microprocessors Logic design Circuits and Systems Processor Architectures Logic Design |
| ISBN | 3-319-91962-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Multi-Many core Systems -- Reliability Issues -- HARPA Multi-layer METHODOLOGY: HARPA OS + HARPA RTE -- Reliability and mitigation strategies in HARPA: Modeling -- Reliability and mitigation strategies in HARPA: Mitigation -- Knobs/Monitors -- Event-based Thermal Control -- Power aware design of On-chip communication -- OS –Based Management -- Sensing application -- FLOREON application -- Landslide application -- Conclusions. |
| Record Nr. | UNINA-9910337652803321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000 Proceedings / / edited by Dimitrios Soudris, Peter Pirsch, Erich Barke
| Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000 Proceedings / / edited by Dimitrios Soudris, Peter Pirsch, Erich Barke |
| Edizione | [1st ed. 2000.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2000 |
| Descrizione fisica | 1 online resource (XII, 338 p.) |
| Disciplina | 621.395 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Microprocessors Arithmetic and logic units, Computer Logic design Computer system failures Computational complexity Computer System Implementation Processor Architectures Arithmetic and Logic Structures Logic Design System Performance and Evaluation Complexity |
| ISBN | 3-540-45373-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Opening -- Constraints, Hurdles and Opportunities for a Successful European Take-Up Action -- RTL Power Modeling -- Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques -- Power Models for Semi-autonomous RTL Macros -- Power Macro-Modelling for Firm-Macro -- RTL Estimation of Steering Logic Power -- Power Estimation and Optimization -- Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers -- Framework for High-Level Power Estimation of Signal Processing Architectures -- Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses -- Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions -- System-Level Design -- A Holistic Approach to System Level Energy Optimization -- Early Power Estimation for System-on-Chip Designs -- Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures -- Transistor-Level Modeling -- Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design -- Impact of Voltage Scaling on Glitch Power Consumption -- Degradation Delay Model Extension to CMOS Gates -- Second Generation Delay Model for Submicron CMOS Process -- Asynchronous Circuit Design -- Semi-modular Latch Chains for Asynchronous Circuit Design -- Asynchronous First-in First-out Queues -- Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance -- VLSI Implementation of a Low-Power High-Speed Self-Timed Adder -- Power Efficient Technologies -- Low Power Design Techniques for Contactless Chipcards -- Dynamic Memory Design for Low Data-Retention Power -- Double-Latch Clocking Scheme for Low-Power I.P. Cores -- Design of Multimedia Processing Applications -- Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip -- Cost-Efficient C-Level Design of an MPEG-4 Video Decoder -- Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications -- AdiabaticDesign and ArithmeticModules -- Design of Reversible Logic Circuits by Means of Control Gates -- Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates -- An Adiabatic Multiplier -- Logarithmic Number System for Low-Power Arithmetic -- Analog-Digital Circuits Modeling -- An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits -- PARCOURS — Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits -- Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits -- Computer Aided Generation of Analytic Models for Nonlinear Function Blocks. |
| Record Nr. | UNINA-9910143617903321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2000 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000 Proceedings / / edited by Dimitrios Soudris, Peter Pirsch, Erich Barke
| Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000 Proceedings / / edited by Dimitrios Soudris, Peter Pirsch, Erich Barke |
| Edizione | [1st ed. 2000.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2000 |
| Descrizione fisica | 1 online resource (XII, 338 p.) |
| Disciplina | 621.395 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Microprocessors Arithmetic and logic units, Computer Logic design Computer system failures Computational complexity Computer System Implementation Processor Architectures Arithmetic and Logic Structures Logic Design System Performance and Evaluation Complexity |
| ISBN | 3-540-45373-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Opening -- Constraints, Hurdles and Opportunities for a Successful European Take-Up Action -- RTL Power Modeling -- Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques -- Power Models for Semi-autonomous RTL Macros -- Power Macro-Modelling for Firm-Macro -- RTL Estimation of Steering Logic Power -- Power Estimation and Optimization -- Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers -- Framework for High-Level Power Estimation of Signal Processing Architectures -- Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses -- Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions -- System-Level Design -- A Holistic Approach to System Level Energy Optimization -- Early Power Estimation for System-on-Chip Designs -- Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures -- Transistor-Level Modeling -- Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design -- Impact of Voltage Scaling on Glitch Power Consumption -- Degradation Delay Model Extension to CMOS Gates -- Second Generation Delay Model for Submicron CMOS Process -- Asynchronous Circuit Design -- Semi-modular Latch Chains for Asynchronous Circuit Design -- Asynchronous First-in First-out Queues -- Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance -- VLSI Implementation of a Low-Power High-Speed Self-Timed Adder -- Power Efficient Technologies -- Low Power Design Techniques for Contactless Chipcards -- Dynamic Memory Design for Low Data-Retention Power -- Double-Latch Clocking Scheme for Low-Power I.P. Cores -- Design of Multimedia Processing Applications -- Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip -- Cost-Efficient C-Level Design of an MPEG-4 Video Decoder -- Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications -- AdiabaticDesign and ArithmeticModules -- Design of Reversible Logic Circuits by Means of Control Gates -- Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates -- An Adiabatic Multiplier -- Logarithmic Number System for Low-Power Arithmetic -- Analog-Digital Circuits Modeling -- An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits -- PARCOURS — Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits -- Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits -- Computer Aided Generation of Analytic Models for Nonlinear Function Blocks. |
| Record Nr. | UNISA-996466356703316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2000 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
IoT for Smart Grids [[electronic resource] ] : Design Challenges and Paradigms / / edited by Kostas Siozios, Dimitrios Anagnostos, Dimitrios Soudris, Elias Kosmatopoulos
| IoT for Smart Grids [[electronic resource] ] : Design Challenges and Paradigms / / edited by Kostas Siozios, Dimitrios Anagnostos, Dimitrios Soudris, Elias Kosmatopoulos |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (289 pages) |
| Disciplina | 621.31 |
| Collana | Power Systems |
| Soggetto topico |
Energy systems
Power electronics Application software Control engineering System theory Energy Systems Power Electronics, Electrical Machines and Networks Information Systems Applications (incl. Internet) Control and Systems Theory Systems Theory, Control |
| ISBN | 3-030-03640-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | IoT for Smart Grids - Design Challenges and Paradigms -- Part I: Fundamental Topics and Technologies for IoT Systems Targeting Smart-Grid Domain -- Mastering the challenges of changing energy systems: The Smart-Grid Concept -- Edge Computing for Smart Grid: An Overview on Architectures and Solutions -- Smart-Grid Modelling and Simulation -- Communication Protocols for the IoT-based Smart Grid -- Smart Grid Hardware Security -- Edge Computing and Efficient Resource Management forintegration of video devices in Smart Grid deployments -- Solar Energy Forecasting in the Era of IoT Enabled Smart Grids -- Data Analytic for Improving Operations and Maintenance in Smart-Grid Environment -- On Accelerating Data Analytics: An Introduction to the Approximate Computing Technique -- Part II: Case Studies about Computerized Monitor and Control of Energy Systems -- Towards plug&play smart thermostats for building’s heating/cooling control. . |
| Record Nr. | UNINA-9910337594003321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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SAMOS XV : International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation : proceedings : July 20-23, 2015, Samos, Greece / / editors, Dimitrios Soudris and Luigi Carro ; sponsored by Institute of Electrical and Electronics Engineers
| SAMOS XV : International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation : proceedings : July 20-23, 2015, Samos, Greece / / editors, Dimitrios Soudris and Luigi Carro ; sponsored by Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2014 |
| Descrizione fisica | 1 online resource (140 pages) |
| Disciplina | 004.22 |
| Soggetto topico |
Computer architecture
Embedded computer systems |
| ISBN | 1-4673-7311-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996280617903316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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