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Integrated formal analysis of timed-triggered ethernet [[electronic resource] /] / Bruno Dutertre, Natarajan Shankar, and Sam Owre
| Integrated formal analysis of timed-triggered ethernet [[electronic resource] /] / Bruno Dutertre, Natarajan Shankar, and Sam Owre |
| Autore | Dutertre Bruno |
| Pubbl/distr/stampa | Hampton, Va. : , : National Aeronautics and Space Administration, Langley Research Center, , [2012] |
| Descrizione fisica | 1 online resource (28 pages) : illustrations |
| Altri autori (Persone) |
ShankarN (Natarajan)
OwreSam |
| Collana | NASA/CR |
| Soggetto topico |
Ethernet
Protocol (computers) Topology Computer networks Time synchronization Formalism Mathematical models |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910702076503321 |
Dutertre Bruno
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| Hampton, Va. : , : National Aeronautics and Space Administration, Langley Research Center, , [2012] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Verified software, theories, tools, experiments : second international conference, VSTTE 2008, Toronto, Canada, October 6-8, 2008 : proceedings / / Natarajan Shankar, Jim Woodcock (editors)
| Verified software, theories, tools, experiments : second international conference, VSTTE 2008, Toronto, Canada, October 6-8, 2008 : proceedings / / Natarajan Shankar, Jim Woodcock (editors) |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | Berlin, Germany : , : Springer, , [2008] |
| Descrizione fisica | 1 online resource (XII, 263 p.) |
| Disciplina | 005.14 |
| Collana | Programming and Software Engineering |
| Soggetto topico | Computer programs - Verification |
| ISBN | 3-540-87873-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynote Talks (Abstracts) -- Readable Formal Proofs -- From Verification to Synthesis -- Verification, Least-Fixpoint Checking, Abstraction -- Combining Tests and Proofs -- Logics -- Propositional Dynamic Logic for Recursive Procedures -- Mapped Separation Logic -- Unguessable Atoms: A Logical Foundation for Security -- Combining Domain-Specific and Foundational Logics to Verify Complete Software Systems -- Tools -- JML4: Towards an Industrial Grade IVE for Java and Next Generation Research Platform for JML -- Incremental Benchmarks for Software Verification Tools and Techniques -- Case Studies -- Verified Protection Model of the seL4 Microkernel -- Verification of the Deutsch-Schorr-Waite Marking Algorithm with Modal Logic -- Bounded Verification of Voting Software -- Methodology -- Expression Decomposition in a Rely/Guarantee Context -- A Verification Approach for System-Level Concurrent Programs -- Boogie Meets Regions: A Verification Experience Report -- Flexible Immutability with Frozen Objects -- Verisoft -- The Verisoft Approach to Systems Verification -- Formal Functional Verification of Device Drivers -- Verified Process-Context Switch for C-Programmed Kernels -- Paper from VSTTE 2005 -- Where Is the Value in a Program Verifier?. |
| Record Nr. | UNISA-996465273103316 |
| Berlin, Germany : , : Springer, , [2008] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Verified software, theories, tools, experiments : second international conference, VSTTE 2008, Toronto, Canada, October 6-8, 2008 : proceedings / / Natarajan Shankar, Jim Woodcock (editors)
| Verified software, theories, tools, experiments : second international conference, VSTTE 2008, Toronto, Canada, October 6-8, 2008 : proceedings / / Natarajan Shankar, Jim Woodcock (editors) |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | Berlin, Germany : , : Springer, , [2008] |
| Descrizione fisica | 1 online resource (XII, 263 p.) |
| Disciplina | 005.14 |
| Collana | Programming and Software Engineering |
| Soggetto topico | Computer programs - Verification |
| ISBN | 3-540-87873-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynote Talks (Abstracts) -- Readable Formal Proofs -- From Verification to Synthesis -- Verification, Least-Fixpoint Checking, Abstraction -- Combining Tests and Proofs -- Logics -- Propositional Dynamic Logic for Recursive Procedures -- Mapped Separation Logic -- Unguessable Atoms: A Logical Foundation for Security -- Combining Domain-Specific and Foundational Logics to Verify Complete Software Systems -- Tools -- JML4: Towards an Industrial Grade IVE for Java and Next Generation Research Platform for JML -- Incremental Benchmarks for Software Verification Tools and Techniques -- Case Studies -- Verified Protection Model of the seL4 Microkernel -- Verification of the Deutsch-Schorr-Waite Marking Algorithm with Modal Logic -- Bounded Verification of Voting Software -- Methodology -- Expression Decomposition in a Rely/Guarantee Context -- A Verification Approach for System-Level Concurrent Programs -- Boogie Meets Regions: A Verification Experience Report -- Flexible Immutability with Frozen Objects -- Verisoft -- The Verisoft Approach to Systems Verification -- Formal Functional Verification of Device Drivers -- Verified Process-Context Switch for C-Programmed Kernels -- Paper from VSTTE 2005 -- Where Is the Value in a Program Verifier?. |
| Record Nr. | UNINA-9910483923703321 |
| Berlin, Germany : , : Springer, , [2008] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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