Integrated circuit and system design : power and timing modeling, optimization and simulation : 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012 : revised selected papers / / Jose L. Ayala, Delong Shang, Alex Yakovlev (eds.) |
Edizione | [1st ed. 2013.] |
Pubbl/distr/stampa | New York, : Springer, 2013 |
Descrizione fisica | 1 online resource (IX, 258 p. 150 illus.) |
Disciplina | 004.24 |
Altri autori (Persone) |
AyalaJose L
ShangDelong YakovlevAlex |
Collana |
Lecture notes in computer science
LNCS sublibrary |
Soggetto topico | Integrated circuits - Very large scale integration - Computer-aided design |
ISBN | 3-642-36157-9 |
Formato | Materiale a stampa ![]() |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Sleep-Transistor Based Power-Gating Tradeoff Analyses -- Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level -- Non-invasive Power Simulation at System-Level with SystemC -- A Standard Cell Optimization Method for Near-Threshold Voltage Operations -- An Extended Metastability Simulation Method for Synchronizer Characterization -- Phase Space Based NBTI Model -- Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths -- Noise Margin Based Library Optimization Considering Variability in Sub-threshold -- TCP Window Based DVFS for Low Power Network Controller SoC -- A Generic Architecture for Robust Asynchronous Communication Links -- Direct Statistical Simulation of Timing Properties in Sequential Circuits -- On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture -- Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications -- Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor -- Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation -- Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines -- Dynamic Power Management of a Computer with Self Power-Managed Components -- Case Studies of Logical Computation on Stochastic Bit Streams. |
Record Nr. | UNINA-9910484142403321 |
New York, : Springer, 2013 | ||
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Lo trovi qui: Univ. Federico II | ||
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers / / edited by José L. Ayala, Delong Shang, Alex Yakovlev |
Edizione | [1st ed. 2013.] |
Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 |
Descrizione fisica | 1 online resource (IX, 258 p. 150 illus.) |
Disciplina | 004.24 |
Collana | Theoretical Computer Science and General Issues |
Soggetto topico |
Electronic digital computers—Evaluation
Computer simulation Computer networks Computer hardware description languages Logic design Compilers (Computer programs) System Performance and Evaluation Computer Modelling Computer Communication Networks Register-Transfer-Level Implementation Logic Design Compilers and Interpreters |
ISBN | 3-642-36157-9 |
Formato | Materiale a stampa ![]() |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Sleep-Transistor Based Power-Gating Tradeoff Analyses -- Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level -- Non-invasive Power Simulation at System-Level with SystemC -- A Standard Cell Optimization Method for Near-Threshold Voltage Operations -- An Extended Metastability Simulation Method for Synchronizer Characterization -- Phase Space Based NBTI Model -- Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths -- Noise Margin Based Library Optimization Considering Variability in Sub-threshold -- TCP Window Based DVFS for Low Power Network Controller SoC -- A Generic Architecture for Robust Asynchronous Communication Links -- Direct Statistical Simulation of Timing Properties in Sequential Circuits -- On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture -- Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications -- Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor -- Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation -- Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines -- Dynamic Power Management of a Computer with Self Power-Managed Components -- Case Studies of Logical Computation on Stochastic Bit Streams. |
Record Nr. | UNISA-996465983903316 |
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 | ||
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Lo trovi qui: Univ. di Salerno | ||
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