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Junctionless Field-Effect Transistors : Design, Modeling, and Simulation / / Shubham Sahay, Mamidala Jagadesh Kumar
Junctionless Field-Effect Transistors : Design, Modeling, and Simulation / / Shubham Sahay, Mamidala Jagadesh Kumar
Autore Sahay Shubham
Pubbl/distr/stampa Hoboken, New Jersey : , : John Wiley & Sons Inc., , [2019]
Descrizione fisica 1 online resource
Disciplina 621.3815/284
Collana IEEE Press series on microelectronic systems
Soggetto topico Metal semiconductor field-effect transistors
ISBN 1-119-52352-4
1-119-52354-0
1-119-52351-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Preface xi -- 1 Introduction to Field-Effect Transistors 1 -- 1.1 Transistor Action 2 -- 1.2 Metal-Oxide-Semiconductor Field-Effect Transistors 4 -- 1.3 MOSFET Circuits: The Need for Complementary MOS 9 -- 1.4 The Need for CMOS Scaling 11 -- 1.5 Moore’s Law 13 -- 1.6 Koomey’s Law 13 -- 1.7 Challenges in Scaling the MOSFET 13 -- 1.8 Conclusion 23 -- References 23 -- 2 Emerging FET Architectures 27 -- 2.1 Tunnel FETs 28 -- 2.2 Impact Ionization MOSFET 34 -- 2.3 Bipolar I-MOS 39 -- 2.4 Negative Capacitance FETs 41 -- 2.5 Two-Dimensional FETs 46 -- 2.6 Nanowire FETs 49 -- 2.7 Nanotube FETs 51 -- 2.8 Conclusion 57 -- References 58 -- 3 Fundamentals of Junctionless Field-Effect Transistors 67 -- 3.1 Device Structure 69 -- 3.2 Operation 70 -- 3.3 Design Parameters 80 -- 3.4 Parameters that Affect the Performance 82 -- 3.5 Beyond Silicon JLFETS: Other Materials 100 -- 3.6 Challenges 103 -- 3.7 Conclusion 110 -- References 111 -- 4 Device Architectures to Mitigate Challenges in Junctionless Field-Effect Transistors 125 -- 4.1 Junctionless Accumulation-Mode Field-Effect Transistors 126 -- 4.2 Realizing Efficient Volume Depletion 129 -- 4.3 SOI JLFET with a High-𝜅 Box 131 -- 4.4 Bulk Planar JLFET 137 -- 4.5 JLFET with a Nonuniform Doping 140 -- 4.6 JLFET with a Step Doping Profile 144 -- 4.7 Multigate JLFET 149 -- 4.8 JLFET with a High-𝜅 Spacer 153 -- 4.9 JLFET with a Dual Material Gate 157 -- 4.10 Conclusion 162 -- References 162 -- 5 Gate-Induced Drain Leakage in Junctionless Field-Effect Transistors 173 -- 5.1 Hole Accumulation 174 -- 5.2 Parasitic BJT Action 176 -- 5.3 Impact of BTBT-Induced Parasitic BJT Action on Scaling 177 -- 5.4 Impact of Silicon Film Thickness on GIDL 179 -- 5.5 Impact of Doping on GIDL 187 -- 5.6 Impact of Spacer Design on GIDL 189 -- 5.7 Nature of GIDL in Different NWFET Configurations 190 -- 5.8 Device Architectures to Mitigate GIDL 199 -- 5.9 Conclusion 248 -- References 249 -- 6 Impact Ionization in Junctionless Field-Effect Transistors 255.
6.1 Impact Ionization 256 -- 6.2 Floating Body Effects in Silicon-on-Insulator MOSFETs 256 -- 6.3 Nature of Impact Ionization in JLFETs 260 -- 6.4 Zero Gate Oxide Thickness Coefficient 263 -- 6.5 Single Transistor Latch-Up in JLFETs 266 -- 6.6 Impact of Body Bias on Impact Ionization in JLFETs 267 -- 6.7 Subband Gap Impact Ionization in DGJLFETS with Asymmetric Operation 268 -- 6.8 Impact of Gate Misalignment on Impact Ionization in DGJLFETs 270 -- 6.9 Spacer Design Guideline from Impact Ionization Perspective 272 -- 6.10 Hysteresis and Snapback in JLFETs 273 -- 6.11 Impact of Heavy-Ion Irradiation on JLFETs 275 -- 6.12 Conclusions 276 -- References 276 -- 7 Junctionless Devices Without Any Chemical Doping 281 -- 7.1 Charge Plasma Doping 282 -- 7.2 Charge Plasma Based p-n Diode 283 -- 7.3 Junctionless I-MOS FET 288 -- 7.4 Junctionless Tunnel FETs 290 -- 7.5 JLTFET on a Highly Doped Silicon Film 294 -- 7.6 Bipolar Enhanced JLTFET 294 -- 7.7 Junctionless FETS Without Any Chemical Doping 297 -- 7.8 Challenges for CPJLFETs 302 -- 7.9 Electrostatic Doping Based FETs 312 -- 7.10 Conclusions 319 -- References 319 -- 8 Modeling Junctionless Field-Effect Transistors 327 -- 8.1 Introduction to FET Modeling 328 -- 8.2 Surface Potential Modeling of JLFETs 330 -- 8.3 Charge-Based Modeling Approach 351 -- 8.4 Drain Current Modeling Approach 355 -- 8.5 Modeling Short-Channel JLFETs 365 -- 8.6 Modeling Quantum Confinement 372 -- 8.7 Conclusion 379 -- References 379 -- 9 Simulation of JLFETS Using Sentaurus TCAD 385 -- 9.1 Introduction to TCAD 386 -- 9.2 Tool Flow 387 -- 9.3 Sample Input Deck for Long-Channel JLFETS 391 -- 9.4 Model Calibration 407 -- 9.5 Model Calibration for Short-Channel JLFETs 409 -- 9.6 Model Calibration for NWFETS 422 -- References 436 -- 10 Conclusion and Perspectives 439 -- 10.1 JLFETS As a Label-Free Biosensor 441 -- 10.2 JLFETS As Capacitorless DRAM 443 -- 10.3 Nanowire Junctionless NAND Flash Memory 444 -- 10.4 Junctionless Polysilicon TFTS with a Hybrid Channel 447.
10.5 JLFETS for 3D Integrated Circuits 449 -- 10.6 Summary 450 -- References 451 -- Index 457.
Record Nr. UNINA-9910554835903321
Sahay Shubham  
Hoboken, New Jersey : , : John Wiley & Sons Inc., , [2019]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Junctionless Field-Effect Transistors : Design, Modeling, and Simulation / / Shubham Sahay, Mamidala Jagadesh Kumar
Junctionless Field-Effect Transistors : Design, Modeling, and Simulation / / Shubham Sahay, Mamidala Jagadesh Kumar
Autore Sahay Shubham
Pubbl/distr/stampa Hoboken, New Jersey : , : John Wiley & Sons Inc., , [2019]
Descrizione fisica 1 online resource
Disciplina 621.3815/284
Collana IEEE Press series on microelectronic systems
Soggetto topico Metal semiconductor field-effect transistors
ISBN 1-119-52352-4
1-119-52354-0
1-119-52351-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Preface xi -- 1 Introduction to Field-Effect Transistors 1 -- 1.1 Transistor Action 2 -- 1.2 Metal-Oxide-Semiconductor Field-Effect Transistors 4 -- 1.3 MOSFET Circuits: The Need for Complementary MOS 9 -- 1.4 The Need for CMOS Scaling 11 -- 1.5 Moore’s Law 13 -- 1.6 Koomey’s Law 13 -- 1.7 Challenges in Scaling the MOSFET 13 -- 1.8 Conclusion 23 -- References 23 -- 2 Emerging FET Architectures 27 -- 2.1 Tunnel FETs 28 -- 2.2 Impact Ionization MOSFET 34 -- 2.3 Bipolar I-MOS 39 -- 2.4 Negative Capacitance FETs 41 -- 2.5 Two-Dimensional FETs 46 -- 2.6 Nanowire FETs 49 -- 2.7 Nanotube FETs 51 -- 2.8 Conclusion 57 -- References 58 -- 3 Fundamentals of Junctionless Field-Effect Transistors 67 -- 3.1 Device Structure 69 -- 3.2 Operation 70 -- 3.3 Design Parameters 80 -- 3.4 Parameters that Affect the Performance 82 -- 3.5 Beyond Silicon JLFETS: Other Materials 100 -- 3.6 Challenges 103 -- 3.7 Conclusion 110 -- References 111 -- 4 Device Architectures to Mitigate Challenges in Junctionless Field-Effect Transistors 125 -- 4.1 Junctionless Accumulation-Mode Field-Effect Transistors 126 -- 4.2 Realizing Efficient Volume Depletion 129 -- 4.3 SOI JLFET with a High-𝜅 Box 131 -- 4.4 Bulk Planar JLFET 137 -- 4.5 JLFET with a Nonuniform Doping 140 -- 4.6 JLFET with a Step Doping Profile 144 -- 4.7 Multigate JLFET 149 -- 4.8 JLFET with a High-𝜅 Spacer 153 -- 4.9 JLFET with a Dual Material Gate 157 -- 4.10 Conclusion 162 -- References 162 -- 5 Gate-Induced Drain Leakage in Junctionless Field-Effect Transistors 173 -- 5.1 Hole Accumulation 174 -- 5.2 Parasitic BJT Action 176 -- 5.3 Impact of BTBT-Induced Parasitic BJT Action on Scaling 177 -- 5.4 Impact of Silicon Film Thickness on GIDL 179 -- 5.5 Impact of Doping on GIDL 187 -- 5.6 Impact of Spacer Design on GIDL 189 -- 5.7 Nature of GIDL in Different NWFET Configurations 190 -- 5.8 Device Architectures to Mitigate GIDL 199 -- 5.9 Conclusion 248 -- References 249 -- 6 Impact Ionization in Junctionless Field-Effect Transistors 255.
6.1 Impact Ionization 256 -- 6.2 Floating Body Effects in Silicon-on-Insulator MOSFETs 256 -- 6.3 Nature of Impact Ionization in JLFETs 260 -- 6.4 Zero Gate Oxide Thickness Coefficient 263 -- 6.5 Single Transistor Latch-Up in JLFETs 266 -- 6.6 Impact of Body Bias on Impact Ionization in JLFETs 267 -- 6.7 Subband Gap Impact Ionization in DGJLFETS with Asymmetric Operation 268 -- 6.8 Impact of Gate Misalignment on Impact Ionization in DGJLFETs 270 -- 6.9 Spacer Design Guideline from Impact Ionization Perspective 272 -- 6.10 Hysteresis and Snapback in JLFETs 273 -- 6.11 Impact of Heavy-Ion Irradiation on JLFETs 275 -- 6.12 Conclusions 276 -- References 276 -- 7 Junctionless Devices Without Any Chemical Doping 281 -- 7.1 Charge Plasma Doping 282 -- 7.2 Charge Plasma Based p-n Diode 283 -- 7.3 Junctionless I-MOS FET 288 -- 7.4 Junctionless Tunnel FETs 290 -- 7.5 JLTFET on a Highly Doped Silicon Film 294 -- 7.6 Bipolar Enhanced JLTFET 294 -- 7.7 Junctionless FETS Without Any Chemical Doping 297 -- 7.8 Challenges for CPJLFETs 302 -- 7.9 Electrostatic Doping Based FETs 312 -- 7.10 Conclusions 319 -- References 319 -- 8 Modeling Junctionless Field-Effect Transistors 327 -- 8.1 Introduction to FET Modeling 328 -- 8.2 Surface Potential Modeling of JLFETs 330 -- 8.3 Charge-Based Modeling Approach 351 -- 8.4 Drain Current Modeling Approach 355 -- 8.5 Modeling Short-Channel JLFETs 365 -- 8.6 Modeling Quantum Confinement 372 -- 8.7 Conclusion 379 -- References 379 -- 9 Simulation of JLFETS Using Sentaurus TCAD 385 -- 9.1 Introduction to TCAD 386 -- 9.2 Tool Flow 387 -- 9.3 Sample Input Deck for Long-Channel JLFETS 391 -- 9.4 Model Calibration 407 -- 9.5 Model Calibration for Short-Channel JLFETs 409 -- 9.6 Model Calibration for NWFETS 422 -- References 436 -- 10 Conclusion and Perspectives 439 -- 10.1 JLFETS As a Label-Free Biosensor 441 -- 10.2 JLFETS As Capacitorless DRAM 443 -- 10.3 Nanowire Junctionless NAND Flash Memory 444 -- 10.4 Junctionless Polysilicon TFTS with a Hybrid Channel 447.
10.5 JLFETS for 3D Integrated Circuits 449 -- 10.6 Summary 450 -- References 451 -- Index 457.
Record Nr. UNINA-9910830003503321
Sahay Shubham  
Hoboken, New Jersey : , : John Wiley & Sons Inc., , [2019]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui