2000 International Workshops on Parallel Processing : proceedings : 21-24 August, 2000, Toronto, Canada |
Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2000 |
Disciplina | 004/.35 |
Soggetto topico |
Parallel processing (Electronic computers)
Engineering & Applied Sciences Computer Science |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Record Nr. | UNISA-996218933603316 |
[Place of publication not identified], : IEEE Computer Society, 2000 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. di Salerno | ||
|
2000 International Workshops on Parallel Processing : proceedings : 21-24 August, 2000, Toronto, Canada |
Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2000 |
Disciplina | 004/.35 |
Soggetto topico |
Parallel processing (Electronic computers)
Engineering & Applied Sciences Computer Science |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Record Nr. | UNINA-9910872791803321 |
[Place of publication not identified], : IEEE Computer Society, 2000 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
High Performance Computing - HiPC 2008 : 15th International Conference, Bangalore, India, December 17-20, 2008, Proceedings / / edited by P. Sadayappan, Manish Parashar, Ramamurthy Badrinath, Viktor K. Prasanna |
Edizione | [1st ed. 2008.] |
Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 |
Descrizione fisica | 1 online resource (XXV, 596 p.) |
Disciplina | 004.11 |
Collana | Theoretical Computer Science and General Issues |
Soggetto topico |
Software engineering
Computer science Computer engineering Computer networks Computers Software Engineering Theory of Computation Computer Engineering and Networks Hardware Performance and Reliability |
ISBN | 3-540-89894-8 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Keynote Addresses -- Extreme Computing on the Distributed European Infrastructure for Supercomputing Applications - DEISA -- Towards Networked Computers: What Can Be Learned from Distributed Computing? -- Computational Environments for Coupling Multiphase Flow, Transport, and Mechanics in Porous Media -- The Excitement in Parallel Computing -- Session I: Performance Optimization -- Improving Performance of Digest Caches in Network Processors -- Optimization of BLAS on the Cell Processor -- Fine Tuning Matrix Multiplications on Multicore -- The Design and Architecture of MAQAOAdvisor: A Live Tuning Guide -- A Load Balancing Framework for Clustered Storage Systems -- Construction and Evaluation of Coordinated Performance Skeletons -- Session II: Parallel Algorithms and Applications -- Data Sharing Analysis of Emerging Parallel Media Mining Workloads -- Efficient PDM Sorting Algorithms -- Accelerating Cone Beam Reconstruction Using the CUDA-Enabled GPU -- Improving the Performance of Tensor Matrix Vector Multiplication in Cumulative Reaction Probability Based Quantum Chemistry Codes -- Experimental Evaluation of Molecular Dynamics Simulations on Multi-core Systems -- Parsing XML Using Parallel Traversal of Streaming Trees -- Session III: Scheduling and Resource Management -- Performance Analysis of Multiple Site Resource Provisioning: Effects of the Precision of Availability Information -- An Open Computing Resource Management Framework for Real-Time Computing -- A Load Aware Channel Assignment and Link Scheduling Algorithm for Multi-channel Multi-radio Wireless Mesh Networks -- Multi-round Real-Time Divisible Load Scheduling for Clusters -- Energy-Efficient Dynamic Scheduling on Parallel Machines -- A Service-Oriented Priority-Based Resource Scheduling Scheme for Virtualized Utility Computing -- Session IV: Sensor Networks -- Scalable Processing of Spatial Alarms -- Coverage Based Expanding Ring Search for Dense Wireless Sensor Networks -- An Energy-Balanced Task Scheduling Heuristic for Heterogeneous Wireless Sensor Networks -- Energy Efficient Distributed Algorithms for Sensor Target Coverage Based on Properties of an Optimal Schedule -- In-Network Data Estimation for Sensor-Driven Scientific Applications -- Localization in Ad Hoc and Sensor Wireless Networks with Bounded Errors -- Session V: Energy-Aware Computing -- Optimization of Fast Fourier Transforms on the Blue Gene/L Supercomputer -- ScELA: Scalable and Extensible Launching Architecture for Clusters -- Parallel Information Theory Based Construction of Gene Regulatory Networks -- Communication Analysis of Parallel 3D FFT for Flat Cartesian Meshes on Large Blue Gene Systems -- Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware -- Session VI: Distributed Algorithms -- TrustCode: P2P Reputation-Based Trust Management Using Network Coding -- Design, Analysis, and Performance Evaluation of an Efficient Resource Unaware Scheduling Strategy for Processing Divisible Loads on Distributed Linear Daisy Chain Networks -- A Novel Learning Based Solution for Efficient Data Transport in Heterogeneous Wireless Networks -- Scalable Data Collection in Sensor Networks -- Task Scheduling on Heterogeneous Devices in Parallel Pervasive Systems (P 2 S) -- A Performance Guaranteed Distributed Multicast Algorithm for Long-Lived Directional Communications in WANETs -- Session VII: Communication Networks -- Maintaining Quality of Service with Dynamic Fault Tolerance in Fat-Trees -- Designing a High-Performance Clustered NAS: A Case Study with pNFS over RDMA on InfiniBand -- Sockets Direct Protocol for Hybrid Network Stacks: A Case Study with iWARP over 10G Ethernet -- Making a Case for Proactive Flow Control in Optical Circuit-Switched Networks -- FBICM: Efficient Congestion Management for High-Performance Networks Using Distributed Deterministic Routing -- Achieving 10Gbps Network Processing: Are We There Yet? -- Session VIII: Architecture -- SAIL: Self-Adaptive File Reallocation on Hybrid Disk Arrays -- Directory-Based Conflict Detection in Hardware Transactional Memory -- Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs -- SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories -- An Utilization Driven Framework for Energy Efficient Caches. |
Altri titoli varianti | HiPC'08 |
Record Nr. | UNISA-996466363503316 |
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. di Salerno | ||
|
High Performance Computing - HiPC 2008 : 15th International Conference, Bangalore, India, December 17-20, 2008, Proceedings / / edited by P. Sadayappan, Manish Parashar, Ramamurthy Badrinath, Viktor K. Prasanna |
Edizione | [1st ed. 2008.] |
Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 |
Descrizione fisica | 1 online resource (XXV, 596 p.) |
Disciplina | 004.11 |
Collana | Theoretical Computer Science and General Issues |
Soggetto topico |
Software engineering
Computer science Computer engineering Computer networks Computers Software Engineering Theory of Computation Computer Engineering and Networks Hardware Performance and Reliability |
ISBN | 3-540-89894-8 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Keynote Addresses -- Extreme Computing on the Distributed European Infrastructure for Supercomputing Applications - DEISA -- Towards Networked Computers: What Can Be Learned from Distributed Computing? -- Computational Environments for Coupling Multiphase Flow, Transport, and Mechanics in Porous Media -- The Excitement in Parallel Computing -- Session I: Performance Optimization -- Improving Performance of Digest Caches in Network Processors -- Optimization of BLAS on the Cell Processor -- Fine Tuning Matrix Multiplications on Multicore -- The Design and Architecture of MAQAOAdvisor: A Live Tuning Guide -- A Load Balancing Framework for Clustered Storage Systems -- Construction and Evaluation of Coordinated Performance Skeletons -- Session II: Parallel Algorithms and Applications -- Data Sharing Analysis of Emerging Parallel Media Mining Workloads -- Efficient PDM Sorting Algorithms -- Accelerating Cone Beam Reconstruction Using the CUDA-Enabled GPU -- Improving the Performance of Tensor Matrix Vector Multiplication in Cumulative Reaction Probability Based Quantum Chemistry Codes -- Experimental Evaluation of Molecular Dynamics Simulations on Multi-core Systems -- Parsing XML Using Parallel Traversal of Streaming Trees -- Session III: Scheduling and Resource Management -- Performance Analysis of Multiple Site Resource Provisioning: Effects of the Precision of Availability Information -- An Open Computing Resource Management Framework for Real-Time Computing -- A Load Aware Channel Assignment and Link Scheduling Algorithm for Multi-channel Multi-radio Wireless Mesh Networks -- Multi-round Real-Time Divisible Load Scheduling for Clusters -- Energy-Efficient Dynamic Scheduling on Parallel Machines -- A Service-Oriented Priority-Based Resource Scheduling Scheme for Virtualized Utility Computing -- Session IV: Sensor Networks -- Scalable Processing of Spatial Alarms -- Coverage Based Expanding Ring Search for Dense Wireless Sensor Networks -- An Energy-Balanced Task Scheduling Heuristic for Heterogeneous Wireless Sensor Networks -- Energy Efficient Distributed Algorithms for Sensor Target Coverage Based on Properties of an Optimal Schedule -- In-Network Data Estimation for Sensor-Driven Scientific Applications -- Localization in Ad Hoc and Sensor Wireless Networks with Bounded Errors -- Session V: Energy-Aware Computing -- Optimization of Fast Fourier Transforms on the Blue Gene/L Supercomputer -- ScELA: Scalable and Extensible Launching Architecture for Clusters -- Parallel Information Theory Based Construction of Gene Regulatory Networks -- Communication Analysis of Parallel 3D FFT for Flat Cartesian Meshes on Large Blue Gene Systems -- Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware -- Session VI: Distributed Algorithms -- TrustCode: P2P Reputation-Based Trust Management Using Network Coding -- Design, Analysis, and Performance Evaluation of an Efficient Resource Unaware Scheduling Strategy for Processing Divisible Loads on Distributed Linear Daisy Chain Networks -- A Novel Learning Based Solution for Efficient Data Transport in Heterogeneous Wireless Networks -- Scalable Data Collection in Sensor Networks -- Task Scheduling on Heterogeneous Devices in Parallel Pervasive Systems (P 2 S) -- A Performance Guaranteed Distributed Multicast Algorithm for Long-Lived Directional Communications in WANETs -- Session VII: Communication Networks -- Maintaining Quality of Service with Dynamic Fault Tolerance in Fat-Trees -- Designing a High-Performance Clustered NAS: A Case Study with pNFS over RDMA on InfiniBand -- Sockets Direct Protocol for Hybrid Network Stacks: A Case Study with iWARP over 10G Ethernet -- Making a Case for Proactive Flow Control in Optical Circuit-Switched Networks -- FBICM: Efficient Congestion Management for High-Performance Networks Using Distributed Deterministic Routing -- Achieving 10Gbps Network Processing: Are We There Yet? -- Session VIII: Architecture -- SAIL: Self-Adaptive File Reallocation on Hybrid Disk Arrays -- Directory-Based Conflict Detection in Hardware Transactional Memory -- Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs -- SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories -- An Utilization Driven Framework for Energy Efficient Caches. |
Altri titoli varianti | HiPC'08 |
Record Nr. | UNINA-9910483062903321 |
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Languages and Compilers for Parallel Computing [[electronic resource] ] : 10th International Workshop, LCPC'97, Minneapolis, Minnesota, USA, August 7-9, 1997. Proceedings / / edited by Zhiyuan Li, Pen-Chung Yew, Siddharta Chatterjee, Chua-Huang Huang, P. Sadayappan, David Sehr |
Edizione | [1st ed. 1998.] |
Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 |
Descrizione fisica | 1 online resource (XII, 440 p.) |
Disciplina | 005.13 |
Collana | Lecture Notes in Computer Science |
Soggetto topico |
Programming languages (Electronic computers)
Architecture, Computer Computer programming Computers Arithmetic and logic units, Computer Programming Languages, Compilers, Interpreters Computer System Implementation Programming Techniques Computation by Abstract Devices Arithmetic and Logic Structures |
ISBN | 3-540-69788-8 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Quantifying the multi-level nature of tiling interactions -- Reuse-driven tiling for data locality -- Table-lookup approach for compiling two-level data-processor mappings in HPF -- Code generation for complex subscripts in data-parallel programs -- Automatic data decomposition for message-passing machines -- Program analysis of overlap area usage in self-similar parallel programs -- Analysis and optimization of explicity parallel programs using the parallel program graph representation -- Concurrent static single assignment form and constant propagation for explicitly parallel programs -- Identifying DEF/USE information of statements that construct and traverse dynamic recursive data structures -- Program optimization for concurrent multithreaded architectures -- Interactive compilation and performance analysis with URSA MINOR -- The SPNT test: A new technology for run-time speculative parallelization of loops -- Lowering HPF procedure interface to a canonical representation -- PCRC-based HPF compilation -- Data parallel language extensions for exploiting locality in irregular problems -- Simplifying control flow in compiler-generated parallel code -- Reducing synchronization overhead for compiler-parallelized codes on software DSMs (extended abstract) -- An array data flow analysis based communication optimizer -- A compiler abstraction for machine independent parallel communication generation -- The aggregate function API: It's not just for PAPERS anymore -- Definition of the F?? extension to fortran 90 -- Exploiting parallelism through directives on the nano-threads programming model -- “Optimal” parallelism through integration of data and control parallelism: A case study in complete parallelization -- Java as a language for scientific parallel programming -- Experiences with loop parallelization in javar (A prototype restructuring compiler for java) -- NAMD: A case study in multilingual parallel programming -- A unified software pipeline construction scheme for modulo scheduled loops -- A systematic approach to branch speculation -- Integrating automatic data alignment and array operation synthesis to optimize data parallel programs -- A compiler for the ibm scalable shared memory project machine — extended abstract -- Automatic data layout with read-only replication and memory constraints -- Static analysis of recursive data structures. |
Record Nr. | UNISA-996466078803316 |
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. di Salerno | ||
|
Languages and Compilers for Parallel Computing [[electronic resource] ] : 10th International Workshop, LCPC'97, Minneapolis, Minnesota, USA, August 7-9, 1997. Proceedings / / edited by Zhiyuan Li, Pen-Chung Yew, Siddharta Chatterjee, Chua-Huang Huang, P. Sadayappan, David Sehr |
Edizione | [1st ed. 1998.] |
Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 |
Descrizione fisica | 1 online resource (XII, 440 p.) |
Disciplina | 005.13 |
Collana | Lecture Notes in Computer Science |
Soggetto topico |
Programming languages (Electronic computers)
Computer architecture Computer programming Computers Computer arithmetic and logic units Programming Languages, Compilers, Interpreters Computer System Implementation Programming Techniques Computation by Abstract Devices Arithmetic and Logic Structures |
ISBN | 3-540-69788-8 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Quantifying the multi-level nature of tiling interactions -- Reuse-driven tiling for data locality -- Table-lookup approach for compiling two-level data-processor mappings in HPF -- Code generation for complex subscripts in data-parallel programs -- Automatic data decomposition for message-passing machines -- Program analysis of overlap area usage in self-similar parallel programs -- Analysis and optimization of explicity parallel programs using the parallel program graph representation -- Concurrent static single assignment form and constant propagation for explicitly parallel programs -- Identifying DEF/USE information of statements that construct and traverse dynamic recursive data structures -- Program optimization for concurrent multithreaded architectures -- Interactive compilation and performance analysis with URSA MINOR -- The SPNT test: A new technology for run-time speculative parallelization of loops -- Lowering HPF procedure interface to a canonical representation -- PCRC-based HPF compilation -- Data parallel language extensions for exploiting locality in irregular problems -- Simplifying control flow in compiler-generated parallel code -- Reducing synchronization overhead for compiler-parallelized codes on software DSMs (extended abstract) -- An array data flow analysis based communication optimizer -- A compiler abstraction for machine independent parallel communication generation -- The aggregate function API: It's not just for PAPERS anymore -- Definition of the F?? extension to fortran 90 -- Exploiting parallelism through directives on the nano-threads programming model -- “Optimal” parallelism through integration of data and control parallelism: A case study in complete parallelization -- Java as a language for scientific parallel programming -- Experiences with loop parallelization in javar (A prototype restructuring compiler for java) -- NAMD: A case study in multilingual parallel programming -- A unified software pipeline construction scheme for modulo scheduled loops -- A systematic approach to branch speculation -- Integrating automatic data alignment and array operation synthesis to optimize data parallel programs -- A compiler for the ibm scalable shared memory project machine — extended abstract -- Automatic data layout with read-only replication and memory constraints -- Static analysis of recursive data structures. |
Record Nr. | UNINA-9910767524403321 |
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1998 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|