Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
Circuit Design for Reliability [[electronic resource] /] / edited by Ricardo Reis, Yu Cao, Gilson Wirth
| Circuit Design for Reliability [[electronic resource] /] / edited by Ricardo Reis, Yu Cao, Gilson Wirth |
| Edizione | [1st ed. 2015.] |
| Pubbl/distr/stampa | New York, NY : , : Springer New York : , : Imprint : Springer, , 2015 |
| Descrizione fisica | 1 online resource (271 p.) |
| Disciplina |
620
620.00420285 621.3815 658.56 |
| Soggetto topico |
Electronic circuits
Quality control Reliability Industrial safety Computer-aided engineering Circuits and Systems Quality Control, Reliability, Safety and Risk Computer-Aided Engineering (CAD, CAE) and Design |
| ISBN | 1-4614-4078-5 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Recent Trends in Bias Temperature Instability -- Charge trapping phenomena in MOSFETS: From Noise to Bias Temperature Instability -- Atomistic Simulations on Reliability -- On-chip characterization of statistical device degradation -- Circuit Resilience Roadmap -- Layout Aware Electromigration Analysis of Power/Ground Networks -- Power-Gating for Leakage Control and Beyond -- Soft Error Rate and Fault Tolerance Techniques for FPGAs. |
| Record Nr. | UNINA-9910299666303321 |
| New York, NY : , : Springer New York : , : Imprint : Springer, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electromigration Inside Logic Cells [[electronic resource] ] : Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS / / by Gracieli Posser, Sachin S. Sapatnekar, Ricardo Reis
| Electromigration Inside Logic Cells [[electronic resource] ] : Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS / / by Gracieli Posser, Sachin S. Sapatnekar, Ricardo Reis |
| Autore | Posser Gracieli |
| Edizione | [1st ed. 2017.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017 |
| Descrizione fisica | 1 online resource (XX, 118 p. 72 illus., 69 illus. in color.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Microprocessors Circuits and Systems Electronic Circuits and Devices Processor Architectures |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Introduction -- Chapter 2. State of the Art -- Chapter 3. Modeling Cell-internal EM -- Chapter 4. Current Calculation -- Chapter 5. Experimental Setup -- Chapter 6.Results -- Chapter 7. Analyzing the Electromigration Effects on Different Metal Layers -- Chapter 8. Conclusions. |
| Record Nr. | UNINA-9910155299203321 |
Posser Gracieli
|
||
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Soft error reliability using virtual platforms : early evaluation of multicore systems / / Felipe Rocha da Rosa, Luciano Ost and Ricardo Reis
| Soft error reliability using virtual platforms : early evaluation of multicore systems / / Felipe Rocha da Rosa, Luciano Ost and Ricardo Reis |
| Autore | Rocha da Rosa Felipe |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2020] |
| Descrizione fisica | 1 online resource (XI, 136 p. 53 illus., 51 illus. in color.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Processor Architectures
Electronics and Microelectronics, Instrumentation Circuits and Systems |
| ISBN | 3-030-55704-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1 . Introduction -- Chapter 2. Background on Soft Errors -- Chapter 3. Fault Injection Framework Using Virtual Platforms -- Chapter 4. Performance and Accuracy Assessment of Fault Injection Frameworks Based on VPs -- Chapter 5. Extensive Soft Error Evaluation -- Chapter 6. Machine Learning Applied to Soft Error Assessment in Multicoresystems. |
| Record Nr. | UNINA-9910427674703321 |
|
Rocha da Rosa Felipe
|
||
| Cham, Switzerland : , : Springer, , [2020] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Soft error reliability using virtual platforms : early evaluation of multicore systems / / Felipe Rocha da Rosa, Luciano Ost and Ricardo Reis
| Soft error reliability using virtual platforms : early evaluation of multicore systems / / Felipe Rocha da Rosa, Luciano Ost and Ricardo Reis |
| Autore | Rocha da Rosa Felipe |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2020] |
| Descrizione fisica | 1 online resource (XI, 136 p. 53 illus., 51 illus. in color.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Processor Architectures
Electronics and Microelectronics, Instrumentation Circuits and Systems |
| ISBN | 3-030-55704-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1 . Introduction -- Chapter 2. Background on Soft Errors -- Chapter 3. Fault Injection Framework Using Virtual Platforms -- Chapter 4. Performance and Accuracy Assessment of Fault Injection Frameworks Based on VPs -- Chapter 5. Extensive Soft Error Evaluation -- Chapter 6. Machine Learning Applied to Soft Error Assessment in Multicoresystems. |
| Record Nr. | UNISA-996465458703316 |
|
Rocha da Rosa Felipe
|
||
| Cham, Switzerland : , : Springer, , [2020] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
VLSI-SoC: At the Crossroads of Emerging Trends [[electronic resource] ] : 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised Selected Papers / / edited by Alex Orailoglu, H. Fatih Ugurdag, Luís Miguel Silveira, Martin Margala, Ricardo Reis
| VLSI-SoC: At the Crossroads of Emerging Trends [[electronic resource] ] : 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised Selected Papers / / edited by Alex Orailoglu, H. Fatih Ugurdag, Luís Miguel Silveira, Martin Margala, Ricardo Reis |
| Edizione | [1st ed. 2015.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 |
| Descrizione fisica | 1 online resource (XIV, 267 p. 177 illus.) |
| Disciplina | 621.395 |
| Collana | IFIP Advances in Information and Communication Technology |
| Soggetto topico |
Computer organization
Computer hardware Computer-aided engineering Computer Systems Organization and Communication Networks Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design |
| ISBN | 3-319-23799-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910299195503321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms [[electronic resource] ] : 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8–10, 2018, Revised and Extended Selected Papers / / edited by Nicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd Austin, Ricardo Reis
| VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms [[electronic resource] ] : 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8–10, 2018, Revised and Extended Selected Papers / / edited by Nicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd Austin, Ricardo Reis |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIV, 281 p. 138 illus., 64 illus. in color.) |
| Disciplina | 621.395 |
| Collana | IFIP Advances in Information and Communication Technology |
| Soggetto topico |
Computer organization
Operating systems (Computers) Logic design Input-output equipment (Computers) Artificial intelligence Computer Systems Organization and Communication Networks Operating Systems Logic Design Input/Output and Data Communications Artificial Intelligence |
| ISBN | 3-030-23425-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910337562903321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
VLSI-SoC: Design for Reliability, Security, and Low Power [[electronic resource] ] : 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers / / edited by Youngsoo Shin, Chi Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis
| VLSI-SoC: Design for Reliability, Security, and Low Power [[electronic resource] ] : 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers / / edited by Youngsoo Shin, Chi Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis |
| Edizione | [1st ed. 2016.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 |
| Descrizione fisica | 1 online resource (XIII, 223 p. 121 illus.) |
| Disciplina | 621.395 |
| Collana | IFIP Advances in Information and Communication Technology |
| Soggetto topico |
Computer organization
Computer hardware Computer-aided engineering Electronic circuits Computer Systems Organization and Communication Networks Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Circuits and Systems |
| ISBN | 3-319-46097-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Organization -- Contents -- On the Use of System-on-Chip Technology in Next-Generation Instruments Avionics for Space Exploration -- 1 Introduction -- 2 System-on-Chip Technology and Its Use in Space Exploration Avionics -- 3 The APEX-SoC Platform and Infrastructure -- 3.1 ARM-Centric Processing System -- 3.2 Data-Flow Infrastructure -- 3.3 Fault-Tolerance Features -- 3.4 Reliability Mode -- 4 Case-Study: APEX-SoC-Based Controller of the JPL CIRIS Spectrometer -- 4.1 The JPL CIRIS Spectrometer -- 4.2 CIRIS Data Processing -- 4.3 CIRIS Data Processing Integration into the APEX-SoC Infrastructure -- 5 Results -- 5.1 Implementation -- 5.2 Performance -- 5.3 Robustness Against Radiation -- 6 Conclusions and Future Work -- References -- Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs -- Abstract -- 1 Introduction -- 2 Structurally Synthesized BDD -- 3 Synthesis of SSBDDs -- 4 Fault Equivalence and Fault Dominance on the SSBDD Model -- 5 Fault Equivalence and Fault Dominance Fast Reasoning on the SSBDD Model -- 6 Lower and Higher Bounds for Fault Collapsing -- 7 Experimental Data -- 8 Conclusions -- Acknowledgments -- References -- A Hardware Accelerator for Real Time Sliding Window Based Pedestrian Detection on High Resolution Images -- Abstract -- 1 Introduction -- 2 Literature Survey -- 2.1 Sliding Window Based Pedestrian Detection -- 2.2 Real Time Pedestrian Detection -- 3 Overview of HOG -- 4 Hardware Architecture -- 4.1 Gradient Computation -- 4.2 Cell Histogram Generation -- 4.3 Block Histogram Normalization -- 4.4 SVM Classification -- 5 Results and Discussion -- 5.1 Experimental Setup -- 5.2 Accuracy Analysis -- 5.3 Throughput and Power Consumption Analysis -- 5.4 Choice of Parameters -- 6 Conclusion -- Acknowledgments -- References.
Wearable ECG SoC for Wireless Body Area Networks: Implementation with Fuzzy Decision Making Chip -- Abstract -- 1 Introduction -- 2 Prior Art -- 3 Wearable ECG System: With Decision Making -- 3.1 System Overview -- 3.2 ECG on Chip -- 3.3 Fuzzy Decision Making Chip: Concepts, Design and Implementation -- 4 Results and Discussion -- 4.1 ECG Acquisition -- 4.2 Fuzzy Decision Making -- 4.3 Performance Evaluation -- 5 Concluding Remarks -- Acknowledgement -- References -- Delay Testing Based on Multiple Faulty Behaviors -- 1 Introduction -- 2 Functional Faults Caused by Distributed Additional Delay -- 3 Functional Delay Fault Models -- 3.1 Functional Delay Fault Model with Two Time Frames, FDF2 -- 3.2 Functional Delay Fault Model with One Time Frame, FDF1 -- 4 ATPG Methods Based on Incremental SAT Formulation -- 4.1 Application of Test Vectors -- 5 Experimental Results -- 6 Concluding Remarks -- References -- A Temperature-Aware Battery Cycle Life Model for Different Battery Chemistries -- 1 Introduction -- 2 Background and Motivations -- 2.1 Battery Aging Issues -- 2.2 Battery Aging Models -- 2.3 Motivations for the Work -- 3 Modeling Methodology -- 3.1 Model Definition -- 3.2 Analysis of the Mathematical Model -- 3.3 Extraction of Model Parameters -- 4 Model Validation -- 4.1 VRLA Batteries -- 4.2 Other Battery Chemistries -- 5 Extension of the Basic Model -- 5.1 Impact of the Temperature on Cycle Life -- 5.2 Impact of the Current on Cycle Life -- 5.3 Results -- 6 Conclusion -- References -- A SAR Pipeline ADC Embedding Time Interleaved DAC Sharing for Ultra-low Power Camera Front Ends -- 1 Introduction -- 2 ADC Architectures for CS Image Acquisition -- 3 SAR-Pipeline ADC Architecture for CS Measurements -- 4 Design Components -- 4.1 Stage 1 ADC and Residue Amplification -- 4.2 Stage 2 ADC -- 5 Analysis of Capacitor Mismatch -- 6 Simulation Results. 7 Power Budget & Energy Efficiency -- 8 Comparison with Reported Works -- 9 Conclusion -- References -- Electromagnetic Transmission of Intellectual Property Data to Protect FPGA Designs -- Abstract -- 1 Introduction -- 1.1 The Threat Model of IC and IP -- 1.2 Salware vs. Malware -- 2 EM Communication of IP Data -- 2.1 Principle -- 2.2 Ultra-Lightweight Digital BFSK Transmitter -- 3 Experimental Results -- 4 Second Version of the Ultra-Lightweight Digital EM Transmitter -- 5 Comparison with State of the Art Spy Circuitries Using a Side-Channel -- 6 Industrial Scenarios Using the Proposed IP Protection -- 7 Conclusion -- Acknowledgment -- References -- JAIP-MP: A Four-Core Java Application Processor for Embedded Systems -- Abstract -- 1 Introduction -- 1.1 Multi-core Java Processors -- 1.2 Potentials of Hardwired Virtual Machines -- 2 The Architecture of the JAIP Core -- 2.1 The Overview of JAIP Core -- 2.2 The Bytecode Execution Engine and the Stack Memory -- 2.3 Single-Core Preemptive Thread Management -- 2.4 The Memory Manager and Garbage Collector -- 2.5 Dynamic Symbol Resolution Unit and the I/O Subsystem -- 3 Multi-core Integration of JAIP -- 3.1 The Multi-core Thread Manager -- 3.2 The Data Coherence Controller Architecture -- 4 Experimental Results -- 4.1 Single-Core Multithread Performance Evaluation -- 4.2 Multi-core Multithread Performance Evaluation -- 4.3 Synchronization Overhead -- 5 Conclusions and Future Work -- References -- Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach -- 1 Introduction -- 2 Related Works -- 3 Background and Preliminaries -- 3.1 Definitions -- 3.2 Comparing Data Mining and Assertion Mining -- 4 Methodology -- 5 Assertion Mining -- 5.1 Mining of Interesting Behaviors -- 5.2 Pruning of Behaviours -- 5.3 Mining of Assertions -- 6 Assertion Qualification. 6.1 Metrics -- 6.2 Assertion Ranking -- 7 Experimental Results -- 7.1 Assertion Qualification -- 8 Conclusions -- References -- Author Index. |
| Record Nr. | UNINA-9910254985403321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design [[electronic resource] ] : 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers / / edited by Andreas Burg, Ayse Coskun, Matthew Guthaus, Srinivas Katkoori, Ricardo Reis
| VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design [[electronic resource] ] : 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers / / edited by Andreas Burg, Ayse Coskun, Matthew Guthaus, Srinivas Katkoori, Ricardo Reis |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 |
| Descrizione fisica | 1 online resource (X, 235 p. 121 illus.) |
| Disciplina | 003.3 |
| Collana | IFIP Advances in Information and Communication Technology |
| Soggetto topico |
Architecture, Computer
Computer hardware Computer organization Computer System Implementation Computer Hardware Computer Systems Organization and Communication Networks |
| ISBN | 3-642-45073-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | FPGA-Based High-Speed Authenticated Encryption System -- A Smart Memory Accelerated Computed Tomography Parallel Backprojection -- Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure -- Spatially-Varying Image Warping: Evaluations and VLSI Implementations -- An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing -- Configurable Low-Latency Interconnect for Multi-core Clusters -- A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks -- Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections -- On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors -- SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture -- CMOS Implementation of Threshold Gates with Hysteresis -- Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates. |
| Record Nr. | UNINA-9910437570503321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
VLSI-SoC: Internet of Things Foundations [[electronic resource] ] : 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised Selected Papers / / edited by Luc Claesen, Maria-Teresa Sanz-Pascual, Ricardo Reis, Arturo Sarmiento-Reyes
| VLSI-SoC: Internet of Things Foundations [[electronic resource] ] : 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised Selected Papers / / edited by Luc Claesen, Maria-Teresa Sanz-Pascual, Ricardo Reis, Arturo Sarmiento-Reyes |
| Edizione | [1st ed. 2015.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 |
| Descrizione fisica | 1 online resource (XIV, 241 p. 150 illus. in color.) |
| Disciplina | 004 |
| Collana | IFIP Advances in Information and Communication Technology |
| Soggetto topico |
Computer organization
Computer hardware Computer-aided engineering Computer Systems Organization and Communication Networks Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design |
| ISBN | 3-319-25279-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Organization -- Contents -- Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip -- 1 Introduction -- 2 Related Work -- 3 Lifetime Budget Definition -- 4 Lifetime-Aware Adaptive Routing -- 4.1 Problem Definition -- 4.2 Dynamic Programming-Based Formulation -- 4.3 Lifetime-Aware Adaptive Routing Algorithm -- 4.4 Dynamic Programming Network -- 4.5 Lifetime Budget Runtime Computation -- 5 Experimental Results -- 5.1 Experimental Setup -- 5.2 MTTF Distribution -- 5.3 Minimal MTTF Evaluation -- 5.4 NoC Overall MTTF Evaluation -- 5.5 Variance of MTTF -- 5.6 Average Packets Delay Comparison -- 5.7 Hardware Evaluation -- 6 Conclusions and Future Work -- References -- Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs -- Abstract -- 1 Introduction -- 2 Related Work -- 3 Sequential Linear Decompression -- 4 Proposed Architecture -- 5 Optimizing Number of Test Elevators by Inter-layer Serialization of Test Data -- 6 Experimental Results -- 7 Conclusion and Future Work -- References -- Design and Optimization of Multiple-Mesh Clock Network -- 1 Introduction -- 2 Preliminaries -- 2.1 Clock Mesh Structure and Its Synthesis -- 2.2 Multi-level Clock Gating -- 3 Mesh Clock Networks for Multi-level Clock Gating -- 3.1 Single-Mesh Implementation -- 3.2 Multiple-Mesh Implementation -- 3.3 Assessment -- 4 Choosing Mesh Implementation Style -- 4.1 Switching Capacitance Estimation -- 5 Floorplanning of Multiple Meshes -- 5.1 Assessment -- 6 Comparison with Clock Tree -- 6.1 Clock Skew Variation -- 7 Related Work -- 8 Conclusion -- References -- Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture -- 1 Introduction -- 2 Background -- 2.1 STT-RAM Technology -- 2.2 Hybrid Approach for Last-Level Caches -- 2.3 Cache Partitioning Technique -- 3 Partitioning Technique for Hybrid Caches.
3.1 Motivation -- 3.2 Architecture -- 3.3 Replacement Policy -- 3.4 Allocation Switching Technique -- 4 Evaluation Methodology -- 4.1 Simulator -- 4.2 Workloads -- 5 Results -- 5.1 Performance -- 5.2 Miss Rates -- 5.3 Cache Energy Consumption -- 5.4 DRAM Energy Consumption -- 5.5 Area Overhead -- 6 Related Work -- 6.1 Reducing Write Overhead of STT-RAM -- 6.2 Cache Partitioning for Energy Saving -- 7 Conclusion -- References -- Interval Arithmetic and Self Similarity Based Subthreshold Leakage Optimization in RTL Datapaths -- 1 Introduction and Motivation -- 2 Background, Related Work, and Terminology -- 2.1 Input Vector Control Techniques -- 2.2 Fractals and Self Similarity -- 2.3 Interval Arithmetic -- 2.4 Notation and Problem Formulation -- 3 Self Similarity Based Monte Carlo Characterization for Low Leakage Intervals -- 3.1 Leakage Profile and Scope for Optimization -- 3.2 Self Similarity of Leakage Distributions in n Bit Adders and Multipliers -- 3.3 Monte Carlo Based Low Leakage Interval Search -- 4 Proposed Approach -- 4.1 Motivating Examples -- 4.2 Low Leakage Vector Determination -- 5 Experimental Results -- 6 Conclusion -- References -- 8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology -- Abstract -- 1 Introduction -- 2 The Proposed 8T-SRAM Cell -- 3 Simulation Results and Comparison -- 4 Conclusions -- References -- On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms -- 1 Introduction -- 2 Background and Related Works -- 2.1 QEMU -- 2.2 OVP -- 3 Co-simulation Architecture -- 3.1 SystemC Bridge -- 3.2 Virtual Device -- 3.3 Interrupt Handling -- 4 Experimental Results -- 5 Conclusions -- References -- Statistical Evaluation of Digital Techniques for ADC BIST -- 1 Introduction -- 2 Dynamic Test of ADCs Using Digital Ternary Stimuli -- 2.1 Ternary Stimulus: Theoretical Basis. 2.2 Ternary Stimulus Optimization -- 2.3 Response Evaluation: Theoretical Basis -- 3 Efficient On-chip Implementation -- 4 Simulation Framework -- 5 Case Study -- 5.1 Behavioral Model -- 5.2 Fault-Free Case -- 5.3 Nominal and Extreme Variations -- 5.4 Parametric Test Metrics Estimation -- 6 Conclusion -- References -- A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm -- 1 Introduction -- 2 System Model -- 3 MCMC-Based MIMO Detection -- 4 Low-Level Algorithm -- 4.1 Basic Concepts -- 4.2 Overall Algorithm Design -- 4.3 Front-end Processing -- 4.4 Gibbs Sampler -- 4.5 Metric Update -- 4.6 LLR Computation -- 5 VLSI Architecture -- 5.1 Overview -- 5.2 FEP-Circuit -- 5.3 GS/M-Circuit -- 5.4 L-Circuit -- 6 Differences to Reference Architecture -- 7 Results -- 7.1 Simulation Setup -- 7.2 Architecture -- 7.3 Synthesis Results -- 7.4 Layout Results -- 8 Algorithmic Considerations -- 9 Conclusions and Outlook -- References -- Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras -- 1 Introduction -- 2 Omnidirectional Vision Reconstruction Algorithm -- 3 Distributed and Parallel Implementation -- 3.1 Processing Demands -- 3.2 Effects of Pixelation Schemes -- 4 Interconnected Network of Cameras -- 4.1 Camera Assignment Problem -- 4.2 Central Unit Access -- 4.3 Verification -- 5 Panoptic Media Platform -- 5.1 Central FPGA -- 5.2 Slave FPGAs -- 5.3 Inter FPGA Communication -- 5.4 Implementation Results -- 6 Visualization of Omnidirectional Data -- 6.1 Server Application -- 6.2 Client Application -- 6.3 Future Work -- 7 A Real-Time HDR Panorama with Panoptic Camera -- 7.1 HDR Composite Frame -- 7.2 Tone Mapping -- 7.3 FPGA Implementation -- 7.4 Discussion and Future Work -- 8 Conclusion and Future Work -- References -- Transmission Channel Noise Aware Energy Effective LDPC Decoding -- 1 Introduction. 2 Sum-Product LDPC Decoding -- 3 Proposed Technique -- 3.1 Pre-characterization -- 3.2 Adaptation -- 4 Evaluation -- 5 Conclusions -- References -- Laser-Induced Fault Effects in Security-Dedicated Circuits -- Abstract -- 1 Introduction -- 2 Laser/Silicon Interaction -- 2.1 Photoelectric Effect -- 2.2 Single Event Transient (SET) and Single Event Upset (SEU) -- 3 Global Flow: Overview -- 4 Measures on Bulk and FDSOI Components -- 5 Models: From Physical-Level to Behavioral-Level -- 5.1 Physical-Level -- 5.2 Electrical --Level -- 5.3 Logical Level -- 5.4 Behavioral Level -- 6 CAD Tools -- 7 Counter-Measures -- 7.1 Structure of the Detector -- 7.2 Detector Sensitivity -- 7.3 Insertion of Detectors in the Design -- 8 Conclusions -- Acknowledgment -- References -- Author Index. |
| Record Nr. | UNINA-9910299255103321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
VLSI-SoC: New Technology Enabler [[electronic resource] ] : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6–9, 2019, Revised and Extended Selected Papers / / edited by Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva-Cardenas, Ricardo Reis
| VLSI-SoC: New Technology Enabler [[electronic resource] ] : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6–9, 2019, Revised and Extended Selected Papers / / edited by Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva-Cardenas, Ricardo Reis |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XVII, 345 p. 214 illus., 129 illus. in color.) |
| Disciplina | 621.395 |
| Collana | IFIP Advances in Information and Communication Technology |
| Soggetto topico |
Computer organization
Microprogramming Input-output equipment (Computers) Operating systems (Computers) Computer Systems Organization and Communication Networks Control Structures and Microprogramming Input/Output and Data Communications Operating Systems |
| ISBN | 3-030-53273-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Software-Based Self-Test for Delay Faults -- On Test Generation for Microprocessors for Extended Class of Functional Faults -- Robust FinFET Schmitt Trigger Designs for Low Power Applications -- An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults -- Process Variability Impact on the SET Response of FinFET Multi-level Design -- Efficient Soft Error Vulnerability Analysis Using Non-Intrusive Fault Injection Techniques -- A Statistical Wafer Scale Error and Redundancy Analysis Simulator -- Hardware-enabled Secure Firmware Updates in Embedded Systems -- Reliability Enhanced Digital Low-Dropout Regulator with Improved Transient Performance -- Security Aspects of Real-time MPSoCs: The Flaws and Opportunities of Preemptive NoCs -- Offset-Compensation Systems for Multi-Gbit/s Optical Receivers -- Accelerating Inference on Binary Neural Networks with Digital RRAM Processing -- Semi- and Fully-Random Access LUTs for Smooth Functions -- A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors -- Exploiting Heterogeneous Mobile Architectures through a Unified Runtime Framework. |
| Record Nr. | UNINA-9910413438303321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
