Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
Handbook of 3D integration . Volume 3 3D process technology / / edited by Philip Garrou, Mitsumasa Koyanagi, and Peter Ramm ; Richard A. Allen [and sixty others], contributors
| Handbook of 3D integration . Volume 3 3D process technology / / edited by Philip Garrou, Mitsumasa Koyanagi, and Peter Ramm ; Richard A. Allen [and sixty others], contributors |
| Pubbl/distr/stampa | Weinheim, Germany : , : Wiley-VCH, , 2014 |
| Descrizione fisica | 1 online resource (475 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Integrated circuits
Integrated circuits - Design and construction Silicon Three-dimensional imaging |
| ISBN |
3-527-67012-2
3-527-67010-6 3-527-67013-0 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Handbook of 3D Integration: 3D Process Technology; Contents; List of Contributors; 1 3D IC Integration Since 2008; 1.1 3D IC Nomenclature; 1.2 Process Standardization; 1.3 The Introduction of Interposers (2.5D); 1.4 The Foundries; 1.4.1 TSMC; 1.4.2 UMC; 1.4.3 GlobalFoundries; 1.5 Memory; 1.5.1 Samsung; 1.5.2 Micron; 1.5.3 Hynix; 1.6 The Assembly and Test Houses; 1.7 3D IC Application Roadmaps; References; 2 Key Applications and Market Trends for 3D Integration and Interposer Technologies; 2.1 Introduction; 2.2 Advanced Packaging Importance in the Semiconductor Industry is Growing
2.3 3D Integration-Focused Activities - The Global IP Landscape2.4 Applications, Technology, and Market Trends; References; 3 Economic Drivers and Impediments for 2.5D/3D Integration; 3.1 3D Performance Advantages; 3.2 The Economics of Scaling; 3.3 The Cost of Future Scaling; 3.4 Cost Remains the Impediment to 2.5D and 3D Product Introduction; 3.4.1 Required Economics for Interposer Use in Mobile Products; 3.4.2 Silicon Interposer Pricing; References; 4 Interposer Technology; 4.1 Definition of 2.5D Interposers; 4.2 Interposer Drivers and Need; 4.3 Comparison of Interposer Materials 4.4 Silicon Interposers with TSV4.5 Lower Cost Interposers; 4.5.1 Glass Interposers; 4.5.1.1 Challenges in Glass Interposers; 4.5.1.2 Small-Pitch Through-Package Via Hole Formation and Ultrathin Glass Handling; 4.5.1.3 Metallization of Glass TPV; 4.5.1.4 Reliability of Copper TPVs in Glass Interposers; 4.5.1.5 Thermal Dissipation of Glass; 4.5.1.6 Glass Interposer Fabrication with TPV and RDL; 4.5.2 Low-CTE Organic Interposers; 4.5.3 Polycrystalline Silicon Interposer; 4.5.3.1 Polycrystalline Silicon Interposer Fabrication Process; 4.6 Interposer Technical and Manufacturing Challenges 4.7 Interposer Application Examples4.8 Conclusions; References; 5 TSV Formation Overview; 5.1 Introduction; 5.2 TSV Process Approaches; 5.2.1 TSV-Middle Approach; 5.2.2 Backside TSV-Last Approach; 5.2.3 Front-Side TSV-Last Approach; 5.3 TSV Fabrication Steps; 5.3.1 TSV Etching; 5.3.2 TSV Insulation; 5.3.3 TSV Metallization; 5.3.4 Overburden Removal by CMP; 5.3.5 TSV Anneal; 5.3.6 Temporary Carrier Wafer Bonding and Debonding; 5.3.7 Wafer Thinning and TSV Reveal; 5.4 Yield and Reliability; References; 6 TSV Unit Processes and Integration; 6.1 Introduction; 6.2 TSV Process Overview 6.3 TSV Unit Processes6.3.1 Etching; 6.3.2 Insulator Deposition with CVD; 6.3.3 Metal Liner/Barrier Deposition with PVD; 6.3.4 Via Filling by ECD of Copper; 6.3.5 CMP of Copper; 6.3.6 Temporary Bonding between Carrier and Device Wafer; 6.3.7 Wafer Backside Thinning; 6.3.8 Backside RDL; 6.3.9 Metrology, Inspection, and Defect Review; 6.4 Integration and Co-optimization of Unit Processes in Via Formation Sequence; 6.5 Co-optimization of Unit Processes in Backside Processing and Via-Reveal Flow; 6.6 Integration and Co-optimization of Unit Processes in Via-Last Flow 6.7 Integration with Packaging |
| Record Nr. | UNINA-9910139111803321 |
| Weinheim, Germany : , : Wiley-VCH, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of 3D integration . Volume 3 3D process technology / / edited by Philip Garrou, Mitsumasa Koyanagi, and Peter Ramm ; Richard A. Allen [and sixty others], contributors
| Handbook of 3D integration . Volume 3 3D process technology / / edited by Philip Garrou, Mitsumasa Koyanagi, and Peter Ramm ; Richard A. Allen [and sixty others], contributors |
| Pubbl/distr/stampa | Weinheim, Germany : , : Wiley-VCH, , 2014 |
| Descrizione fisica | 1 online resource (475 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Integrated circuits
Integrated circuits - Design and construction Silicon Three-dimensional imaging |
| ISBN |
3-527-67012-2
3-527-67010-6 3-527-67013-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Handbook of 3D Integration: 3D Process Technology; Contents; List of Contributors; 1 3D IC Integration Since 2008; 1.1 3D IC Nomenclature; 1.2 Process Standardization; 1.3 The Introduction of Interposers (2.5D); 1.4 The Foundries; 1.4.1 TSMC; 1.4.2 UMC; 1.4.3 GlobalFoundries; 1.5 Memory; 1.5.1 Samsung; 1.5.2 Micron; 1.5.3 Hynix; 1.6 The Assembly and Test Houses; 1.7 3D IC Application Roadmaps; References; 2 Key Applications and Market Trends for 3D Integration and Interposer Technologies; 2.1 Introduction; 2.2 Advanced Packaging Importance in the Semiconductor Industry is Growing
2.3 3D Integration-Focused Activities - The Global IP Landscape2.4 Applications, Technology, and Market Trends; References; 3 Economic Drivers and Impediments for 2.5D/3D Integration; 3.1 3D Performance Advantages; 3.2 The Economics of Scaling; 3.3 The Cost of Future Scaling; 3.4 Cost Remains the Impediment to 2.5D and 3D Product Introduction; 3.4.1 Required Economics for Interposer Use in Mobile Products; 3.4.2 Silicon Interposer Pricing; References; 4 Interposer Technology; 4.1 Definition of 2.5D Interposers; 4.2 Interposer Drivers and Need; 4.3 Comparison of Interposer Materials 4.4 Silicon Interposers with TSV4.5 Lower Cost Interposers; 4.5.1 Glass Interposers; 4.5.1.1 Challenges in Glass Interposers; 4.5.1.2 Small-Pitch Through-Package Via Hole Formation and Ultrathin Glass Handling; 4.5.1.3 Metallization of Glass TPV; 4.5.1.4 Reliability of Copper TPVs in Glass Interposers; 4.5.1.5 Thermal Dissipation of Glass; 4.5.1.6 Glass Interposer Fabrication with TPV and RDL; 4.5.2 Low-CTE Organic Interposers; 4.5.3 Polycrystalline Silicon Interposer; 4.5.3.1 Polycrystalline Silicon Interposer Fabrication Process; 4.6 Interposer Technical and Manufacturing Challenges 4.7 Interposer Application Examples4.8 Conclusions; References; 5 TSV Formation Overview; 5.1 Introduction; 5.2 TSV Process Approaches; 5.2.1 TSV-Middle Approach; 5.2.2 Backside TSV-Last Approach; 5.2.3 Front-Side TSV-Last Approach; 5.3 TSV Fabrication Steps; 5.3.1 TSV Etching; 5.3.2 TSV Insulation; 5.3.3 TSV Metallization; 5.3.4 Overburden Removal by CMP; 5.3.5 TSV Anneal; 5.3.6 Temporary Carrier Wafer Bonding and Debonding; 5.3.7 Wafer Thinning and TSV Reveal; 5.4 Yield and Reliability; References; 6 TSV Unit Processes and Integration; 6.1 Introduction; 6.2 TSV Process Overview 6.3 TSV Unit Processes6.3.1 Etching; 6.3.2 Insulator Deposition with CVD; 6.3.3 Metal Liner/Barrier Deposition with PVD; 6.3.4 Via Filling by ECD of Copper; 6.3.5 CMP of Copper; 6.3.6 Temporary Bonding between Carrier and Device Wafer; 6.3.7 Wafer Backside Thinning; 6.3.8 Backside RDL; 6.3.9 Metrology, Inspection, and Defect Review; 6.4 Integration and Co-optimization of Unit Processes in Via Formation Sequence; 6.5 Co-optimization of Unit Processes in Backside Processing and Via-Reveal Flow; 6.6 Integration and Co-optimization of Unit Processes in Via-Last Flow 6.7 Integration with Packaging |
| Record Nr. | UNINA-9910822662203321 |
| Weinheim, Germany : , : Wiley-VCH, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of 3D integration [[electronic resource] ] : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm
| Handbook of 3D integration [[electronic resource] ] : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm |
| Pubbl/distr/stampa | Weinheim, : Wiley-VCH, 2008 |
| Descrizione fisica | 1 online resource (801 p.) |
| Disciplina |
621.381
621.3815 |
| Altri autori (Persone) |
GarrouPhilip E
BowerChristopher Andrew RammPeter |
| Soggetto topico |
Integrated circuits
Integrated circuits - Design and construction Semiconductor wafers Three-dimensional imaging |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-283-86967-5
3-527-62306-X 3-527-62305-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Handbook of 3D Integration; Contents; Preface; List of Contributors; 1 Introduction to 3D Integration; 1.1 Introduction; 1.2 Historical Evolution of Stacked Wafer Concepts; 1.3 3D Packaging vs 3D Integration; 1.4 Non-TSV 3D Stacking Technologies; 1.4.1 Irvine Sensors; 1.4.2 UTCS (Ultrathin Chip Stacking) IMEC, CNRS, U. Barcelona; 1.4.3 Fujitsu; 1.4.4 Fraunhofer/IZM; 1.4.5 3D Plus/Leti; 1.4.6 Toshiba System Block Module; References; 2 Drivers for 3D Integration; 2.1 Introduction; 2.2 Electrical Performance; 2.2.1 Signal Seed; 2.2.2 Memory Latency; 2.3 Power Consumption and Noise; 2.3.1 Noise
2.4 Form Factor2.4.1 Non-Volatile Memory Technology: Flash; 2.4.2 Volatile Memory Technology: SRAM and DRAM; 2.4.3 CMOS Image Sensors; 2.5 Lower Cost; 2.6 Application Based Drivers; 2.6.1 Microprocessors; 2.6.2 Memory; 2.6.3 Sensors; 2.6.4 Fields Programmable Gate Arrays (FPGAs); References; 3 Overview of 3D Integration Process Technology; 3.1 3D Integration Terminology; 3.1.1 Through Silicon Vias (TSVs); 3.1.2 Wafer Thinning; 3.1.3 Aligned Wafer/IC Bonding; 3.2 Processing Sequences; 3.3 Technologies for 3D Integration; 3.3.1 TSV Formation; 3.3.2 Temporary Bonding to Carrier Wafer 3.3.3 Thinning3.3.4 Alignment/Bonding; References; I Through Silicon Via Fabrication; 4 Deep Reactive Ion Etching of Through Silicon Vias; 4.1 Introduction; 4.1.1 Deep Reactive Ion Etching as Breakthrough Enabling Through-Wafer Interconnects; 4.1.2 State of the Art and Basic Principles in DRIE; 4.1.3 Bosch Process; 4.1.4 Alternatives for Via Hole Creation; 4.2 DRIE Equipment and Characterization; 4.2.1 High-Density Plasma Reactors; 4.2.2 Plasma Chemistry; 4.2.3 Plasma Diagnostics and Surface Analysis; 4.3 DRIE Processing; 4.3.1 Mask Issues; 4.3.2 High Aspect Ratio Features 4.3.3 Sidewall Passivation, Depassivation and Profile Control4.4 Practical Solutions in Via Etching; 4.4.1 Undercut and Scallop Reduction; 4.4.2 Sidewall Roughness Minimization; 4.4.3 Loading Effects; 4.4.4 Notching at Dielectric Interfaces; 4.4.5 Inspection of Via Structures; 4.4.6 In Situ Trench Depth Measurement; 4.5 Concluding Remarks; Appendix A: Glossary of Abbreviations; Appendix B: Examples of DRIE Recipes; References; 5 Laser Ablation; 5.1 Introduction; 5.2 Laser Technology for 3D Packaging; 5.2.1 Advantages; 5.2.2 Disadvantages; 5.3 For Si Substrate; 5.3.1 Difficulties 5.3.2 Results5.4 Results for 3D Chip Stacking; 5.5 Reliabilities; 5.6 The Future; References; 6 SiO(2); 6.1 Introduction; 6.2 Dielectric CVD; 6.2.1 Sub-Atmospheric CVD; 6.2.2 Process Sequence of O(3)-Activated SACVD Deposition; 6.2.3 Conformal SACVD O(3) TEOS Films for 3D Integration; 6.3 Dielectric Film Properties; 6.4 3D-Specifics Regarding SiO(2) Dielectrics; 6.4.1 Wafer Pre-Processing; 6.4.2 Backside Processing Requirements on SiO(2) Film Conformality in TSVs; 6.4.3 SiO(2) Film Deposition on Thinned Silicon Substrates; 6.5 Concluding Remarks; References; 7 Insulation - Organic Dielectrics 7.1 Parylene |
| Record Nr. | UNINA-9910144685303321 |
| Weinheim, : Wiley-VCH, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of 3D integration [[electronic resource] ] : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm
| Handbook of 3D integration [[electronic resource] ] : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm |
| Pubbl/distr/stampa | Weinheim, : Wiley-VCH, 2008 |
| Descrizione fisica | 1 online resource (801 p.) |
| Disciplina |
621.381
621.3815 |
| Altri autori (Persone) |
GarrouPhilip E
BowerChristopher Andrew RammPeter |
| Soggetto topico |
Integrated circuits
Integrated circuits - Design and construction Semiconductor wafers Three-dimensional imaging |
| ISBN |
1-283-86967-5
3-527-62306-X 3-527-62305-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Handbook of 3D Integration; Contents; Preface; List of Contributors; 1 Introduction to 3D Integration; 1.1 Introduction; 1.2 Historical Evolution of Stacked Wafer Concepts; 1.3 3D Packaging vs 3D Integration; 1.4 Non-TSV 3D Stacking Technologies; 1.4.1 Irvine Sensors; 1.4.2 UTCS (Ultrathin Chip Stacking) IMEC, CNRS, U. Barcelona; 1.4.3 Fujitsu; 1.4.4 Fraunhofer/IZM; 1.4.5 3D Plus/Leti; 1.4.6 Toshiba System Block Module; References; 2 Drivers for 3D Integration; 2.1 Introduction; 2.2 Electrical Performance; 2.2.1 Signal Seed; 2.2.2 Memory Latency; 2.3 Power Consumption and Noise; 2.3.1 Noise
2.4 Form Factor2.4.1 Non-Volatile Memory Technology: Flash; 2.4.2 Volatile Memory Technology: SRAM and DRAM; 2.4.3 CMOS Image Sensors; 2.5 Lower Cost; 2.6 Application Based Drivers; 2.6.1 Microprocessors; 2.6.2 Memory; 2.6.3 Sensors; 2.6.4 Fields Programmable Gate Arrays (FPGAs); References; 3 Overview of 3D Integration Process Technology; 3.1 3D Integration Terminology; 3.1.1 Through Silicon Vias (TSVs); 3.1.2 Wafer Thinning; 3.1.3 Aligned Wafer/IC Bonding; 3.2 Processing Sequences; 3.3 Technologies for 3D Integration; 3.3.1 TSV Formation; 3.3.2 Temporary Bonding to Carrier Wafer 3.3.3 Thinning3.3.4 Alignment/Bonding; References; I Through Silicon Via Fabrication; 4 Deep Reactive Ion Etching of Through Silicon Vias; 4.1 Introduction; 4.1.1 Deep Reactive Ion Etching as Breakthrough Enabling Through-Wafer Interconnects; 4.1.2 State of the Art and Basic Principles in DRIE; 4.1.3 Bosch Process; 4.1.4 Alternatives for Via Hole Creation; 4.2 DRIE Equipment and Characterization; 4.2.1 High-Density Plasma Reactors; 4.2.2 Plasma Chemistry; 4.2.3 Plasma Diagnostics and Surface Analysis; 4.3 DRIE Processing; 4.3.1 Mask Issues; 4.3.2 High Aspect Ratio Features 4.3.3 Sidewall Passivation, Depassivation and Profile Control4.4 Practical Solutions in Via Etching; 4.4.1 Undercut and Scallop Reduction; 4.4.2 Sidewall Roughness Minimization; 4.4.3 Loading Effects; 4.4.4 Notching at Dielectric Interfaces; 4.4.5 Inspection of Via Structures; 4.4.6 In Situ Trench Depth Measurement; 4.5 Concluding Remarks; Appendix A: Glossary of Abbreviations; Appendix B: Examples of DRIE Recipes; References; 5 Laser Ablation; 5.1 Introduction; 5.2 Laser Technology for 3D Packaging; 5.2.1 Advantages; 5.2.2 Disadvantages; 5.3 For Si Substrate; 5.3.1 Difficulties 5.3.2 Results5.4 Results for 3D Chip Stacking; 5.5 Reliabilities; 5.6 The Future; References; 6 SiO(2); 6.1 Introduction; 6.2 Dielectric CVD; 6.2.1 Sub-Atmospheric CVD; 6.2.2 Process Sequence of O(3)-Activated SACVD Deposition; 6.2.3 Conformal SACVD O(3) TEOS Films for 3D Integration; 6.3 Dielectric Film Properties; 6.4 3D-Specifics Regarding SiO(2) Dielectrics; 6.4.1 Wafer Pre-Processing; 6.4.2 Backside Processing Requirements on SiO(2) Film Conformality in TSVs; 6.4.3 SiO(2) Film Deposition on Thinned Silicon Substrates; 6.5 Concluding Remarks; References; 7 Insulation - Organic Dielectrics 7.1 Parylene |
| Record Nr. | UNINA-9910829969203321 |
| Weinheim, : Wiley-VCH, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of 3D integration : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm
| Handbook of 3D integration : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm |
| Pubbl/distr/stampa | Weinheim, : Wiley-VCH, 2008 |
| Descrizione fisica | 1 online resource (801 p.) |
| Disciplina |
621.381
621.3815 |
| Altri autori (Persone) |
GarrouPhilip E
BowerChristopher Andrew RammPeter |
| Soggetto topico |
Integrated circuits
Integrated circuits - Design and construction Semiconductor wafers Three-dimensional imaging |
| ISBN |
1-283-86967-5
3-527-62306-X 3-527-62305-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Handbook of 3D Integration; Contents; Preface; List of Contributors; 1 Introduction to 3D Integration; 1.1 Introduction; 1.2 Historical Evolution of Stacked Wafer Concepts; 1.3 3D Packaging vs 3D Integration; 1.4 Non-TSV 3D Stacking Technologies; 1.4.1 Irvine Sensors; 1.4.2 UTCS (Ultrathin Chip Stacking) IMEC, CNRS, U. Barcelona; 1.4.3 Fujitsu; 1.4.4 Fraunhofer/IZM; 1.4.5 3D Plus/Leti; 1.4.6 Toshiba System Block Module; References; 2 Drivers for 3D Integration; 2.1 Introduction; 2.2 Electrical Performance; 2.2.1 Signal Seed; 2.2.2 Memory Latency; 2.3 Power Consumption and Noise; 2.3.1 Noise
2.4 Form Factor2.4.1 Non-Volatile Memory Technology: Flash; 2.4.2 Volatile Memory Technology: SRAM and DRAM; 2.4.3 CMOS Image Sensors; 2.5 Lower Cost; 2.6 Application Based Drivers; 2.6.1 Microprocessors; 2.6.2 Memory; 2.6.3 Sensors; 2.6.4 Fields Programmable Gate Arrays (FPGAs); References; 3 Overview of 3D Integration Process Technology; 3.1 3D Integration Terminology; 3.1.1 Through Silicon Vias (TSVs); 3.1.2 Wafer Thinning; 3.1.3 Aligned Wafer/IC Bonding; 3.2 Processing Sequences; 3.3 Technologies for 3D Integration; 3.3.1 TSV Formation; 3.3.2 Temporary Bonding to Carrier Wafer 3.3.3 Thinning3.3.4 Alignment/Bonding; References; I Through Silicon Via Fabrication; 4 Deep Reactive Ion Etching of Through Silicon Vias; 4.1 Introduction; 4.1.1 Deep Reactive Ion Etching as Breakthrough Enabling Through-Wafer Interconnects; 4.1.2 State of the Art and Basic Principles in DRIE; 4.1.3 Bosch Process; 4.1.4 Alternatives for Via Hole Creation; 4.2 DRIE Equipment and Characterization; 4.2.1 High-Density Plasma Reactors; 4.2.2 Plasma Chemistry; 4.2.3 Plasma Diagnostics and Surface Analysis; 4.3 DRIE Processing; 4.3.1 Mask Issues; 4.3.2 High Aspect Ratio Features 4.3.3 Sidewall Passivation, Depassivation and Profile Control4.4 Practical Solutions in Via Etching; 4.4.1 Undercut and Scallop Reduction; 4.4.2 Sidewall Roughness Minimization; 4.4.3 Loading Effects; 4.4.4 Notching at Dielectric Interfaces; 4.4.5 Inspection of Via Structures; 4.4.6 In Situ Trench Depth Measurement; 4.5 Concluding Remarks; Appendix A: Glossary of Abbreviations; Appendix B: Examples of DRIE Recipes; References; 5 Laser Ablation; 5.1 Introduction; 5.2 Laser Technology for 3D Packaging; 5.2.1 Advantages; 5.2.2 Disadvantages; 5.3 For Si Substrate; 5.3.1 Difficulties 5.3.2 Results5.4 Results for 3D Chip Stacking; 5.5 Reliabilities; 5.6 The Future; References; 6 SiO(2); 6.1 Introduction; 6.2 Dielectric CVD; 6.2.1 Sub-Atmospheric CVD; 6.2.2 Process Sequence of O(3)-Activated SACVD Deposition; 6.2.3 Conformal SACVD O(3) TEOS Films for 3D Integration; 6.3 Dielectric Film Properties; 6.4 3D-Specifics Regarding SiO(2) Dielectrics; 6.4.1 Wafer Pre-Processing; 6.4.2 Backside Processing Requirements on SiO(2) Film Conformality in TSVs; 6.4.3 SiO(2) Film Deposition on Thinned Silicon Substrates; 6.5 Concluding Remarks; References; 7 Insulation - Organic Dielectrics 7.1 Parylene |
| Record Nr. | UNINA-9910841560903321 |
| Weinheim, : Wiley-VCH, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of wafer bonding [[electronic resource] /] / edited by Peter Ramm, James Jian-Qiang Lu, and Maaike M.V. Taklo
| Handbook of wafer bonding [[electronic resource] /] / edited by Peter Ramm, James Jian-Qiang Lu, and Maaike M.V. Taklo |
| Pubbl/distr/stampa | Weinheim, Germany, : Wiley-VCH, 2012 |
| Descrizione fisica | 1 online resource (430 p.) |
| Disciplina | 621.38152 |
| Altri autori (Persone) |
RammPeter
LuJames Jian-Qiang TakloMaaike M. V |
| Soggetto topico |
Semiconductors - Bonding
Semiconductor wafers Microelectromechanical systems - Design and construction |
| ISBN |
3-527-64423-7
1-280-66282-4 9786613639752 3-527-64422-9 3-527-64424-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. 1. Technologies -- pt. 2. Applications. |
| Record Nr. | UNINA-9910139699603321 |
| Weinheim, Germany, : Wiley-VCH, 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of wafer bonding / / edited by Peter Ramm, James Jian-Qiang Lu, and Maaike M.V. Taklo
| Handbook of wafer bonding / / edited by Peter Ramm, James Jian-Qiang Lu, and Maaike M.V. Taklo |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Weinheim, Germany, : Wiley-VCH, 2012 |
| Descrizione fisica | 1 online resource (430 p.) |
| Disciplina | 621.38152 |
| Altri autori (Persone) |
RammPeter
LuJames Jian-Qiang TakloMaaike M. V |
| Soggetto topico |
Semiconductors - Bonding
Semiconductor wafers Microelectromechanical systems - Design and construction |
| ISBN |
3-527-64423-7
1-280-66282-4 9786613639752 3-527-64422-9 3-527-64424-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. 1. Technologies -- pt. 2. Applications. |
| Record Nr. | UNINA-9910815016903321 |
| Weinheim, Germany, : Wiley-VCH, 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||