Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
Intel Xeon Phi coprocessor architecture and tools : the guide for application developers / / Rezaur Rahman
| Intel Xeon Phi coprocessor architecture and tools : the guide for application developers / / Rezaur Rahman |
| Autore | Rahman Rezaur |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Apress, 2013 |
| Descrizione fisica | 1 online resource (xxi, 209 pages) : illustrations (some color) |
| Disciplina |
004
005.1 |
| Collana |
The expert's voice in microprocessors
Gale eBooks |
| Soggetto topico |
Coprocessors
Computer programming High performance computing |
| ISBN | 1-4302-5927-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
""Contents at a Glance""; ""Contents""; ""About the Author""; ""About the Technical Reviewer""; ""Acknowledgments""; ""Introduction""; ""Part1: Hardware Foundation: Intel Xeon Phi Architecture""; ""Chapter 1: Introduction to Xeon Phi Architecture""; ""History of Intel Xeon Phi Development""; ""Evolution from Von Neumann Architecture to Cache Subsystem Architecture""; ""Improvements in the Core and Memory""; ""Instruction-Level Parallelism""; ""Instruction Pipelining""; ""Single Instruction Multiple Data""; ""Multithreading""; ""Multicore and Manycore Architecture""
""Interconnect and Cache Improvements""""System Interconnect""; ""Intel Xeon Phi Coprocessor Chip Architecture""; ""Applicability of the Intel Xeon Phi Coprocessor""; ""Summary""; ""Chapter 2: Programming Xeon Phi""; ""Intel Xeon Phi Execution Models""; ""Development Tools for Intel Xeon Phi Architecture""; ""Intel Composer XE""; ""Getting the Tools""; ""Using the Compilers""; ""Setting Up an Intel Xeon Phi System""; ""Install the MPSS Stack""; ""Install the Development Tools""; ""Code Generation for Intel Xeon Phi Architecture""; ""Native Execution Mode""; ""Hello World Example"" ""Language Extensions to Support Offload Computation on Intel Xeon Phi""""Heterogeneous Computing Model and Offload Pragmas""; ""Language Extensions and Execution Model""; ""Terminology""; ""Offload Function and Data Declaration Directives""; ""declare target Directives""; ""Syntax""; ""C/C++""; ""Fortran""; ""Restrictions""; ""Function Offload and Execution Constructs""; ""Target Data Directive""; ""Syntax""; ""C/C++""; ""Fortran""; ""Restrictions""; ""Target Directive""; ""Syntax""; ""C/C++""; ""Fortran""; ""Restrictions""; ""Target Update Directive""; ""Syntax""; ""C/C++""; ""Fortran"" ""Runtime Library Routines""""Offload Example""; ""Summary""; ""Chapter 3: Xeon Phi Vector Architecture and Instruction Set""; ""Xeon Phi Vector Microarchitecture""; ""The VPU Pipeline""; ""VPU Instruction Stalls""; ""Pairing Rule""; ""Vector Registers""; ""Vector Mask Registers""; ""Extended Math Unit""; ""Xeon Phi Vector Instruction Set Architecture""; ""Data Types""; ""Vector Nomenclature""; ""Vector Instruction Syntax""; ""Xeon Phi Vector ISA by Categories""; ""Mask Operations""; ""Swizzle, Shuffle, Broadcast, and Convert Instructions""; ""Swizzle""; ""Register Memory Swizzle"" ""Data Broadcasts""""Data Conversions""; ""Shuffles""; ""Shift Operation""; ""Logical Shifts""; ""Arithmetic Shifts""; ""Sample Code for Swizzle and Shuffle Instructions""; ""Arithmetic and Logic Operations""; ""Fused Multiply-Add""; ""Data Access Operations (Load, Store, Prefetch, and Gather/Scatter)""; ""Memory Alignment""; ""Pack/ U npack""; ""Non-temporal data""; ""Streaming Stores""; ""Scatter/Gather""; ""Prefetch Instructions""; ""Summary""; ""Chapter 4: Xeon Phi Core Microarchitecture""; ""Intel Xeon Phi Cores""; ""Core Pipeline Stages""; ""Cache and TLB Structure"" ""L2 Cache Structure"" |
| Record Nr. | UNISA-996198793103316 |
Rahman Rezaur
|
||
| Apress, 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Intel Xeon Phi coprocessor architecture and tools : the guide for application developers / / Rezaur Rahman
| Intel Xeon Phi coprocessor architecture and tools : the guide for application developers / / Rezaur Rahman |
| Autore | Rahman Rezaur |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Apress, 2013 |
| Descrizione fisica | 1 online resource (xxi, 209 pages) : illustrations (some color) |
| Disciplina |
004
005.1 |
| Collana |
The expert's voice in microprocessors
Gale eBooks |
| Soggetto topico |
Coprocessors
Computer programming High performance computing |
| ISBN | 1-4302-5927-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
""Contents at a Glance""; ""Contents""; ""About the Author""; ""About the Technical Reviewer""; ""Acknowledgments""; ""Introduction""; ""Part1: Hardware Foundation: Intel Xeon Phi Architecture""; ""Chapter 1: Introduction to Xeon Phi Architecture""; ""History of Intel Xeon Phi Development""; ""Evolution from Von Neumann Architecture to Cache Subsystem Architecture""; ""Improvements in the Core and Memory""; ""Instruction-Level Parallelism""; ""Instruction Pipelining""; ""Single Instruction Multiple Data""; ""Multithreading""; ""Multicore and Manycore Architecture""
""Interconnect and Cache Improvements""""System Interconnect""; ""Intel Xeon Phi Coprocessor Chip Architecture""; ""Applicability of the Intel Xeon Phi Coprocessor""; ""Summary""; ""Chapter 2: Programming Xeon Phi""; ""Intel Xeon Phi Execution Models""; ""Development Tools for Intel Xeon Phi Architecture""; ""Intel Composer XE""; ""Getting the Tools""; ""Using the Compilers""; ""Setting Up an Intel Xeon Phi System""; ""Install the MPSS Stack""; ""Install the Development Tools""; ""Code Generation for Intel Xeon Phi Architecture""; ""Native Execution Mode""; ""Hello World Example"" ""Language Extensions to Support Offload Computation on Intel Xeon Phi""""Heterogeneous Computing Model and Offload Pragmas""; ""Language Extensions and Execution Model""; ""Terminology""; ""Offload Function and Data Declaration Directives""; ""declare target Directives""; ""Syntax""; ""C/C++""; ""Fortran""; ""Restrictions""; ""Function Offload and Execution Constructs""; ""Target Data Directive""; ""Syntax""; ""C/C++""; ""Fortran""; ""Restrictions""; ""Target Directive""; ""Syntax""; ""C/C++""; ""Fortran""; ""Restrictions""; ""Target Update Directive""; ""Syntax""; ""C/C++""; ""Fortran"" ""Runtime Library Routines""""Offload Example""; ""Summary""; ""Chapter 3: Xeon Phi Vector Architecture and Instruction Set""; ""Xeon Phi Vector Microarchitecture""; ""The VPU Pipeline""; ""VPU Instruction Stalls""; ""Pairing Rule""; ""Vector Registers""; ""Vector Mask Registers""; ""Extended Math Unit""; ""Xeon Phi Vector Instruction Set Architecture""; ""Data Types""; ""Vector Nomenclature""; ""Vector Instruction Syntax""; ""Xeon Phi Vector ISA by Categories""; ""Mask Operations""; ""Swizzle, Shuffle, Broadcast, and Convert Instructions""; ""Swizzle""; ""Register Memory Swizzle"" ""Data Broadcasts""""Data Conversions""; ""Shuffles""; ""Shift Operation""; ""Logical Shifts""; ""Arithmetic Shifts""; ""Sample Code for Swizzle and Shuffle Instructions""; ""Arithmetic and Logic Operations""; ""Fused Multiply-Add""; ""Data Access Operations (Load, Store, Prefetch, and Gather/Scatter)""; ""Memory Alignment""; ""Pack/ U npack""; ""Non-temporal data""; ""Streaming Stores""; ""Scatter/Gather""; ""Prefetch Instructions""; ""Summary""; ""Chapter 4: Xeon Phi Core Microarchitecture""; ""Intel Xeon Phi Cores""; ""Core Pipeline Stages""; ""Cache and TLB Structure"" ""L2 Cache Structure"" |
| Record Nr. | UNINA-9910293151803321 |
|
Rahman Rezaur
|
||
| Apress, 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||