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Fundamentals of digital logic and microcomputer design [[electronic resource] /] / M. Rafiquzzaman
| Fundamentals of digital logic and microcomputer design [[electronic resource] /] / M. Rafiquzzaman |
| Autore | Rafiquzzaman Mohamed |
| Edizione | [5th ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : J. Wiley & Sons, c2005 |
| Descrizione fisica | 1 online resource (842 p.) |
| Disciplina |
621.39/5
621.395 |
| Soggetto topico |
Logic circuits
Microcomputers - Design and construction Electronic digital computers - Circuits |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-27716-5
9786610277162 0-470-35893-9 0-471-73352-0 0-471-73349-0 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Fundamentals of Digital Logic and Microcomputer Design; Contents; PREFACE; 1. INTRODUCTION TO DIGITAL SYSTEMS; 1.1 Explanation of Terms; 1.2 Design Levels; 1.3 Combinational vs. Sequential Systems; 1.4 Digital Integrated Circuits; 1.4.1 Diodes; 1.4.2 Transistors; 1.4.3 MOS Transistors; 1.5 Integrated Circuits (ICs); 1.6 Evolution of Computers; 1.7 A Typical Microcomputer-Based Application; 1.8 Trends and Perspectives in Digital Technology; 2. NUMBER SYSTEMS AND CODES; 2.1 Number Systems; 2.1.1 General Number Representation; 2.1.2 Converting Numbers from One Base to Another
2.2 Unsigned and Signed Binary Numbers2.3 Codes; 2.3.1 Binary-Coded-Decimal Code (8421 Code); 2.3.2 Alphanumeric Codes; 2.3.3 Excess-3 Code; 2.3.4 Gray Code; 2.3.5 Unicode; 2.4 Fixed-Point and Floating-Point Representations; 2.5 Arithmetic Operations; 2.5.1 Binary Arithmetic; 2.5.2 BCD Arithmetic; 2.5.3 Multiword Binary Addition and Subtraction; 2.6 Error Correction and Detection; Questions and Problems; 3. BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES; 3.1 Basic Logic Operations; 3.1.1 NOT Operation; 3.1.2 OR Operation; 3.1.3 AND Operation; 3.2 Other Logic Operations; 3.2.1 NOR Operation 3.2.2 NAND Operation3.2.3 Exclusive-OR Operation (XOR); 3.2.4 Exclusive-NOR Operation (XNOR); 3.3 IEEE Symbols for Logic Gates; 3.4 Positive and Negative Logic; 3.5 Boolean Algebra; 3.5.1 Boolean Identities; 3.5.2 Simplification Using Boolean Identities; 3.5.3 Consensus Theorem; 3.5.4 Complement of a Boolean Function; 3.6 Standard Representations; 3.7 Karnaugh Maps; 3.7.1 Two-Variable K-Map; 3.7.2 Three-Variable K-Map; 3.7.3 Four-Variable K-Map; 3.7.4 Prime Implicants; 3.7.5 Expressing a Function in Product-of-Sums Form Using a K-Map; 3.7.6 Don't Care Conditions; 3.7.7 Five-Variable K-Map 3.8 Quine-McCluskey Method3.9 Implementation of Digital Circuits with NAND, NOR, and Exclusive-OR Exclusive-NOR Gates; 3.9.1 NAND Gate Implementation; 3.9.2 NOR Gate Implementation; 3.9.3 XOR / XNOR Implementations; Questions and Problems; 4. COMBINATIONAL LOGIC DESIGN; 4.1 Basic Concepts; 4.2 Analysis of a Combinational Logic Circuit; 4.3 Design of a Combinational Circuit; 4.4 Multiple-Output Combinational Circuits; 4.5 Typical Combinational Circuits; 4.5.1 Binary / BCD Adders and Binary Subtractors; 4.5.2 Comparators; 4.5.3 Decoders; 4.5.4 Encoders; 4.5.5 Multiplexers; 4.5.6 Demultiplexers 4.6 IEEE Standard Symbols4.7 Read-Only Memories (ROMs); 4.8 Programmable Logic Devices (PLDs); 4.9 Commercially Available Field Programmable Devices (FPDs); 4.10 Hardware Description Language (HDL); Questions and Problems; 5. SEQUENTIAL LOGIC DESIGN; 5.1 Basic Concepts; 5.2 Flip-Flops; 5.2.1 SR Latch; 5.2.2 RS Flip-Flop; 5.2.3 D Flip-Flop; 5.2.4 JK Flip-Flop; 5.2.5 T Flip-Flop; 5.3 Master-Slave Flip-Flop; 5.4 Preset and Clear Inputs; 5.5 Summary of Flip-Flops; 5.6 Analysis of Synchronous Sequential Circuits; 5.7 Types of Synchronous Sequential Circuits; 5.8 Minimization of States 5.9 Design of Synchronous Sequential Circuits |
| Record Nr. | UNINA-9910144578503321 |
Rafiquzzaman Mohamed
|
||
| Hoboken, N.J., : J. Wiley & Sons, c2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Fundamentals of digital logic and microcomputer design [[electronic resource] /] / M. Rafiquzzaman
| Fundamentals of digital logic and microcomputer design [[electronic resource] /] / M. Rafiquzzaman |
| Autore | Rafiquzzaman Mohamed |
| Edizione | [5th ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : J. Wiley & Sons, c2005 |
| Descrizione fisica | 1 online resource (842 p.) |
| Disciplina |
621.39/5
621.395 |
| Soggetto topico |
Logic circuits
Microcomputers - Design and construction Electronic digital computers - Circuits |
| ISBN |
1-280-27716-5
9786610277162 0-470-35893-9 0-471-73352-0 0-471-73349-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Fundamentals of Digital Logic and Microcomputer Design; Contents; PREFACE; 1. INTRODUCTION TO DIGITAL SYSTEMS; 1.1 Explanation of Terms; 1.2 Design Levels; 1.3 Combinational vs. Sequential Systems; 1.4 Digital Integrated Circuits; 1.4.1 Diodes; 1.4.2 Transistors; 1.4.3 MOS Transistors; 1.5 Integrated Circuits (ICs); 1.6 Evolution of Computers; 1.7 A Typical Microcomputer-Based Application; 1.8 Trends and Perspectives in Digital Technology; 2. NUMBER SYSTEMS AND CODES; 2.1 Number Systems; 2.1.1 General Number Representation; 2.1.2 Converting Numbers from One Base to Another
2.2 Unsigned and Signed Binary Numbers2.3 Codes; 2.3.1 Binary-Coded-Decimal Code (8421 Code); 2.3.2 Alphanumeric Codes; 2.3.3 Excess-3 Code; 2.3.4 Gray Code; 2.3.5 Unicode; 2.4 Fixed-Point and Floating-Point Representations; 2.5 Arithmetic Operations; 2.5.1 Binary Arithmetic; 2.5.2 BCD Arithmetic; 2.5.3 Multiword Binary Addition and Subtraction; 2.6 Error Correction and Detection; Questions and Problems; 3. BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES; 3.1 Basic Logic Operations; 3.1.1 NOT Operation; 3.1.2 OR Operation; 3.1.3 AND Operation; 3.2 Other Logic Operations; 3.2.1 NOR Operation 3.2.2 NAND Operation3.2.3 Exclusive-OR Operation (XOR); 3.2.4 Exclusive-NOR Operation (XNOR); 3.3 IEEE Symbols for Logic Gates; 3.4 Positive and Negative Logic; 3.5 Boolean Algebra; 3.5.1 Boolean Identities; 3.5.2 Simplification Using Boolean Identities; 3.5.3 Consensus Theorem; 3.5.4 Complement of a Boolean Function; 3.6 Standard Representations; 3.7 Karnaugh Maps; 3.7.1 Two-Variable K-Map; 3.7.2 Three-Variable K-Map; 3.7.3 Four-Variable K-Map; 3.7.4 Prime Implicants; 3.7.5 Expressing a Function in Product-of-Sums Form Using a K-Map; 3.7.6 Don't Care Conditions; 3.7.7 Five-Variable K-Map 3.8 Quine-McCluskey Method3.9 Implementation of Digital Circuits with NAND, NOR, and Exclusive-OR Exclusive-NOR Gates; 3.9.1 NAND Gate Implementation; 3.9.2 NOR Gate Implementation; 3.9.3 XOR / XNOR Implementations; Questions and Problems; 4. COMBINATIONAL LOGIC DESIGN; 4.1 Basic Concepts; 4.2 Analysis of a Combinational Logic Circuit; 4.3 Design of a Combinational Circuit; 4.4 Multiple-Output Combinational Circuits; 4.5 Typical Combinational Circuits; 4.5.1 Binary / BCD Adders and Binary Subtractors; 4.5.2 Comparators; 4.5.3 Decoders; 4.5.4 Encoders; 4.5.5 Multiplexers; 4.5.6 Demultiplexers 4.6 IEEE Standard Symbols4.7 Read-Only Memories (ROMs); 4.8 Programmable Logic Devices (PLDs); 4.9 Commercially Available Field Programmable Devices (FPDs); 4.10 Hardware Description Language (HDL); Questions and Problems; 5. SEQUENTIAL LOGIC DESIGN; 5.1 Basic Concepts; 5.2 Flip-Flops; 5.2.1 SR Latch; 5.2.2 RS Flip-Flop; 5.2.3 D Flip-Flop; 5.2.4 JK Flip-Flop; 5.2.5 T Flip-Flop; 5.3 Master-Slave Flip-Flop; 5.4 Preset and Clear Inputs; 5.5 Summary of Flip-Flops; 5.6 Analysis of Synchronous Sequential Circuits; 5.7 Types of Synchronous Sequential Circuits; 5.8 Minimization of States 5.9 Design of Synchronous Sequential Circuits |
| Record Nr. | UNINA-9910830681303321 |
|
Rafiquzzaman Mohamed
|
||
| Hoboken, N.J., : J. Wiley & Sons, c2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Fundamentals of digital logic and microcomputer design [[electronic resource] /] / M. Rafiquzzaman
| Fundamentals of digital logic and microcomputer design [[electronic resource] /] / M. Rafiquzzaman |
| Autore | Rafiquzzaman Mohamed |
| Edizione | [5th ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : J. Wiley & Sons, c2005 |
| Descrizione fisica | 1 online resource (842 p.) |
| Disciplina |
621.39/5
621.395 |
| Soggetto topico |
Logic circuits
Microcomputers - Design and construction Electronic digital computers - Circuits |
| ISBN |
1-280-27716-5
9786610277162 0-470-35893-9 0-471-73352-0 0-471-73349-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Fundamentals of Digital Logic and Microcomputer Design; Contents; PREFACE; 1. INTRODUCTION TO DIGITAL SYSTEMS; 1.1 Explanation of Terms; 1.2 Design Levels; 1.3 Combinational vs. Sequential Systems; 1.4 Digital Integrated Circuits; 1.4.1 Diodes; 1.4.2 Transistors; 1.4.3 MOS Transistors; 1.5 Integrated Circuits (ICs); 1.6 Evolution of Computers; 1.7 A Typical Microcomputer-Based Application; 1.8 Trends and Perspectives in Digital Technology; 2. NUMBER SYSTEMS AND CODES; 2.1 Number Systems; 2.1.1 General Number Representation; 2.1.2 Converting Numbers from One Base to Another
2.2 Unsigned and Signed Binary Numbers2.3 Codes; 2.3.1 Binary-Coded-Decimal Code (8421 Code); 2.3.2 Alphanumeric Codes; 2.3.3 Excess-3 Code; 2.3.4 Gray Code; 2.3.5 Unicode; 2.4 Fixed-Point and Floating-Point Representations; 2.5 Arithmetic Operations; 2.5.1 Binary Arithmetic; 2.5.2 BCD Arithmetic; 2.5.3 Multiword Binary Addition and Subtraction; 2.6 Error Correction and Detection; Questions and Problems; 3. BOOLEAN ALGEBRA AND DIGITAL LOGIC GATES; 3.1 Basic Logic Operations; 3.1.1 NOT Operation; 3.1.2 OR Operation; 3.1.3 AND Operation; 3.2 Other Logic Operations; 3.2.1 NOR Operation 3.2.2 NAND Operation3.2.3 Exclusive-OR Operation (XOR); 3.2.4 Exclusive-NOR Operation (XNOR); 3.3 IEEE Symbols for Logic Gates; 3.4 Positive and Negative Logic; 3.5 Boolean Algebra; 3.5.1 Boolean Identities; 3.5.2 Simplification Using Boolean Identities; 3.5.3 Consensus Theorem; 3.5.4 Complement of a Boolean Function; 3.6 Standard Representations; 3.7 Karnaugh Maps; 3.7.1 Two-Variable K-Map; 3.7.2 Three-Variable K-Map; 3.7.3 Four-Variable K-Map; 3.7.4 Prime Implicants; 3.7.5 Expressing a Function in Product-of-Sums Form Using a K-Map; 3.7.6 Don't Care Conditions; 3.7.7 Five-Variable K-Map 3.8 Quine-McCluskey Method3.9 Implementation of Digital Circuits with NAND, NOR, and Exclusive-OR Exclusive-NOR Gates; 3.9.1 NAND Gate Implementation; 3.9.2 NOR Gate Implementation; 3.9.3 XOR / XNOR Implementations; Questions and Problems; 4. COMBINATIONAL LOGIC DESIGN; 4.1 Basic Concepts; 4.2 Analysis of a Combinational Logic Circuit; 4.3 Design of a Combinational Circuit; 4.4 Multiple-Output Combinational Circuits; 4.5 Typical Combinational Circuits; 4.5.1 Binary / BCD Adders and Binary Subtractors; 4.5.2 Comparators; 4.5.3 Decoders; 4.5.4 Encoders; 4.5.5 Multiplexers; 4.5.6 Demultiplexers 4.6 IEEE Standard Symbols4.7 Read-Only Memories (ROMs); 4.8 Programmable Logic Devices (PLDs); 4.9 Commercially Available Field Programmable Devices (FPDs); 4.10 Hardware Description Language (HDL); Questions and Problems; 5. SEQUENTIAL LOGIC DESIGN; 5.1 Basic Concepts; 5.2 Flip-Flops; 5.2.1 SR Latch; 5.2.2 RS Flip-Flop; 5.2.3 D Flip-Flop; 5.2.4 JK Flip-Flop; 5.2.5 T Flip-Flop; 5.3 Master-Slave Flip-Flop; 5.4 Preset and Clear Inputs; 5.5 Summary of Flip-Flops; 5.6 Analysis of Synchronous Sequential Circuits; 5.7 Types of Synchronous Sequential Circuits; 5.8 Minimization of States 5.9 Design of Synchronous Sequential Circuits |
| Record Nr. | UNINA-9910841070303321 |
|
Rafiquzzaman Mohamed
|
||
| Hoboken, N.J., : J. Wiley & Sons, c2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Microprocessor theory and applications with 68000/68020 and Pentium [[electronic resource] /] / M. Rafiquzzaman
| Microprocessor theory and applications with 68000/68020 and Pentium [[electronic resource] /] / M. Rafiquzzaman |
| Autore | Rafiquzzaman Mohamed |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2008 |
| Descrizione fisica | 1 online resource (589 p.) |
| Disciplina |
004.165
005.136 005.265 |
| Soggetto topico |
Motorola 68000 series microprocessors
Pentium (Microprocessor) |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-93762-2
9786611937621 0-470-39139-1 0-470-39137-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Microprocessor Theory and Applications with 68000/68020 and Pentium; CONTENTS; PREFACE; CREDITS; 1. INTRODUCTION TO MICROPROCESSORS; 1.1 Explanation of Terms; 1.2 Microprocessor Data Types; 1.2.1 Unsigned and Signed Binary Numbers; 1.2.2 ASCII and EBCDIC Codes; 1.2.3 Unpacked and Packed Binary-Coded-Decimal Numbers; 1.2.4 Floating-point Numbers; 1.3 Evolution of the Microprocessor; 1.4 Typical Features of 32-bit and 64-bit Microprocessors; 1.5 Microprocessor-based System Design Concepts; 1.6 Typical Microprocessor Applications; 1.6.1 A Simple Microprocessor Application
1.6.2 Examples of Typical Microprocessor Applications2. MICROCOMPUTER ARCHITECTURE; 2.1 Basic Blocks of a Microcomputer; 2.2 Typical Microcomputer Architecture; 2.2.1 System Bus; 2.2.2 Clock Signals; 2.3 Single-Chip Microprocessor; 2.3.1 Register Section; 2.3.2 Control Unit; 2.3.3 Arithmetic-Logic Unit; 2.3.4 Functional Representations of Simple and Typical Microprocessors; 2.3.5 Simplified Explanation of Control Unit design; 2.4 Program Execution by Conventional Microprocessors; 2.5 Program Execution by typical 32-bit Microprocessors; 2.5.1 Pipelining; 2.5.2 Branch Prediction Feature 2.6 Scalar and Superscalar Microprocessors2.7 RISC vs. CISC; Questions and Problems; 3. MICROPROCESSOR MEMORY ORGANIZATION; 3.1 Introduction; 3.2 Main memory; 3.2.1 Read-Only Memory; 3.2.2 Random-Access Memory; 3.2.3 READ and WRITE Timing Diagrams; 3.2.4 Main Memory Organization; 3.2.5 Main Memory Array Design; 3.3 Microprocessor on-chip memory management unit and cache; 3.3.1 Memory Management Concepts; 3.3.2 Cache Memory Organization; Questions and Problems; 4. MICROPROCESSOR INPUT/OUTPUT; 4.1 Introduction; 4.2 Simple I/O Devices; 4.3 Programmed I/O 4.4 Unconditional and Conditional Programmed I/O4.5 Interrupt I/O; 4.5.1 Interrupt Types; 4.5.2 Interrupt Address Vector; 4.5.3 Saving the Microprocessor Registers; 4.5.4 Interrupt Priorities; 4.6 Direct Memory Access (DMA); 4.7 Summary of I/O; Questions and Problems; 5. MICROPROCESSOR PROGRAMMING CONCEPTS; 5.1 Microcomputer Programming Languages; 5.2 Machine Language; 5.3 Assembly Language; 5.3.1 Types of Assemblers; 5.3.2 Assembler Delimiters; 5.3.3 Specifying Numbers by Typical Assemblers; 5.3.4 Assembler Directives or Pseudoinstructions; 5.3.5 Assembly Language Instruction Formats 5.3.6 Instruction Set Architecture (ISA)5.3.7 Typical Instruction Set; 5.3.8 Typical Addressing Modes; 5.3.9 Subroutine Calls in Assembly Language; 5.4 High-Level Language; 5.5 Choosing a programming language; 5.6 Flowcharts; Questions and Problems; 6. ASSEMBLY LANGUAGE PROGRAMMING WITH THE 68000; 6.1 Introduction; 6.2 68000 Registers; 6.3 68000 Memory Addressing; 6.4 Assembly Language Programming with the 68000; 6.5 68000 Addressing Modes; 6.5.1 Register Direct Addressing; 6.5.2 Address Register Indirect Addressing; 6.5.3 Absolute Addressing; 6.5.4 Program Counter Relative Addressing 6.5.5 Immediate Data Addressing |
| Record Nr. | UNINA-9910144121403321 |
|
Rafiquzzaman Mohamed
|
||
| Hoboken, N.J., : Wiley, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Microprocessor theory and applications with 68000/68020 and Pentium [[electronic resource] /] / M. Rafiquzzaman
| Microprocessor theory and applications with 68000/68020 and Pentium [[electronic resource] /] / M. Rafiquzzaman |
| Autore | Rafiquzzaman Mohamed |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2008 |
| Descrizione fisica | 1 online resource (589 p.) |
| Disciplina |
004.165
005.136 005.265 |
| Soggetto topico |
Motorola 68000 series microprocessors
Pentium (Microprocessor) |
| ISBN |
1-281-93762-2
9786611937621 0-470-39139-1 0-470-39137-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Microprocessor Theory and Applications with 68000/68020 and Pentium; CONTENTS; PREFACE; CREDITS; 1. INTRODUCTION TO MICROPROCESSORS; 1.1 Explanation of Terms; 1.2 Microprocessor Data Types; 1.2.1 Unsigned and Signed Binary Numbers; 1.2.2 ASCII and EBCDIC Codes; 1.2.3 Unpacked and Packed Binary-Coded-Decimal Numbers; 1.2.4 Floating-point Numbers; 1.3 Evolution of the Microprocessor; 1.4 Typical Features of 32-bit and 64-bit Microprocessors; 1.5 Microprocessor-based System Design Concepts; 1.6 Typical Microprocessor Applications; 1.6.1 A Simple Microprocessor Application
1.6.2 Examples of Typical Microprocessor Applications2. MICROCOMPUTER ARCHITECTURE; 2.1 Basic Blocks of a Microcomputer; 2.2 Typical Microcomputer Architecture; 2.2.1 System Bus; 2.2.2 Clock Signals; 2.3 Single-Chip Microprocessor; 2.3.1 Register Section; 2.3.2 Control Unit; 2.3.3 Arithmetic-Logic Unit; 2.3.4 Functional Representations of Simple and Typical Microprocessors; 2.3.5 Simplified Explanation of Control Unit design; 2.4 Program Execution by Conventional Microprocessors; 2.5 Program Execution by typical 32-bit Microprocessors; 2.5.1 Pipelining; 2.5.2 Branch Prediction Feature 2.6 Scalar and Superscalar Microprocessors2.7 RISC vs. CISC; Questions and Problems; 3. MICROPROCESSOR MEMORY ORGANIZATION; 3.1 Introduction; 3.2 Main memory; 3.2.1 Read-Only Memory; 3.2.2 Random-Access Memory; 3.2.3 READ and WRITE Timing Diagrams; 3.2.4 Main Memory Organization; 3.2.5 Main Memory Array Design; 3.3 Microprocessor on-chip memory management unit and cache; 3.3.1 Memory Management Concepts; 3.3.2 Cache Memory Organization; Questions and Problems; 4. MICROPROCESSOR INPUT/OUTPUT; 4.1 Introduction; 4.2 Simple I/O Devices; 4.3 Programmed I/O 4.4 Unconditional and Conditional Programmed I/O4.5 Interrupt I/O; 4.5.1 Interrupt Types; 4.5.2 Interrupt Address Vector; 4.5.3 Saving the Microprocessor Registers; 4.5.4 Interrupt Priorities; 4.6 Direct Memory Access (DMA); 4.7 Summary of I/O; Questions and Problems; 5. MICROPROCESSOR PROGRAMMING CONCEPTS; 5.1 Microcomputer Programming Languages; 5.2 Machine Language; 5.3 Assembly Language; 5.3.1 Types of Assemblers; 5.3.2 Assembler Delimiters; 5.3.3 Specifying Numbers by Typical Assemblers; 5.3.4 Assembler Directives or Pseudoinstructions; 5.3.5 Assembly Language Instruction Formats 5.3.6 Instruction Set Architecture (ISA)5.3.7 Typical Instruction Set; 5.3.8 Typical Addressing Modes; 5.3.9 Subroutine Calls in Assembly Language; 5.4 High-Level Language; 5.5 Choosing a programming language; 5.6 Flowcharts; Questions and Problems; 6. ASSEMBLY LANGUAGE PROGRAMMING WITH THE 68000; 6.1 Introduction; 6.2 68000 Registers; 6.3 68000 Memory Addressing; 6.4 Assembly Language Programming with the 68000; 6.5 68000 Addressing Modes; 6.5.1 Register Direct Addressing; 6.5.2 Address Register Indirect Addressing; 6.5.3 Absolute Addressing; 6.5.4 Program Counter Relative Addressing 6.5.5 Immediate Data Addressing |
| Record Nr. | UNINA-9910830071503321 |
|
Rafiquzzaman Mohamed
|
||
| Hoboken, N.J., : Wiley, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Microprocessor theory and applications with 68000/68020 and Pentium [[electronic resource] /] / M. Rafiquzzaman
| Microprocessor theory and applications with 68000/68020 and Pentium [[electronic resource] /] / M. Rafiquzzaman |
| Autore | Rafiquzzaman Mohamed |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2008 |
| Descrizione fisica | 1 online resource (589 p.) |
| Disciplina |
004.165
005.136 005.265 |
| Soggetto topico |
Motorola 68000 series microprocessors
Pentium (Microprocessor) |
| ISBN |
1-281-93762-2
9786611937621 0-470-39139-1 0-470-39137-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Microprocessor Theory and Applications with 68000/68020 and Pentium; CONTENTS; PREFACE; CREDITS; 1. INTRODUCTION TO MICROPROCESSORS; 1.1 Explanation of Terms; 1.2 Microprocessor Data Types; 1.2.1 Unsigned and Signed Binary Numbers; 1.2.2 ASCII and EBCDIC Codes; 1.2.3 Unpacked and Packed Binary-Coded-Decimal Numbers; 1.2.4 Floating-point Numbers; 1.3 Evolution of the Microprocessor; 1.4 Typical Features of 32-bit and 64-bit Microprocessors; 1.5 Microprocessor-based System Design Concepts; 1.6 Typical Microprocessor Applications; 1.6.1 A Simple Microprocessor Application
1.6.2 Examples of Typical Microprocessor Applications2. MICROCOMPUTER ARCHITECTURE; 2.1 Basic Blocks of a Microcomputer; 2.2 Typical Microcomputer Architecture; 2.2.1 System Bus; 2.2.2 Clock Signals; 2.3 Single-Chip Microprocessor; 2.3.1 Register Section; 2.3.2 Control Unit; 2.3.3 Arithmetic-Logic Unit; 2.3.4 Functional Representations of Simple and Typical Microprocessors; 2.3.5 Simplified Explanation of Control Unit design; 2.4 Program Execution by Conventional Microprocessors; 2.5 Program Execution by typical 32-bit Microprocessors; 2.5.1 Pipelining; 2.5.2 Branch Prediction Feature 2.6 Scalar and Superscalar Microprocessors2.7 RISC vs. CISC; Questions and Problems; 3. MICROPROCESSOR MEMORY ORGANIZATION; 3.1 Introduction; 3.2 Main memory; 3.2.1 Read-Only Memory; 3.2.2 Random-Access Memory; 3.2.3 READ and WRITE Timing Diagrams; 3.2.4 Main Memory Organization; 3.2.5 Main Memory Array Design; 3.3 Microprocessor on-chip memory management unit and cache; 3.3.1 Memory Management Concepts; 3.3.2 Cache Memory Organization; Questions and Problems; 4. MICROPROCESSOR INPUT/OUTPUT; 4.1 Introduction; 4.2 Simple I/O Devices; 4.3 Programmed I/O 4.4 Unconditional and Conditional Programmed I/O4.5 Interrupt I/O; 4.5.1 Interrupt Types; 4.5.2 Interrupt Address Vector; 4.5.3 Saving the Microprocessor Registers; 4.5.4 Interrupt Priorities; 4.6 Direct Memory Access (DMA); 4.7 Summary of I/O; Questions and Problems; 5. MICROPROCESSOR PROGRAMMING CONCEPTS; 5.1 Microcomputer Programming Languages; 5.2 Machine Language; 5.3 Assembly Language; 5.3.1 Types of Assemblers; 5.3.2 Assembler Delimiters; 5.3.3 Specifying Numbers by Typical Assemblers; 5.3.4 Assembler Directives or Pseudoinstructions; 5.3.5 Assembly Language Instruction Formats 5.3.6 Instruction Set Architecture (ISA)5.3.7 Typical Instruction Set; 5.3.8 Typical Addressing Modes; 5.3.9 Subroutine Calls in Assembly Language; 5.4 High-Level Language; 5.5 Choosing a programming language; 5.6 Flowcharts; Questions and Problems; 6. ASSEMBLY LANGUAGE PROGRAMMING WITH THE 68000; 6.1 Introduction; 6.2 68000 Registers; 6.3 68000 Memory Addressing; 6.4 Assembly Language Programming with the 68000; 6.5 68000 Addressing Modes; 6.5.1 Register Direct Addressing; 6.5.2 Address Register Indirect Addressing; 6.5.3 Absolute Addressing; 6.5.4 Program Counter Relative Addressing 6.5.5 Immediate Data Addressing |
| Record Nr. | UNINA-9910840696803321 |
|
Rafiquzzaman Mohamed
|
||
| Hoboken, N.J., : Wiley, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||