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The Complexity of Simple Computer Architectures [[electronic resource] /] / edited by Silvia M. Müller, Wolfgang J. Paul
| The Complexity of Simple Computer Architectures [[electronic resource] /] / edited by Silvia M. Müller, Wolfgang J. Paul |
| Autore | Müller Silvia M |
| Edizione | [1st ed. 1995.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1995 |
| Descrizione fisica | 1 online resource (XII, 273 p.) |
| Disciplina | 004.2/2 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Microprogramming
Microprocessors Computer system failures Arithmetic and logic units, Computer Electronics Microelectronics Logic design Control Structures and Microprogramming Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Electronics and Microelectronics, Instrumentation Logic Design |
| ISBN | 3-540-47774-8 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | The formal architecture model -- Functional modules -- Hardwired control -- Design of a minimal CPU -- Design of the DLX machine -- Trade-off analyses -- Interrupt -- Microprogrammed control -- Further applications of the architecture model. |
| Record Nr. | UNISA-996466040903316 |
Müller Silvia M
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| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1995 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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A Pipelined Multi-Core Machine with Operating System Support [[electronic resource] ] : Hardware Implementation and Correctness Proof / / by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul
| A Pipelined Multi-Core Machine with Operating System Support [[electronic resource] ] : Hardware Implementation and Correctness Proof / / by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul |
| Autore | Lutsyk Petro |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (634 pages) |
| Disciplina | 005.434 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer programming
Computer engineering Computer networks Microprogramming Computer input-output equipment Logic programming Computer science Programming Techniques Computer Engineering and Networks Control Structures and Microprogramming Input/Output and Data Communications Logic in AI Theory of Computation |
| ISBN | 3-030-43243-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic. |
| Record Nr. | UNISA-996418302503316 |
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Lutsyk Petro
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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A Pipelined Multi-Core Machine with Operating System Support : Hardware Implementation and Correctness Proof / / by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul
| A Pipelined Multi-Core Machine with Operating System Support : Hardware Implementation and Correctness Proof / / by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul |
| Autore | Lutsyk Petro |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (634 pages) |
| Disciplina | 005.434 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer programming
Computer engineering Computer networks Microprogramming Computer input-output equipment Logic programming Computer science Programming Techniques Computer Engineering and Networks Control Structures and Microprogramming Input/Output and Data Communications Logic in AI Theory of Computation |
| ISBN | 3-030-43243-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic. |
| Record Nr. | UNINA-9910409666503321 |
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Lutsyk Petro
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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A Pipelined Multi-core MIPS Machine [[electronic resource] ] : Hardware Implementation and Correctness Proof / / by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
| A Pipelined Multi-core MIPS Machine [[electronic resource] ] : Hardware Implementation and Correctness Proof / / by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul |
| Autore | Kovalev Mikhail |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2014 |
| Descrizione fisica | 1 online resource (XII, 352 p. 147 illus.) |
| Disciplina | 004.165 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Algorithms
Software engineering Computers Microprocessors Computer architecture Computer networks Compilers (Computer programs) Software Engineering Computer Hardware Processor Architectures Computer Communication Networks Compilers and Interpreters |
| ISBN | 3-319-13906-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Motivation -- Overview -- Number Formats and Boolean Algebra -- Basics -- Numbers, Sets and Logical Connectives -- Sequences and Bit-Strings -- Modulo Computation -- Geometric Sums -- Binary Numbers -- Two’s Complement Numbers -- Boolean Algebra -- Identities -- Solving Equations -- Disjunctive Normal Form -- Hardware -- Digital Gates and Circuits -- Some Basic Circuits -- Clocked Circuits -- Digital Clocked Circuits -- The Detailed Hardware Model -- Timing Analysis -- Registers -- Drivers and Main Memory -- Open Collector Drivers and Active Low Signal -- Tristate Drivers and Bus Contention -- The Incomplete Digital Model for Drivers -- Self Destructing Hardware -- Clean Operation of Tristate Buses -- Specification of Main Memory -- Operation of Main Memory via a Tristate Bus -- Finite State Transducers -- Realization of Moore Automata -- Precomputing Outputs of Moore Automata -- Realization of Mealy Automata -- Precomputing Outputs of Mealy Automata -- Nine Shades of RAM -- Basic Random Access Memory -- Single-Port RAM Designs -- Read Only Memory (ROM) -- Multi-bank RAM -- Cache State RAM -- SPR RAM -- Multi-port RAM Designs -- 3-port RAM for General Purpose Registers -- General 2-port RAM -- 2-port Multi-bank RAM-ROM -- 2-port Cache State RAM -- Arithmetic Circuits -- Adder and Incrementer -- Arithmetic Unit -- Arithmetic Logic Unit (ALU) -- Shift Unit -- Branch Condition Evaluation Unit -- A Basic Sequential MIPS Machine -- Tables -- I-type -- R-type -- J-type -- MIPS ISA -- Configuration and Instruction Fields -- Instruction Decoding -- ALU-Operations -- Shift Unit Operations -- Branch and Jump -- Sequences of Consecutive Memory Bytes -- Loads and Stores -- ISA Summary -- A Sequential Processor Design -- Software Conditions -- Hardware Configurations and Computations -- Memory Embedding -- Defining Correctness for the Processor Design -- Stages of Instruction Execution -- Initialization -- Instruction Fetch -- Instruction Decoder -- Reading from General Purpose Registers -- Next PC Environment -- ALU Environment -- Shift Unit Environment -- Jump and Link -- Collecting Results -- Effective Address -- Shift for Store Environment -- Memory Stage -- Shifter for Load -- Writing to the General Purpose Register File -- Pipelining.-MIPS ISA and Basic Implementation Revisited -- Delayed PC -- Implementing the Delayed PC -- Pipeline Stages and Visible Registers -- Basic Pipelined Processor Design -- Transforming the Sequential Design -- Scheduling Functions -- Use of Invisible Registers -- Software Condition SC-1 -- Correctness Statement -- Correctness Proof of the Basic Pipelined Design -- Forwarding -- Hits -- Forwarding Circuits -- Software Condition SC-2 -- Scheduling Functions Revisited -- Correctness Proof -- Stalling Stall Engine -- Hazard Signals -- Correctness Statement -- Scheduling Functions -- Correctness Proof -- Liveness -- Caches and Shared Memory -- Concrete and Abstract Caches -- Abstract Caches and Cache Coherence -- Direct Mapped Caches -- k-way Associative Caches -- Fully Associative Caches -- Notation -- Parameters -- Memory and Memory Systems -- Accesses and Access Sequences -- Sequential Memory Semantics -- Sequentially Consistent Memory Systems -- Memory System Hardware Configurations -- Atomic MOESI Protocol -- Invariants -- Defining the Protocol by Tables -- Translating the Tables into Switching Functions -- Algebraic Specification -- Properties of the Atomic Protocol -- Gate Level Design of a Shared Memory System -- Specification of Interfaces -- Data Paths of Caches -- Cache Protocol Automata -- Automata Transitions and Control Signals -- Bus Arbiter -- Initialization -- Correctness Proof -- Arbitration -- Silent Slaves and Silent Masters -- Automata Synchronization -- Control of Tristate Drivers -- Protocol Data Transmission -- Data Transmission -- Accesses of the Hardware Computation -- Relation with the Atomic Protocol -- Ordering Hardware Accesses Sequentially -- Sequential Consistency -- Liveness -- A Multi-core Processor -- Compare-and-Swap Instruction -- Introducing CAS to the ISA -- Introducing CAS to the Sequential Processor -- Multi-core ISA and Reference Implementation -- Multi-core ISA Specification -- Sequential Reference Implementation -- Simulation Relation -- Local Configurations and Computations -- Accesses of the Reference Computation -- Shared Memory in the Multi-core System -- Notation -- Invisible Registers and Hazard Signals -- Connecting Interfaces -- Stability of Inputs of Accesses -- Relating Update Enable Signals and Ends of Accesses -- Scheduling Functions -- Stepping Function -- Correctness Proof -- Liveness -- References -- Index. |
| Record Nr. | UNISA-996210512703316 |
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Kovalev Mikhail
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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A Pipelined Multi-core MIPS Machine : Hardware Implementation and Correctness Proof / / by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
| A Pipelined Multi-core MIPS Machine : Hardware Implementation and Correctness Proof / / by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul |
| Autore | Kovalev Mikhail |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2014 |
| Descrizione fisica | 1 online resource (XII, 352 p. 147 illus.) |
| Disciplina | 004.165 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Algorithms
Software engineering Computers Microprocessors Computer architecture Computer networks Compilers (Computer programs) Software Engineering Computer Hardware Processor Architectures Computer Communication Networks Compilers and Interpreters |
| ISBN | 3-319-13906-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Motivation -- Overview -- Number Formats and Boolean Algebra -- Basics -- Numbers, Sets and Logical Connectives -- Sequences and Bit-Strings -- Modulo Computation -- Geometric Sums -- Binary Numbers -- Two’s Complement Numbers -- Boolean Algebra -- Identities -- Solving Equations -- Disjunctive Normal Form -- Hardware -- Digital Gates and Circuits -- Some Basic Circuits -- Clocked Circuits -- Digital Clocked Circuits -- The Detailed Hardware Model -- Timing Analysis -- Registers -- Drivers and Main Memory -- Open Collector Drivers and Active Low Signal -- Tristate Drivers and Bus Contention -- The Incomplete Digital Model for Drivers -- Self Destructing Hardware -- Clean Operation of Tristate Buses -- Specification of Main Memory -- Operation of Main Memory via a Tristate Bus -- Finite State Transducers -- Realization of Moore Automata -- Precomputing Outputs of Moore Automata -- Realization of Mealy Automata -- Precomputing Outputs of Mealy Automata -- Nine Shades of RAM -- Basic Random Access Memory -- Single-Port RAM Designs -- Read Only Memory (ROM) -- Multi-bank RAM -- Cache State RAM -- SPR RAM -- Multi-port RAM Designs -- 3-port RAM for General Purpose Registers -- General 2-port RAM -- 2-port Multi-bank RAM-ROM -- 2-port Cache State RAM -- Arithmetic Circuits -- Adder and Incrementer -- Arithmetic Unit -- Arithmetic Logic Unit (ALU) -- Shift Unit -- Branch Condition Evaluation Unit -- A Basic Sequential MIPS Machine -- Tables -- I-type -- R-type -- J-type -- MIPS ISA -- Configuration and Instruction Fields -- Instruction Decoding -- ALU-Operations -- Shift Unit Operations -- Branch and Jump -- Sequences of Consecutive Memory Bytes -- Loads and Stores -- ISA Summary -- A Sequential Processor Design -- Software Conditions -- Hardware Configurations and Computations -- Memory Embedding -- Defining Correctness for the Processor Design -- Stages of Instruction Execution -- Initialization -- Instruction Fetch -- Instruction Decoder -- Reading from General Purpose Registers -- Next PC Environment -- ALU Environment -- Shift Unit Environment -- Jump and Link -- Collecting Results -- Effective Address -- Shift for Store Environment -- Memory Stage -- Shifter for Load -- Writing to the General Purpose Register File -- Pipelining.-MIPS ISA and Basic Implementation Revisited -- Delayed PC -- Implementing the Delayed PC -- Pipeline Stages and Visible Registers -- Basic Pipelined Processor Design -- Transforming the Sequential Design -- Scheduling Functions -- Use of Invisible Registers -- Software Condition SC-1 -- Correctness Statement -- Correctness Proof of the Basic Pipelined Design -- Forwarding -- Hits -- Forwarding Circuits -- Software Condition SC-2 -- Scheduling Functions Revisited -- Correctness Proof -- Stalling Stall Engine -- Hazard Signals -- Correctness Statement -- Scheduling Functions -- Correctness Proof -- Liveness -- Caches and Shared Memory -- Concrete and Abstract Caches -- Abstract Caches and Cache Coherence -- Direct Mapped Caches -- k-way Associative Caches -- Fully Associative Caches -- Notation -- Parameters -- Memory and Memory Systems -- Accesses and Access Sequences -- Sequential Memory Semantics -- Sequentially Consistent Memory Systems -- Memory System Hardware Configurations -- Atomic MOESI Protocol -- Invariants -- Defining the Protocol by Tables -- Translating the Tables into Switching Functions -- Algebraic Specification -- Properties of the Atomic Protocol -- Gate Level Design of a Shared Memory System -- Specification of Interfaces -- Data Paths of Caches -- Cache Protocol Automata -- Automata Transitions and Control Signals -- Bus Arbiter -- Initialization -- Correctness Proof -- Arbitration -- Silent Slaves and Silent Masters -- Automata Synchronization -- Control of Tristate Drivers -- Protocol Data Transmission -- Data Transmission -- Accesses of the Hardware Computation -- Relation with the Atomic Protocol -- Ordering Hardware Accesses Sequentially -- Sequential Consistency -- Liveness -- A Multi-core Processor -- Compare-and-Swap Instruction -- Introducing CAS to the ISA -- Introducing CAS to the Sequential Processor -- Multi-core ISA and Reference Implementation -- Multi-core ISA Specification -- Sequential Reference Implementation -- Simulation Relation -- Local Configurations and Computations -- Accesses of the Reference Computation -- Shared Memory in the Multi-core System -- Notation -- Invisible Registers and Hazard Signals -- Connecting Interfaces -- Stability of Inputs of Accesses -- Relating Update Enable Signals and Ends of Accesses -- Scheduling Functions -- Stepping Function -- Correctness Proof -- Liveness -- References -- Index. |
| Record Nr. | UNINA-9910483387903321 |
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Kovalev Mikhail
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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