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Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing : Use Cases and Emerging Challenges / / edited by Sudeep Pasricha, Muhammad Shafique
| Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing : Use Cases and Emerging Challenges / / edited by Sudeep Pasricha, Muhammad Shafique |
| Autore | Pasricha Sudeep |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (571 pages) |
| Disciplina | 006.22 |
| Altri autori (Persone) | ShafiqueMuhammad |
| Soggetto topico |
Embedded computer systems
Electronic circuits Cooperating objects (Computer systems) Embedded Systems Electronic Circuits and Systems Cyber-Physical Systems |
| ISBN |
9783031406775
303140677X |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910760256003321 |
Pasricha Sudeep
|
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| Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing : Software Optimizations and Hardware/Software Codesign / / edited by Sudeep Pasricha, Muhammad Shafique
| Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing : Software Optimizations and Hardware/Software Codesign / / edited by Sudeep Pasricha, Muhammad Shafique |
| Autore | Pasricha Sudeep |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (481 pages) |
| Disciplina | 006.22 |
| Altri autori (Persone) | ShafiqueMuhammad |
| Soggetto topico |
Embedded computer systems
Electronic circuits Cooperating objects (Computer systems) Embedded Systems Electronic Circuits and Systems Cyber-Physical Systems |
| ISBN |
9783031399329
3031399323 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Acknowledgments -- Contents -- Part I Efficient Software Design for Embedded Machine Learning -- Machine Learning Model Compression for Efficient Indoor Localization on Embedded Platforms -- 1 Introduction -- 2 Background and Related Work -- 3 CHISEL Framework -- 3.1 Data Preprocessing and Augmentation -- 3.2 Network Architecture -- 3.3 Model Compression -- 4 Experiments -- 4.1 Evaluation on UJIIndoorLoc Dataset -- 4.2 Evaluation on Compression-Aware Training -- 5 Conclusion -- References -- A Design Methodology for Energy-Efficient Embedded Spiking Neural Networks -- 1 Introduction -- 1.1 Overview -- 1.2 Design Constraints for Embedded SNNs -- 2 Preliminaries -- 2.1 Spiking Neural Networks (SNNs) -- 2.2 Spike-Timing-Dependent Plasticity (STDP) -- 3 A Design Methodology for Embedded SNNs -- 3.1 Overview -- 3.2 Reduction of SNN Operations -- 3.3 Learning Enhancements -- 3.4 Weight Quantization -- 3.5 Evaluation of Memory and Energy Requirements -- 3.6 Employment of Approximate DRAM -- 4 Experimental Evaluations -- 4.1 Classification Accuracy -- 4.2 Reduction of Memory Requirement -- 4.3 Improvement of Energy Efficiency -- 4.4 Impact of Approximate DRAM -- 5 Conclusion -- References -- Compilation and Optimizations for Efficient Machine Learning on Embedded Systems -- 1 Introduction -- 2 Background and Related Works -- 2.1 Efficient DNN Designs -- 2.2 Efficient Accelerator Designs and DNN Mapping Methods -- 2.3 Efficient Co-Design Optimization -- 3 Efficient Machine Learning Model Designs -- 3.1 The ELB-NN -- 3.1.1 Hybrid Quantization Scheme -- 3.1.2 Hardware Accelerator for ELB-NN -- 3.2 The VecQ -- 3.2.1 Quantization with Vector Loss -- 3.2.2 Framework Integration -- 4 Efficient Accelerator Design and Workload Mapping -- 4.1 DNNBuilder -- 4.1.1 An End-to-end Automation Flow -- 4.1.2 Architecture Novelties.
4.1.3 State-of-the-art Performance -- 4.2 PyLog: A Python-Based FPGA Programming Flow -- 4.2.1 PyLog Flow Overview -- 4.2.2 PyLog Features -- 4.2.3 PyLog Evaluation Results -- 5 Efficient Optimizations -- 5.1 Overview of Hardware-aware Neural Architecture Search (NAS) -- 5.2 HW-Aware NAS Formulation -- 5.3 FPGA/DNN Co-Design -- 5.3.1 The Key to Co-Design: Bundle -- 5.3.2 Progressively Reducing Search Space -- 5.3.3 Evaluation Results -- 5.4 EDD: Efficient Differential DNN Architecture Search -- 5.4.1 Fused Co-Design Space -- 5.4.2 Differentiable Performance and Resource Formulation -- 5.4.3 State-of-the-art Results -- 6 Conclusion -- References -- A Pedestrian Detection Case Study for a Traffic Light Controller -- 1 Introduction -- 2 Related Work -- 2.1 Neural Networks for Pedestrian Detection -- 2.2 Pedestrian Detection on Embedded Systems -- 2.3 Quantization -- 3 Pedestrian Detection Use Case -- 4 Results -- 4.1 Experimentation Setup -- 4.2 No Constraints -- 4.3 Cost Constraints -- 4.4 Cost, Latency, and Precision Constraints -- 4.5 Effect of Resolution and Quantization -- 5 Conclusion -- References -- How to Train Accurate BNNs for Embedded Systems? -- 1 Introduction -- 2 Related Work -- 3 Background on BNNs -- 3.1 Inference -- 3.2 Training -- 4 Classification of Accuracy Repair Techniques -- 5 Overview of Accuracy Repair Techniques as Applied in the Literature -- 5.1 Training Techniques -- 5.1.1 Binarizer (STE) -- 5.1.2 Normalization -- 5.1.3 Teacher-Student -- 5.1.4 Regularization -- 5.1.5 Two-Stage Training -- 5.1.6 Optimizer -- 5.2 Network Topology Changing -- 5.2.1 Scaling Factor -- 5.2.2 Ensemble -- 5.2.3 Activation Function -- 5.2.4 Double Residual -- 5.2.5 Squeeze-and-Excitation -- 6 Empirical Review of Accuracy Repair Methods -- 6.1 Establishing the Design Space -- 6.2 Finding a Good Baseline BNN -- 6.3 Design Space Exploration. 6.3.1 Binarizer (STE) -- 6.3.2 Normalization -- 6.3.3 Scaling Factor -- 6.3.4 Two-Stage Training, Activation Function, and Double Residual -- 7 Discussion and Future Research -- 7.1 Accuracy Gap -- 7.2 Benefit and Cost of BNNs -- 8 Conclusion -- References -- Embedded Neuromorphic Using Intel's Loihi Processor -- 1 Introduction -- 2 Brain-Inspired Spiking Neural Networks -- 2.1 Spiking Neuron Models -- 2.2 Spike Coding Methods -- 2.3 SNN Learning Methods -- 3 Conventional Architectures vs. Neuromorphic Architectures -- 4 Event-Based Cameras -- 5 Applications and Datasets for Event-Based SNNs -- 6 The Loihi Architecture -- 6.1 Neuron Model -- 6.2 Chip Architecture -- 6.3 Second Generation: Loihi 2 -- 6.4 Tools to Support Loihi Developers -- 6.5 SOTA Results of Event-Based SNNs on Loihi -- 7 Case Study for Autonomous Vehicles: Car Detection with CarSNN -- 7.1 Problem Analysis and General Design Decisions -- 7.2 CarSNN Methodology -- 7.2.1 CarSNN Model Design -- 7.2.2 Parameters for Training -- 7.2.3 Parameters for Feeding the Input Data -- 7.3 Evaluation of CarSNN Implemented on Loihi -- 7.3.1 Experimental Setup -- 7.3.2 Accuracy Results for Offline Trained CarSNN -- 7.3.3 CarSNN Implemented on Loihi -- 7.3.4 Comparison with the State of the Art -- 8 Conclusion -- References -- Part II Hardware-Software Co-Design and Co-Optimizations for Embedded Machine Learning -- Machine Learning for Heterogeneous Manycore Design -- 1 Introduction -- 2 ML-Enabled 3D CPU/GPU-Based Heterogeneous Manycore Design -- 2.1 Related Prior Work -- 2.1.1 3D Heterogeneous Manycore Systems -- 2.1.2 Multi-Objective Optimization Algorithms -- 3 3D Heterogeneous Manycore Design Formulation -- 4 MOO-STAGE: ML-Enabled Manycore Design Framework -- 4.1 MOO-STAGE: Local Search -- 4.2 MOO-STAGE: Meta Search -- 5 Experimental Results -- 5.1 Experimental Setup. 5.2 Comparing the Different Algorithms -- 5.3 Comparison with Mesh NoC-Based Heterogeneous Manycore System -- 6 MOO-STAGE FOR M3D-Based Manycore Systems -- 6.1 MOO-STAGE for M3D Design -- 7 Conclusion -- References -- Hardware-Software Co-design for Ultra-Resource-Constrained Embedded Machine Learning Inference: A Printed Electronics Use Case -- 1 Introduction -- 2 Background on Printed Electronics -- 3 Preliminaries -- 4 Bespoke ML Classification Circuits -- 4.1 Resource-Aware ML Algorithm Selection -- 4.2 Bespoke Classifier Implementation -- 5 Co-Design for Approximate ML Classification Circuits -- 5.1 Approximate MLPs and SVMs -- 5.2 Approximate Decision Trees -- 6 Co-design for Stochastic Neural Network Circuits -- 6.1 Mixed-Signal Stochastic Neuron -- 6.2 Analog Stochastic SNG -- 6.3 Analog Stochastic Activation Function -- 6.4 Hardware-Driven Training -- 6.5 Mixed-Signal Stochastic Inference -- 7 Conclusion -- References -- Cross-Layer Optimizations for Efficient Deep Learning Inference at the Edge -- 1 Introduction -- 2 Preliminaries -- 3 DNN Optimization Techniques -- 3.1 Pruning -- 3.1.1 Fine-Grained Pruning -- 3.1.2 Course-Grained Pruning -- 3.2 Quantization -- 3.3 Knowledge Distillation -- 3.4 Neural Architecture Search -- 3.5 Hardware Approximations -- 4 Cross-Layer Optimization -- 4.1 Methodology -- 4.2 Structured Pruning -- 4.3 Quantization -- 4.4 Hardware-Level Approximations: Impact of Self-Healing and Non-Self-Healing Approximate Designs on DNN Accuracy -- 5 End-to-End System-Level Approximations -- 6 Conclusion -- References -- Co-designing Photonic Accelerators for Machine Learningon the Edge -- 1 Introduction -- 2 Background and Related Work -- 3 Noncoherent Photonic Computation Overview -- 4 CrossLight Architecture -- 4.1 MR Device Engineering and Fabrication -- 4.2 Tuning Circuit Design -- 4.3 Architecture Design. 4.3.1 Decomposing Vector Operations in CONV/FC Layers -- 4.3.2 Vector Dot Product (VDP) Unit Design -- 4.3.3 Optical Wavelength Reuse in VDP Units -- 5 Evaluation and Simulation Results -- 5.1 Simulation Setup -- 5.2 Results: CrossLight Resolution Analysis -- 5.3 Results: CrossLight Sensitivity Analysis -- 5.4 Results: Comparison with State-of-the-Art Accelerators -- 6 Conclusion -- References -- Hardware-Software Co-design of Deep Neural Architectures: From FPGAs and ASICs to Computing-in-Memories -- 1 Introduction -- 2 Hardware-Software Co-design with Neural Architecture Search -- 3 Hardware-Aware Neural Architecture Search for FPGA -- 3.1 Implementation of DNNs on FPGAs -- 3.2 Co-design Framework for FPGAs -- 3.2.1 Problem Statement and Solution -- 3.3 Experiments -- 3.3.1 Search Space Setup -- 3.4 Comparison Results with the Existing NAS Frameworks -- 3.5 Comparison Results with the Existing Architectures -- 3.6 Importance of Co-exploration -- 3.7 Concluding Remarks for NAS-F -- 4 Co-design of Neural Networks and ASICs -- 4.1 Problem Analysis for DNN-ASIC Co-design -- 4.1.1 Major Components -- 4.1.2 Problem Definition -- 4.2 Co-design Framework for ASIC -- 4.3 Experimental Evaluation -- 4.3.1 Evaluation Environment -- 4.4 Design Space Exploration -- 4.4.1 Results on Multiple Tasks for Multiple Datasets -- 4.5 Concluding Remarks for NASAIC -- 5 Co-design of Neural Networks and Computing-in-Memory Accelerators -- 5.1 Compute-in-Memory Neural Accelerators -- 5.1.1 Device and Its Variations -- 5.1.2 Crossbar Architecture -- 5.1.3 NeuroSIM -- 5.2 Problem Definition -- 5.3 Co-design Framework for CiM -- 5.4 Experiments and Results -- 5.4.1 Experiment Setup -- 5.4.2 Comparison Results to State-of-the-Art NAS -- 5.4.3 Results of Multi-Objective Optimization -- 5.5 Concluding Remarks for NACIM -- 6 Conclusions -- References. Hardware and Software Optimizations for Capsule Networks. |
| Record Nr. | UNINA-9910760275803321 |
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Pasricha Sudeep
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| Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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On-chip communication architectures : system on chip interconnect / / Sudeep Pasricha, Nikil Dutt
| On-chip communication architectures : system on chip interconnect / / Sudeep Pasricha, Nikil Dutt |
| Autore | Pasricha Sudeep |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier / Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (541 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) | DuttNikil |
| Collana | Systems on Silicon |
| Soggetto topico |
Systems on a chip
Microcomputers - Buses Computer architecture Interconnects (Integrated circuit technology) |
| ISBN |
9786611370947
9781281370945 1281370940 9780080558288 0080558283 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; On-Chip Communication Architectures: System on Chip Interconnect; Copyright Page; Contents; Preface; About the Authors; Acknowledgments; List of Contributors; CHAPTER 1 Introduction; 1.1. Trends in System-On-Chip Design; 1.2. Coping with Soc Design Complexity; 1.3. ESL Design Flow; 1.4. On-Chip Communication Architectures: A Quick Look; 1.5. Book Outline; CHAPTER 2 Basic Concepts of Bus-Based Communication Architectures; 2.1. Terminology; 2.2. Characteristics of Bus-Based Communication Architectures; 2.3. Data Transfer Modes; 2.4. Bus Topology Types
2.5. Physical Implementation of Bus Wires2.6. Discussion: Buses in the DSM Era; 2.7. Summary; CHAPTER 3 On-Chip Communication Architecture Standards; 3.1. Standard On-Chip Bus-Based Communication Architectures; 3.2. Socket-Based On-Chip Bus Interface Standards; 3.3. Discussion: Off-Chip Bus Architecture Standards; 3.4. Summary; CHAPTER 4 Models for Performance Exploration; 4.1. Static Performance Estimation Models; 4.2. Dynamic (Simulation-Based) Performance Estimation Models; 4.3. Hybrid Communication Architecture Performance Estimation Approaches; 4.4. Summary CHAPTER 5 Models for Power and Thermal Estimation5.1. Bus Wire Power Models; 5.2. Comprehensive Bus Architecture Power Models; 5.3. Bus Wire Thermal Models; 5.4. Discussion: PVT Variation-Aware Power Estimation; 5.5. Summary; CHAPTER 6 Synthesis of On-Chip Communication Architectures; 6.1. Bus Topology Synthesis; 6.2. Bus Protocol Parameter Synthesis; 6.3. Bus Topology and Protocol Parameter Synthesis; 6.4. Physical Implementation Aware Synthesis; 6.5. Memory-Communication Architecture Co-synthesis; 6.6. Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures 6.7. SummaryCHAPTER 7 Encoding Techniques for On-Chip Communication Architectures; 7.1. Techniques for Power Reduction; 7.2. Techniques for Reducing Capacitive Crosstalk Delay; 7.3. Techniques for Reducing Power and Capacitive Crosstalk Effects; 7.4. Techniques for Reducing Inductive Crosstalk Effects; 7.5. Techniques for Fault Tolerance and Reliability; 7.6. Summary; CHAPTER 8 Custom Bus-Based On-Chip Communication Architecture Design; 8.1. Split Bus Architectures; 8.2. Serial Bus Architectures; 8.3. CDMA-Based Bus Architectures; 8.4. Asynchronous Bus Architectures 8.5. Dynamically Reconfigurable Bus Architectures8.6. Summary; CHAPTER 9 On-Chip Communication Architecture Refinement and Interface Synthesis; 9.1. On-Chip Communication Architecture Refinement; 9.2. Interface Synthesis; 9.3. Discussion: Interface Synthesis; 9.4. Summary; CHAPTER 10 Verification and Security Issues in On-Chip Communication Architecture Design; 10.1. Verification of On-Chip Communication Protocols; 10.2. Compliance Verification for IP Block Integration; 10.3. Basic Concepts of SoC Security; 10.4. Security Support in Standard Bus Protocols 10.5. Communication Architecture Enhancements for Improving SoC Security |
| Record Nr. | UNINA-9911006627103321 |
|
Pasricha Sudeep
|
||
| Amsterdam ; ; Boston, : Elsevier / Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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