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Intelligent Memory Systems [[electronic resource] ] : Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000. Revised Papers / / edited by Frederic T. Chong, Christoforos Kozyrakis, Mark Oskin
| Intelligent Memory Systems [[electronic resource] ] : Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000. Revised Papers / / edited by Frederic T. Chong, Christoforos Kozyrakis, Mark Oskin |
| Edizione | [1st ed. 2001.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 |
| Descrizione fisica | 1 online resource (VIII, 200 p.) |
| Disciplina | 005.4/35 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Artificial intelligence
Computer engineering Computer memory systems Computer organization Operating systems (Computers) Computer logic Artificial Intelligence Computer Engineering Memory Structures Computer Systems Organization and Communication Networks Operating Systems Logics and Meanings of Programs |
| ISBN | 3-540-44570-6 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Memory Technology -- A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro -- Software Controlled Reconfigurable On-chip Memory for High Performance Computing -- Processor and Memory Architecture -- Content-Based Prefetching: Initial Results -- Memory System Support for Dynamic Cache Line Assembly -- Adaptively Mapping Code in an Intelligent Memory Architecture -- Applications and Operating Systems -- The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems? -- Memory Management in a PIM-Based Architecture -- Compiler Technology -- Exploiting On-chip Memory Bandwidth in the VIRAM Compiler -- FlexCache: A Framework for Flexible Compiler Generated Data Caching -- Poster Session -- Aggressive Memory-Aware Compilation -- Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips? -- SAGE: A New Analysis and Optimization System for FlexRAM Architecture -- Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems -- The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems -- Compiler-Directed Cache Line Size Adaptivity ? -- Summary of Question/Answer Sessions for Workshop Presentations. |
| Record Nr. | UNISA-996465783103316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Intelligent Memory Systems : Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000. Revised Papers / / edited by Frederic T. Chong, Christoforos Kozyrakis, Mark Oskin
| Intelligent Memory Systems : Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000. Revised Papers / / edited by Frederic T. Chong, Christoforos Kozyrakis, Mark Oskin |
| Edizione | [1st ed. 2001.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 |
| Descrizione fisica | 1 online resource (VIII, 200 p.) |
| Disciplina | 005.4/35 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Artificial intelligence
Computer engineering Computer memory systems Computer organization Operating systems (Computers) Computer logic Artificial Intelligence Computer Engineering Memory Structures Computer Systems Organization and Communication Networks Operating Systems Logics and Meanings of Programs |
| ISBN | 3-540-44570-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Memory Technology -- A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro -- Software Controlled Reconfigurable On-chip Memory for High Performance Computing -- Processor and Memory Architecture -- Content-Based Prefetching: Initial Results -- Memory System Support for Dynamic Cache Line Assembly -- Adaptively Mapping Code in an Intelligent Memory Architecture -- Applications and Operating Systems -- The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems? -- Memory Management in a PIM-Based Architecture -- Compiler Technology -- Exploiting On-chip Memory Bandwidth in the VIRAM Compiler -- FlexCache: A Framework for Flexible Compiler Generated Data Caching -- Poster Session -- Aggressive Memory-Aware Compilation -- Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips? -- SAGE: A New Analysis and Optimization System for FlexRAM Architecture -- Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems -- The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems -- Compiler-Directed Cache Line Size Adaptivity ? -- Summary of Question/Answer Sessions for Workshop Presentations. |
| Record Nr. | UNINA-9910143594003321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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