Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
Compiler Construction [[electronic resource] ] : 21st International Conference, CC 2012, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2012, Tallinn, Estonia, March 24 -- April 1, 2012, Proceedings / / edited by Michael O'Boyle
| Compiler Construction [[electronic resource] ] : 21st International Conference, CC 2012, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2012, Tallinn, Estonia, March 24 -- April 1, 2012, Proceedings / / edited by Michael O'Boyle |
| Edizione | [1st ed. 2012.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2012 |
| Descrizione fisica | 1 online resource (XVI, 245 p.) |
| Disciplina | 005.1 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Software engineering
Compilers (Computer programs) Computer programming Machine theory Computer networks Algorithms Software Engineering Compilers and Interpreters Programming Techniques Formal Languages and Automata Theory Computer Communication Networks |
| ISBN | 3-642-28652-6 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996465918403316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
High Performance Embedded Architectures and Compilers [[electronic resource] ] : Fourth International Conference, HiPEAC 2009 / / edited by André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : Fourth International Conference, HiPEAC 2009 / / edited by André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XIII, 420 p.) |
| Disciplina | 003.3 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computer arithmetic and logic units Microprocessors Computer architecture Computer input-output equipment Logic design Computer networks Computer System Implementation Arithmetic and Logic Structures Processor Architectures Input/Output and Data Communications Logic Design Computer Communication Networks |
| ISBN | 3-540-92990-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote: Challenges on the Road to Exascale Computing -- Keynote: Compilers in the Manycore Era -- I Dynamic Translation and Optimisation -- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering -- Predictive Runtime Code Scheduling for Heterogeneous Architectures -- Collective Optimization -- High Speed CPU Simulation Using LTU Dynamic Binary Translation -- II Low Level Scheduling -- Integrated Modulo Scheduling for Clustered VLIW Architectures -- Software Pipelining in Nested Loops with Prolog-Epilog Merging -- A Flexible Code Compression Scheme Using Partitioned Look-Up Tables -- III Parallelism and Resource Control -- MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor -- IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor -- A Hardware Task Scheduler for Embedded Video Processing -- Finding Stress Patterns in Microprocessor Workloads -- IV Communication -- Deriving Efficient Data Movement from Decoupled Access/Execute Specifications -- MPSoC Design Using Application-Specific Architecturally Visible Communication -- Communication Based Proactive Link Power Management -- V Mapping for CMPs -- Mapping and Synchronizing Streaming Applications on Cell Processors -- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors -- Accomodating Diversity in CMPs with Heterogeneous Frequencies -- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip -- VI Power -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines -- HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic -- Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures -- VII Cache Issues -- Revisiting Cache Block Superloading -- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors -- In-Network Caching for Chip Multiprocessors -- VIII Parallel Embedded Applications -- Parallel LDPC Decoding on the Cell/B.E. Processor -- Parallel H.264 Decoding on an Embedded Multicore Processor. |
| Record Nr. | UNISA-996466362503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||