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ASIC/SoC Functional Design Verification : A Comprehensive Guide to Technologies and Methodologies / / by Ashok B. Mehta
| ASIC/SoC Functional Design Verification : A Comprehensive Guide to Technologies and Methodologies / / by Ashok B. Mehta |
| Autore | Mehta Ashok B |
| Edizione | [1st ed. 2018.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 |
| Descrizione fisica | 1 online resource (XXXI, 328 p. 175 illus., 160 illus. in color.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Microprocessors Logic design Circuits and Systems Processor Architectures Logic Design |
| ISBN | 3-319-59418-4 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1.Introduction -- Chapter 2.Functional Verification- Challeenges and Solution -- Chapter 3.SystemVerilog Paradigm -- Chapter 4. UVM -- Chapter 5.CRV -- Chapter 6.SVA -- Chapter 7.SFC -- Chapter 8.CDC -- Chapter 9.Low Power Verification -- Chapter 10. Static Verification -- Chapter 11.ESL -- Chapter 12. Hardware/Software Co-verification -- Chapter 13 -- Analog Mixed Signals Verification -- Chapter 14 -- SOC Interconnect Verification -- Chapter 15. The Complete Product Design Lifecycle -- Chapter 16. Voice Over IP -- Chapter 17. Cache Memory Subsystem Verification: UVM Agent Based -- Chapter 18. Cache Memory Subsystem Verification: ISS Based. |
| Record Nr. | UNINA-9910299911803321 |
Mehta Ashok B
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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System Verilog Assertions and Functional Coverage : Guide to Language, Methodology and Applications / / by Ashok B. Mehta
| System Verilog Assertions and Functional Coverage : Guide to Language, Methodology and Applications / / by Ashok B. Mehta |
| Autore | Mehta Ashok B |
| Edizione | [3rd ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XXXIX, 507 p. 270 illus., 258 illus. in color.) |
| Disciplina |
621.3815
621.392 |
| Soggetto topico |
Electronic circuits
Electronics Microelectronics Microprocessors Circuits and Systems Electronics and Microelectronics, Instrumentation Processor Architectures |
| ISBN | 3-030-24737-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions – Basics (sequence, property, assert) -- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- ‘expect’ -- ‘assume’ and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800–2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions – LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options. |
| Record Nr. | UNINA-9910366582703321 |
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Mehta Ashok B
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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System Verilog assertions and functional coverage : guide to language, methodology and applications / / Ashok B. Mehta
| System Verilog assertions and functional coverage : guide to language, methodology and applications / / Ashok B. Mehta |
| Autore | Mehta Ashok B |
| Pubbl/distr/stampa | New York, : Springer, c2014 |
| Descrizione fisica | 1 online resource (xxxiii, 356 pages) : illustrations (some color) |
| Disciplina |
004.1
620 621.381 621.3815 |
| Collana | Gale eBooks |
| Soggetto topico |
Computer hardware description languages
Verilog (Computer hardware description language) |
| ISBN | 1-4614-7324-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions – Basics (sequence, property, assert).- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- ‘expect’ -- ‘assume’ and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800–2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions – LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options (Reference material). |
| Record Nr. | UNINA-9910299760103321 |
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Mehta Ashok B
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| New York, : Springer, c2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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SystemVerilog Assertions and Functional Coverage : Guide to Language, Methodology and Applications / / by Ashok B. Mehta
| SystemVerilog Assertions and Functional Coverage : Guide to Language, Methodology and Applications / / by Ashok B. Mehta |
| Autore | Mehta Ashok B |
| Edizione | [2nd ed. 2016.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 |
| Descrizione fisica | 1 online resource (424 p.) |
| Disciplina | 620 |
| Soggetto topico |
Electronic circuits
Electronics Microelectronics Microprocessors Circuits and Systems Electronics and Microelectronics, Instrumentation Processor Architectures |
| ISBN | 3-319-30539-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions – Basics (sequence, property, assert) -- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- ‘expect’ -- ‘assume’ and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800–2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions – LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options. |
| Record Nr. | UNINA-9910254234803321 |
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Mehta Ashok B
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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