Autore	Maxfield Clive <1957->
Pubbl/distr/stampa	Hoboken, N.J., : Wiley-Interscience, c2005
Descrizione fisica	1 online resource (469 p.)
Disciplina	004.0151 004/.01/51
Altri autori (Persone)	BrownAlvin <1954->
Soggetto topico	Computer science - Mathematics
Soggetto genere / forma	Electronic books.
ISBN	1-280-23573-X 9786610235735 0-470-36237-5 0-471-74196-5 0-471-74197-3
Classificazione	54.00
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	How Computers Do Math; Contents; Laboratories; Do You Speak Martian?; Chapter 0 Why This Book Is So Cool; Chapter 1 Introducing Binary and Hexadecimal Numbers; Chapter 2 Computers and Calculators; Chapter 3 Subroutines and Other Stuff; Chapter 4 Integer Arithmetic; Chapter 5 Creating an Integer Calculator; Chapter 6 More Functions and Experiments; Interactive Laboratories; Appendix A Installing Your DIY Calculator; Appendix B Addressing Modes; Appendix C Instruction Set Summary; Appendix D Additional Resources; About the Authors; Acknowledgments; Index
Record Nr.	UNINA-9910144256803321

Autore	Maxfield Clive <1957->
Edizione	[1st edition]
Pubbl/distr/stampa	Amsterdam ; ; London, : Newnes, c2004
Descrizione fisica	1 online resource (561 p.)
Disciplina	621.395
Soggetto topico	Field programmable gate arrays Gate array circuits
Soggetto genere / forma	Electronic books.
ISBN	1-280-74598-3 9786610745982 0-08-047713-5
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Front Cover; Copyright; Table of Contents; Preface; Acknowledgments; 1. Introduction; 2. Fundamental Concepts; 3. The Origin of FPGAs; 4. Alternative FPGA Architectures; 5. Programming SConfiguringw an FPGA; 6. Who Are All the Players?; 7. FPGA Versus ASIC Design Styles; 8. Schematic-Based Design Flows; 9. HDL-Based Design Flows; 10. Silicon Virtual Prototyping for FPGAs; 11. C/Cbb etc.-Based Design Flows; 12. DSPIBased Design Flows; 13. Embedded Processor-Based Design Flows; 14. Modular and Incremental Design; 15. High-Speed Design and Other PCB Considerations 16. Observing Internal Nodes in an FPGA17. Intellectual Property; 18. Migrating ASIC Designs to FPGAs and Vice Versa; 19. SimulationI SynthesisI VerificationI etcB Design Tools; 20. Choosing the Right Device; 21. Gigabit Transceivers; 22. Reconfigurable Computing; 23. Field-Programmable Node Arrays; 24. Independent Design Tools; 25. Creating an Open-Source-Based Design Flow; 26. Future FPGA Developments; Appendix A: Signal Integrity 101; Appendix B: Deep-Submicron Delay Effects 101; Appendix C: Linear Feedback Shift Registers 101; Glossary; About the Author; Index
Record Nr.	UNINA-9910450547703321

Autore	Maxfield Clive <1957->
Edizione	[1st edition]
Pubbl/distr/stampa	Amsterdam ; ; Boston, : Newnes, c2008
Descrizione fisica	1 online resource (217 p.)
Disciplina	621.39/5
Collana	The Newnes instant access series
Soggetto topico	Field programmable gate arrays Gate array circuits
ISBN	9786611796112 9781281796110 1281796115 9780080560113 0080560113
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Front Cover; FPGAs: Instant Access; Copyright Page; Contents; About the Author; Chapter 1. The Fundamentals; Why Use FPGAs?; Applications; Some Technology Background; Fusible-link Technology; FPGA Programming Technologies; Instant Summary; Chapter 2. FPGA Architectures; More on Programming Technologies; SRAM-based Devices; Antifuse-based Devices; E[sup(2)]PROM/FLASH-based Devices; Hybrid FLASH-SRAM Devices; Fine-, Medium-, and Coarse-grained Architectures; Logic Blocks; MUX-based; LUT-based; LUT versus Distributed RAM versus SR; CLBs versus LABs versus Slices; Logic Cells/Logic Elements Slicing and DicingCLBs and LABs; Distributed RAMs and Shift Registers; Embedded RAMs; Embedded Multipliers, Adders, etc.; Embedded Processor Cores; Hard Microprocessor Cores; Soft Microprocessor Cores; Clock Managers; Clock Trees; Clock Managers; General-purpose I/O; Configurable I/O Standards; Configurable I/O Impedances; Core versus I/O Supply Voltages; Gigabit Transceivers; Multiple Standards; Intellectual Property (IP); Handcrafted IP; IP Core Generators; System Gates versus Real Gates; Instant Summary; Chapter 3. Programming (Configuring) an FPGA; Configuration Cells Antifuse-based FPGAsSRAM-based FPGAs; Programming Embedded (Block) RAMs, Distributed RAMs, etc.; Multiple Programming Chains; Quickly Reinitializing the Device; Using the Configuration Port; Serial Load with FPGA as Master; Parallel Load with FPGA as Master; Parallel Load with FPGA as Slave; Serial Load with FPGA as Slave; Using the JTAG Port; Using an Embedded Processor; Instant Summary; Chapter 4. FPGA vs. ASIC Designs; When You Switch from ASIC to FPGA Design, or Vice Versa; Coding Styles; Pipelining and Levels of Logic; Levels of Logic; Asynchronous Design Practices Asynchronous StructuresCombinational Loops; Delay Chains; Clock Considerations; Clock Domains; Clock Balancing; Clock Gating versus Clock Enabling; PLLs and Clock Conditioning Circuitry; Reliable Data Transfer across Multiclock Domains; Register and Latch Considerations; Latches; Flip-flops with both ""Set"" and ""Reset"" Inputs; Global Resets and Initial Conditions; Resource Sharing (Time-Division Multiplexing); Use It or Lose It!; But Wait, There's More; State Machine Encoding; Test Methodologies; Migrating ASIC Designs to FPGAs and Vice Versa; Alternative Design Scenarios; Instant Summary Chapter 5. ""Traditional"" Design FlowsSchematic-based Design Flows; Back-end Tools like Layout; CAE + CAD = EDA; A Simple (early) Schematic-driven ASIC Flow; A Simple (early) Schematic-driven FPGA Flow; Flat versus Hierarchical Schematics; Schematic-driven FPGA Design Flows Today; HDL-based Design Flows; Advent of HDL-based Flows; A Plethora of HDLs; Points to Ponder; Instant Summary; Chapter 6. Other Design Flows; C/C++-based Design Flows; C versus C++ and Concurrent versus Sequential; SystemC-based Flows; Augmented C/C++-based Flows; Pure C/C++ -based Flows Different Levels of Synthesis Abstraction
Altri titoli varianti	Field programmable gate arrays instant access
Record Nr.	UNINA-9911006887103321