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Evolving OpenMP for Evolving Architectures [[electronic resource] ] : 14th International Workshop on OpenMP, IWOMP 2018, Barcelona, Spain, September 26–28, 2018, Proceedings / / edited by Bronis R. de Supinski, Pedro Valero-Lara, Xavier Martorell, Sergi Mateo Bellido, Jesus Labarta
| Evolving OpenMP for Evolving Architectures [[electronic resource] ] : 14th International Workshop on OpenMP, IWOMP 2018, Barcelona, Spain, September 26–28, 2018, Proceedings / / edited by Bronis R. de Supinski, Pedro Valero-Lara, Xavier Martorell, Sergi Mateo Bellido, Jesus Labarta |
| Edizione | [1st ed. 2018.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 |
| Descrizione fisica | 1 online resource (X, 253 p. 103 illus.) |
| Disciplina | 004.35 |
| Collana | Programming and Software Engineering |
| Soggetto topico |
Microprocessors
Software engineering Logic design Computers Processor Architectures Software Engineering/Programming and Operating Systems Logic Design Models and Principles |
| ISBN | 3-319-98521-3 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Best Paper -- The Impact of Taskyield on the Design of Tasks Communicating through MPI -- Loops and OpenMP -- OpenMP Loop Scheduling Revisited: Making a Case for More Schedules -- A Proposal for Loop-Transformation Pragmas -- Extending OpenMP to Facilitate Loop Optimization -- OpenMP in Heterogeneous Systems -- Manage OpenMP GPU Data Environment under Unified Address Space -- OpenMP 4.5 Validation and Verification Suite for Device Offload -- Trade-o_ of offloading to FPGA in OpenMP Task-based programming -- OpenMP Improvements and Innovations -- Compiler Optimizations For OpenMP -- Supporting Function Variants in OpenMP -- Towards an OpenMP Specification for Critical Real-time Systems -- OpenMP User Experiences: Applications and Tools -- Performance Tuning to Close Ninja Gap for Accelerator Physics Emulation System (APES) on Intel Xeon Phi Processors -- Visualization of OpenMP Task Dependencies using Intel Advisor Flow Graph Analyzer -- A Semantics-Driven Approach to Improving DataRaceBench's OpenMP Standard Coverage -- Tasking Evaluations -- On the Impact of OpenMP Task Granularity -- Mapping OpenMP to a Distributed Tasking Runtime -- Assessing Task-to-Data Affinity in the LLVM OpenMP Runtime. |
| Record Nr. | UNISA-996466191103316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Evolving OpenMP for Evolving Architectures : 14th International Workshop on OpenMP, IWOMP 2018, Barcelona, Spain, September 26–28, 2018, Proceedings / / edited by Bronis R. de Supinski, Pedro Valero-Lara, Xavier Martorell, Sergi Mateo Bellido, Jesus Labarta
| Evolving OpenMP for Evolving Architectures : 14th International Workshop on OpenMP, IWOMP 2018, Barcelona, Spain, September 26–28, 2018, Proceedings / / edited by Bronis R. de Supinski, Pedro Valero-Lara, Xavier Martorell, Sergi Mateo Bellido, Jesus Labarta |
| Edizione | [1st ed. 2018.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 |
| Descrizione fisica | 1 online resource (X, 253 p. 103 illus.) |
| Disciplina | 004.35 |
| Collana | Programming and Software Engineering |
| Soggetto topico |
Microprocessors
Software engineering Logic design Computers Processor Architectures Software Engineering/Programming and Operating Systems Logic Design Models and Principles |
| ISBN | 3-319-98521-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Best Paper -- The Impact of Taskyield on the Design of Tasks Communicating through MPI -- Loops and OpenMP -- OpenMP Loop Scheduling Revisited: Making a Case for More Schedules -- A Proposal for Loop-Transformation Pragmas -- Extending OpenMP to Facilitate Loop Optimization -- OpenMP in Heterogeneous Systems -- Manage OpenMP GPU Data Environment under Unified Address Space -- OpenMP 4.5 Validation and Verification Suite for Device Offload -- Trade-o_ of offloading to FPGA in OpenMP Task-based programming -- OpenMP Improvements and Innovations -- Compiler Optimizations For OpenMP -- Supporting Function Variants in OpenMP -- Towards an OpenMP Specification for Critical Real-time Systems -- OpenMP User Experiences: Applications and Tools -- Performance Tuning to Close Ninja Gap for Accelerator Physics Emulation System (APES) on Intel Xeon Phi Processors -- Visualization of OpenMP Task Dependencies using Intel Advisor Flow Graph Analyzer -- A Semantics-Driven Approach to Improving DataRaceBench's OpenMP Standard Coverage -- Tasking Evaluations -- On the Impact of OpenMP Task Granularity -- Mapping OpenMP to a Distributed Tasking Runtime -- Assessing Task-to-Data Affinity in the LLVM OpenMP Runtime. |
| Record Nr. | UNINA-9910349408503321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
High Performance Embedded Architectures and Compilers [[electronic resource] ] : 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings / / edited by Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings / / edited by Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell |
| Edizione | [1st ed. 2010.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 |
| Descrizione fisica | 1 online resource (XIII, 370 p.) |
| Disciplina | 005.4/53 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer programming
Computer arithmetic and logic units Microprocessors Computer architecture Computer input-output equipment Logic design Computer networks Programming Techniques Arithmetic and Logic Structures Processor Architectures Input/Output and Data Communications Logic Design Computer Communication Networks |
| ISBN |
1-280-38556-1
9786613563484 3-642-11515-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Embedded Systems as Datacenters -- Larrabee: A Many-Core Intel Architecture for Visual Computing -- Architectural Support for Concurrency -- Remote Store Programming -- Low-Overhead, High-Speed Multi-core Barrier Synchronization -- Improving Performance by Reducing Aborts in Hardware Transactional Memory -- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems -- Compilation and Runtime Systems -- Split Register Allocation: Linear Complexity Without the Performance Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors -- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures -- Reconfigurable and Customized Architectures -- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions -- Accelerating XML Query Matching through Custom Stack Generation on FPGAs -- An Application-Aware Load Balancing Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays -- Multicore Efficiency, Reliability, and Power -- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors -- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors -- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor -- Performance and Power Aware CMP Thread Allocation Modeling -- Memory Organization and Optimization -- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching -- Scalable Shared-Cache Management by Containing Thrashing Workloads -- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs -- DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems -- Programming and Analysis of Accelerators -- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor -- Analysis of Task Offloading for Accelerators -- Offload – Automating Code Migration to Heterogeneous Multicore Systems -- Computer Generation of Efficient Software Viterbi Decoders. |
| Record Nr. | UNISA-996465510303316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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