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Digital design [[electronic resource]] : with a introduction to the verilog hdl / / M. Morris Mano, Michael D. Ciletti ; international edition contributions by B.R. Chandavarkar
| Digital design [[electronic resource]] : with a introduction to the verilog hdl / / M. Morris Mano, Michael D. Ciletti ; international edition contributions by B.R. Chandavarkar |
| Autore | Mano M. Morris <1927-> |
| Edizione | [Fifth edition, International edition.] |
| Pubbl/distr/stampa | Upper Saddle River, New Jersey : , : Pearson Prentice Hall, , [2013] |
| Descrizione fisica | 1 online resource (564 pages) |
| Disciplina | 621.395 |
| Soggetto topico |
Electronic digital computers - Circuits
Logic circuits Logic design Digital integrated circuits |
| ISBN | 0-273-77546-4 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Contents -- Preface -- 1 Digital Systems and Binary Numbers -- 1.1 Digital Systems -- 1.2 Binary Numbers -- 1.3 Number-Base Conversions -- 1.4 Octal and Hexadecimal Numbers -- 1.5 Complements of Numbers -- 1.6 Signed Binary Numbers -- 1.7 Binary Codes -- 1.8 Binary Storage and Registers -- 1.9 Binary Logic -- 2 Boolean Algebra and Logic Gates -- 2.1 Introduction -- 2.2 Basic Definitions -- 2.3 Axiomatic Definition of Boolean Algebra -- 2.4 Basic Theorems and Properties of Boolean Algebra -- 2.5 Boolean Functions -- 2.6 Canonical and Standard Forms -- 2.7 Other Logic Operations -- 2.8 Digital Logic Gates -- 2.9 Integrated Circuits -- 3 Gate-Level Minimization -- 3.1 Introduction -- 3.2 The Map Method -- 3.3 Four-Variable K-Map -- 3.4 Product-of-Sums Simplification -- 3.5 Don't-Care Conditions -- 3.6 NAND and NOR Implementation -- 3.7 Other Two-Level Implementations -- 3.8 Exclusive-OR Function -- 3.9 Hardware Description Language -- 4 Combinational Logic -- 4.1 Introduction -- 4.2 Combinational Circuits -- 4.3 Analysis Procedure -- 4.4 Design Procedure -- 4.5 Binary Adder-Subtractor -- 4.6 Decimal Adder -- 4.7 Binary Multiplier -- 4.8 Magnitude Comparator -- 4.9 Decoders -- 4.10 Encoders -- 4.11 Multiplexers -- 4.12 HDL Models of Combinational Circuits -- 5 Synchronous Sequential Logic -- 5.1 Introduction -- 5.2 Sequential Circuits -- 5.3 Storage Elements: Latches -- 5.4 Storage Elements: Flip-Flops -- 5.5 Analysis of Clocked Sequential Circuits -- 5.6 Synthesizable HDL Models of Sequential Circuits -- 5.7 State Reduction and Assignment -- 5.8 Design Procedure -- 6 Registers and Counters -- 6.1 Registers -- 6.2 Shift Registers -- 6.3 Ripple Counters -- 6.4 Synchronous Counters -- 6.5 Other Counters -- 6.6 HDL for Registers and Counters -- 7 Memory and Programmable Logic -- 7.1 Introduction -- 7.2 Random-Access Memory.
7.3 Memory Decoding -- 7.4 Error Detection and Correction -- 7.5 Read-Only Memory -- 7.6 Programmable Logic Array -- 7.7 Programmable Array Logic -- 7.8 Sequential Programmable Devices -- 8 Design at the Register Transfer Level -- 8.1 Introduction -- 8.2 Register Transfer Level Notation -- 8.3 Register Transfer Level in HDL -- 8.4 Algorithmic State Machines (ASMs) -- 8.5 Design Example (ASMD Chart) -- 8.6 HDL Description of Design Example -- 8.7 Sequential Binary Multiplier -- 8.8 Control Logic -- 8.9 HDL Description of Binary Multiplier -- 8.10 Design with Multiplexers -- 8.11 Race-Free Design (Software Race Conditions) -- 8.12 Latch-Free Design (Why Waste Silicon?) -- 8.13 Other Language Features -- 9 Laboratory Experiments with Standard ICs and FPGAs -- 9.1 Introduction to Experiments -- 9.2 Experiment 1: Binary and Decimal Numbers -- 9.3 Experiment 2: Digital Logic Gates -- 9.4 Experiment 3: Simplification of Boolean Functions -- 9.5 Experiment 4: Combinational Circuits -- 9.6 Experiment 5: Code Converters -- 9.7 Experiment 6: Design with Multiplexers -- 9.8 Experiment 7: Adders and Subtractors -- 9.9 Experiment 8: Flip-Flops -- 9.10 Experiment 9: Sequential Circuits -- 9.11 Experiment 10: Counters -- 9.12 Experiment 11: Shift Registers -- 9.13 Experiment 12: Serial Addition -- 9.14 Experiment 13: Memory Unit -- 9.15 Experiment 14: Lamp Handball -- 9.16 Experiment 15: Clock-Pulse Generator -- 9.17 Experiment 16: Parallel Adder and Accumulator -- 9.18 Experiment 17: Binary Multiplier -- 9.19 Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs -- 10 Standard Graphic Symbols -- 10.1 Rectangular-Shape Symbols -- 10.2 Qualifying Symbols -- 10.3 Dependency Notation -- 10.4 Symbols for Combinational Elements -- 10.5 Symbols for Flip-Flops -- 10.6 Symbols for Registers -- 10.7 Symbols for Counters -- 10.8 Symbol for RAM -- Appendix. Answers to Selected Problems -- Index. |
| Record Nr. | UNINA-9910150213903321 |
Mano M. Morris <1927->
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| Upper Saddle River, New Jersey : , : Pearson Prentice Hall, , [2013] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Logic and computer design fundamentals / / Morris R. Mano, Charles R. Kime, Tom Martin
| Logic and computer design fundamentals / / Morris R. Mano, Charles R. Kime, Tom Martin |
| Autore | Mano M. Morris <1927-> |
| Edizione | [Fifth edition.] |
| Pubbl/distr/stampa | Harlow, England : , : Pearson Education Limited, , [2016] |
| Descrizione fisica | 1 online resource (673 pages) : illustrations (some color) |
| Disciplina | 621.395 |
| Soggetto topico | Electronic digital computers - Circuits |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Logic and Computer Design Fundamentals -- Copyright -- Contents -- Preface -- Chapter 1: Digital Systems and Information -- Information Representation -- The Digital Computer -- Beyond the Computer -- More on the Generic Computer -- Abstraction Layers in Computer Systems Design -- An Overview of the Digital Design Process -- Number Systems -- Binary Numbers -- Octal and Hexadecimal Numbers -- Number Ranges -- Arithmetic Operations -- Conversion from Decimal to Other Bases -- Decimal Codes -- Alphanumeric Codes -- ASCII Character Code -- Parity Bit -- Gray Codes -- Chapter Summary -- References -- Problems -- Chapter 2: Combinational Logic Circuits -- Binary Logic and Gates -- Binary Logic -- Logic Gates -- HDL Representations of Gates -- Boolean Algebra -- Basic Identities of Boolean Algebra -- Algebraic Manipulation -- Complement of a Function -- Standard Forms -- Minterms and Maxterms -- Sum of Products -- Product of Sums -- Two-Level Circuit Optimization -- Cost Criteria -- Map Structures -- Two-Variable Maps -- Three-Variable Maps -- Map Manipulation -- Essential Prime Implicants -- Nonessential Prime Implicants -- Product-of-Sums Optimization -- Don't-Care Conditions -- Exclusive-Or Operator and Gates -- Odd Function -- Gate Propagation Delay -- HDLs Overview -- Logic Synthesis -- HDL Representations-VHDL -- HDL Representations-Verilog -- Chapter Summary -- References -- Problems -- Chapter 3: Combinational Logic Design -- Beginning Hierarchical Design -- Technology Mapping -- Combinational Functional Blocks -- Rudimentary Logic Functions -- Value-Fixing, Transferring, and Inverting -- Multiple-Bit Functions -- Enabling -- Decoding -- Decoder and Enabling Combinations -- Decoder-Based Combinational Circuits -- Encoding -- Priority Encoder -- Encoder Expansion -- Selecting -- Multiplexers -- Multiplexer-Based Combinational Circuits.
Iterative Combinational Circuits -- Binary Adders -- Half Adder -- Full Adder -- Binary Ripple Carry Adder -- Binary Subtraction -- Complements -- Subtraction Using 2s Complement -- Binary Adder-Subtractors -- Signed Binary Numbers -- Signed Binary Addition and Subtraction -- Overflow -- HDL Models of Adders -- Behavioral Description -- Other Arithmetic Functions -- Contraction -- Incrementing -- Decrementing -- Multiplication by Constants -- Division by Constants -- Zero Fill and Extension -- Chapter Summary -- References -- Problems -- Chapter 4: Sequential Circuits -- Sequential Circuit Definitions -- Latches -- SR and SR Latches -- D Latch -- Flip-Flops -- Edge-Triggered Flip-Flop -- Standard Graphics Symbols -- Direct Inputs -- Sequential Circuit Analysis -- Input Equations -- State Table -- State Diagram -- Sequential Circuit Simulation -- Sequential Circuit Design -- Design Procedure -- Finding State Diagrams and State Tables -- State Assignment -- Designing with D Flip-Flops -- Designing with Unused States -- Verification -- State-Machine Diagrams and Applications -- State-Machine Diagram Model -- Constraints on Input Conditions -- Design Applications Using State- Machine Diagrams -- HDL Representation for Sequential Circuits-VHDL -- HDL Representation for Sequential Circuits-Verilog -- Flip-Flop Timing -- Sequential Circuit Timing -- Asynchronous Interactions -- Synchronization and Metastability -- Synchronous Circuit Pitfalls -- Chapter Summary -- References -- Problems -- Chapter 5: Digital Hardware Implementation -- The Design Space -- Integrated Circuits -- CMOS Circuit Technology -- Technology Parameters -- Programmable Implementation Technologies -- Read-Only Memory -- Programmable Logic Array -- Programmable Array Logic Devices -- Field Programmable Gate Array -- Chapter Summary -- References -- Problems. Chapter 6: Registers and Register Transfers -- Registers and Load Enable -- Register with Parallel Load -- Register Transfers -- Register Transfer Operations -- Register Transfers in VHDL and Verilog -- Microoperations -- Arithmetic Microoperations -- Logic Microoperations -- Shift Microoperations -- Microoperations on a Single Register -- Multiplexer-Based Transfers -- Shift Registers -- Ripple Counter -- Synchronous Binary Counters -- Other Counters -- Register-Cell Design -- Multiplexer and Bus-Based Transfers for Multiple Registers -- High-Impedance Outputs -- Three-State Bus -- Serial Transfer and Microoperations -- Serial Addition -- Control of Register Transfers -- Design Procedure -- HDL Representation for Shift Registers and Counters-VHDL -- HDL Representation for Shift Registers and Counters-Verilog -- Microprogrammed Control -- Chapter Summary -- References -- Problems -- Chapter 7: Memory Basics -- Memory Definitions -- Random-Access Memory -- Write and Read Operations -- Timing Waveforms -- Properties of Memory -- SRAM Integrated Circuits -- Coincident Selection -- Array of SRAM ICs -- DRAM ICs -- DRAM Cell -- DRAM Bit Slice -- DRAM Types -- Synchronous DRAM (SDRAM) -- Double-Data-Rate SDRAM (DDR SDRAM) -- RAMBUS® DRAM (RDRAM) -- Arrays of Dynamic RAM ICs -- Chapter Summary -- References -- Problems -- Chapter 8: Computer Design Basics -- Introduction -- Datapaths -- The Arithmetic/Logic Unit -- Arithmetic Circuit -- Logic Circuit -- Arithmetic/Logic Unit -- The Shifter -- Barrel Shifter -- Datapath Representation -- The Control Word -- A Simple Computer Architecture -- Instruction Set Architecture -- Storage Resources -- Instruction Formats -- Instruction Specifications -- Single-Cycle Hardwired Control -- Instruction Decoder -- Sample Instructions and Program -- Single-Cycle Computer Issues -- Multiple-Cycle Hardwired Control. Sequential Control Design -- Chapter Summary -- References -- Problems -- Chapter 9: Instruction Set Architecture -- Computer Architecture Concepts -- Basic Computer Operation Cycle -- Register Set -- Operand Addressing -- Three-Address Instructions -- Two-Address Instructions -- One-Address Instructions -- Zero- Address Instructions -- Addressing Architectures -- Addressing Modes -- Implied Mode -- Immediate Mode -- Register and Register-Indirect Modes -- Direct Addressing Mode -- Indirect Addressing Mode -- Relative Addressing Mode -- Indexed Addressing Mode -- Summary of Addressing Modes -- Instruction Set Architectures -- Data-Transfer Instructions -- Stack Instructions -- Independent versus Memory- Mapped I/O -- Data-Manipulation Instructions -- Arithmetic Instructions -- Logical and Bit- Manipulation Instructions -- Shift Instructions -- Floating-Point Computations -- Arithmetic Operations -- Arithmetic Operations -- Standard Operand Format -- Program Control Instructions -- Conditional Branch Instructions -- Procedure Call and Return Instructions -- Program Interrupt -- Types of Interrupts -- Processing External Interrupts -- Chapter Summary -- References -- Problems -- Chapter 10: Risc and Cisc Central Processing Units -- Pipelined Datapath -- Execution of Pipeline Microoperations -- Pipelined Control -- Pipeline Programming and Performance -- The Reduced Instruction Set Computer -- Instruction Set Architecture -- Addressing Modes -- Datapath Organization -- Control Organization -- Data Hazards -- Control Hazards -- The Complex Instruction Set Computer -- ISA Modifications -- Datapath Modifications -- Control Unit Modifications -- Microprogrammed Control -- Microprograms for Complex Instructions -- More on Design -- Advanced CPU Concepts -- Recent Architectural Innovations -- Chapter Summary -- References -- Problems. Chapter 11: Input-Output and Communication -- Computer I/O -- Sample Peripherals -- Keyboard -- Hard Drive -- Liquid Crystal Display Screen -- I/O Transfer Rates -- I/O Interfaces -- I/O Bus and Interface Unit -- Example of I/O Interface -- Strobing -- Handshaking -- Serial Communication -- Synchronous Transmission -- The Keyboard Revisited -- A Packet-Based Serial I/O Bus -- Modes of Transfer -- Example of Program-Controlled Transfer -- Interrupt-Initiated Transfer -- Priority Interrupt -- Daisy Chain Priority -- Parallel Priority Hardware -- Direct Memory Access -- DMA Controller -- DMA Transfe -- Chapter Summary -- References -- Problems -- Chapter 12: Memory Systems -- Memory Hierarchy -- Locality of Reference -- Cache Memory -- Cache Mappings -- Line Size -- Cache Loading -- Write Methods -- Integration of Concepts -- Instruction and Data Caches -- Multiple-Level Caches -- Virtual Memory -- Page Tables -- Translation Lookaside Buffer -- Virtual Memory and Cache -- Chapter Summary -- References -- Problems -- Index. |
| Record Nr. | UNINA-9910154944603321 |
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Mano M. Morris <1927->
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| Harlow, England : , : Pearson Education Limited, , [2016] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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