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Computer System Design [[electronic resource] ] : System-on-Chip
| Computer System Design [[electronic resource] ] : System-on-Chip |
| Autore | Flynn Michael J |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, : Wiley, 2011 |
| Descrizione fisica | 1 online resource (356 p.) |
| Disciplina | 004.1 |
| Altri autori (Persone) | LukWayne |
| Soggetto topico |
Systems on a chip
Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-283-15735-7
9786613157355 1-118-00991-6 1-118-00992-4 1-118-00990-8 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
COMPUTER SYSTEM DESIGN; CONTENTS; PREFACE; LIST OF ABBREVIATIONS AND ACRONYMS; 1: Introduction to the Systems Approach; 1.1 SYSTEM ARCHITECTURE: AN OVERVIEW; 1.2 COMPONENTS OF THE SYSTEM: PROCESSORS, MEMORIES, AND INTERCONNECTS; 1.3 HARDWARE AND SOFTWARE: PROGRAMMABILITY VERSUS PERFORMANCE; 1.4 PROCESSOR ARCHITECTURES; 1.4.1 Processor: A Functional View; 1.4.2 Processor: An Architectural View; 1.5 MEMORY AND ADDRESSING; 1.5.1 SOC Memory Examples; 1.5.2 Addressing: The Architecture of Memory; 1.5.3 Memory for SOC Operating System; 1.6 SYSTEM-LEVEL INTERCONNECTION; 1.6.1 Bus-Based Approach
1.6.2 Network-on-Chip Approach1.7 AN APPROACH FOR SOC DESIGN; 1.7.1 Requirements and Specifications; 1.7.2 Design Iteration; 1.8 SYSTEM ARCHITECTURE AND COMPLEXITY; 1.9 PRODUCT ECONOMICS AND IMPLICATIONS FOR SOC; 1.9.1 Factors Affecting Product Costs; 1.9.2 Modeling Product Economics and Technology Complexity: The Lesson for SOC; 1.10 DEALING WITH DESIGN COMPLEXITY; 1.10.1 Buying IP; 1.10.2 Reconfiguration; 1.11 CONCLUSIONS; 1.12 PROBLEM SET; 2: Chip Basics: Time, Area, Power, Reliability, and Configurability; 2.1 INTRODUCTION; 2.1.1 Design Trade-Offs; 2.1.2 Requirements and Specifications 2.2 CYCLE TIME2.2.1 Defining a Cycle; 2.2.2 Optimum Pipeline; 2.2.3 Performance; 2.3 DIE AREA AND COST; 2.3.1 Processor Area; 2.3.2 Processor Subunits; 2.4 IDEAL AND PRACTICAL SCALING; 2.5 POWER; 2.6 AREA-TIME-POWER TRADE-OFFS IN PROCESSOR DESIGN; 2.6.1 Workstation Processor; 2.6.2 Embedded Processor; 2.7 RELIABILITY; 2.7.1 Dealing with Physical Faults; 2.7.2 Error Detection and Correction; 2.7.3 Dealing with Manufacturing Faults; 2.7.4 Memory and Function Scrubbing; 2.8 CONFIGURABILITY; 2.8.1 Why Reconfigurable Design?; 2.8.2 Area Estimate of Reconfigurable Devices; 2.9 CONCLUSION 2.10 PROBLEM SET3: Processors; 3.1 INTRODUCTION; 3.2 PROCESSOR SELECTION FOR SOC; 3.2.1 Overview; 3.2.2 Example: Soft Processors; 3.2.3 Examples: Processor Core Selection; 3.3 BASIC CONCEPTS IN PROCESSOR ARCHITECTURE; 3.3.1 Instruction Set; 3.3.2 Some Instruction Set Conventions; 3.3.3 Branches; 3.3.4 Interrupts and Exceptions; 3.4 BASIC CONCEPTS IN PROCESSOR MICROARCHITECTURE; 3.5 BASIC ELEMENTS IN INSTRUCTION HANDLING; 3.5.1 The Instruction Decoder and Interlocks; 3.5.2 Bypassing; 3.5.3 Execution Unit; 3.6 BUFFERS: MINIMIZING PIPELINE DELAYS; 3.6.1 Mean Request Rate Buffers 3.6.2 Buffers Designed for a Fixed or Maximum Request Rate3.7 BRANCHES: REDUCING THE COST OF BRANCHES; 3.7.1 Branch Target Capture: Branch Target Buffers (BTBs); 3.7.2 Branch Prediction; 3.8 MORE ROBUST PROCESSORS: VECTOR, VERY LONG INSTRUCTION WORD (VLIW), AND SUPERSCALAR; 3.9 VECTOR PROCESSORS AND VECTOR INSTRUCTION EXTENSIONS; 3.9.1 Vector Functional Units; 3.10 VLIW PROCESSORS; 3.11 SUPERSCALAR PROCESSORS; 3.11.1 Data Dependencies; 3.11.2 Detecting Instruction Concurrency; 3.11.3 A Simple Implementation; 3.11.4 Preserving State with Out-of-Order Execution 3.12 PROCESSOR EVOLUTION AND TWO EXAMPLES |
| Record Nr. | UNINA-9910139647903321 |
Flynn Michael J
|
||
| Hoboken, : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Computer System Design : System-on-Chip
| Computer System Design : System-on-Chip |
| Autore | Flynn Michael J |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, : Wiley, 2011 |
| Descrizione fisica | 1 online resource (356 p.) |
| Disciplina | 004.1 |
| Altri autori (Persone) | LukWayne |
| Soggetto topico |
Systems on a chip
Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
9786613157355
9781283157353 1283157357 9781118009918 1118009916 9781118009925 1118009924 9781118009901 1118009908 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
COMPUTER SYSTEM DESIGN; CONTENTS; PREFACE; LIST OF ABBREVIATIONS AND ACRONYMS; 1: Introduction to the Systems Approach; 1.1 SYSTEM ARCHITECTURE: AN OVERVIEW; 1.2 COMPONENTS OF THE SYSTEM: PROCESSORS, MEMORIES, AND INTERCONNECTS; 1.3 HARDWARE AND SOFTWARE: PROGRAMMABILITY VERSUS PERFORMANCE; 1.4 PROCESSOR ARCHITECTURES; 1.4.1 Processor: A Functional View; 1.4.2 Processor: An Architectural View; 1.5 MEMORY AND ADDRESSING; 1.5.1 SOC Memory Examples; 1.5.2 Addressing: The Architecture of Memory; 1.5.3 Memory for SOC Operating System; 1.6 SYSTEM-LEVEL INTERCONNECTION; 1.6.1 Bus-Based Approach
1.6.2 Network-on-Chip Approach1.7 AN APPROACH FOR SOC DESIGN; 1.7.1 Requirements and Specifications; 1.7.2 Design Iteration; 1.8 SYSTEM ARCHITECTURE AND COMPLEXITY; 1.9 PRODUCT ECONOMICS AND IMPLICATIONS FOR SOC; 1.9.1 Factors Affecting Product Costs; 1.9.2 Modeling Product Economics and Technology Complexity: The Lesson for SOC; 1.10 DEALING WITH DESIGN COMPLEXITY; 1.10.1 Buying IP; 1.10.2 Reconfiguration; 1.11 CONCLUSIONS; 1.12 PROBLEM SET; 2: Chip Basics: Time, Area, Power, Reliability, and Configurability; 2.1 INTRODUCTION; 2.1.1 Design Trade-Offs; 2.1.2 Requirements and Specifications 2.2 CYCLE TIME2.2.1 Defining a Cycle; 2.2.2 Optimum Pipeline; 2.2.3 Performance; 2.3 DIE AREA AND COST; 2.3.1 Processor Area; 2.3.2 Processor Subunits; 2.4 IDEAL AND PRACTICAL SCALING; 2.5 POWER; 2.6 AREA-TIME-POWER TRADE-OFFS IN PROCESSOR DESIGN; 2.6.1 Workstation Processor; 2.6.2 Embedded Processor; 2.7 RELIABILITY; 2.7.1 Dealing with Physical Faults; 2.7.2 Error Detection and Correction; 2.7.3 Dealing with Manufacturing Faults; 2.7.4 Memory and Function Scrubbing; 2.8 CONFIGURABILITY; 2.8.1 Why Reconfigurable Design?; 2.8.2 Area Estimate of Reconfigurable Devices; 2.9 CONCLUSION 2.10 PROBLEM SET3: Processors; 3.1 INTRODUCTION; 3.2 PROCESSOR SELECTION FOR SOC; 3.2.1 Overview; 3.2.2 Example: Soft Processors; 3.2.3 Examples: Processor Core Selection; 3.3 BASIC CONCEPTS IN PROCESSOR ARCHITECTURE; 3.3.1 Instruction Set; 3.3.2 Some Instruction Set Conventions; 3.3.3 Branches; 3.3.4 Interrupts and Exceptions; 3.4 BASIC CONCEPTS IN PROCESSOR MICROARCHITECTURE; 3.5 BASIC ELEMENTS IN INSTRUCTION HANDLING; 3.5.1 The Instruction Decoder and Interlocks; 3.5.2 Bypassing; 3.5.3 Execution Unit; 3.6 BUFFERS: MINIMIZING PIPELINE DELAYS; 3.6.1 Mean Request Rate Buffers 3.6.2 Buffers Designed for a Fixed or Maximum Request Rate3.7 BRANCHES: REDUCING THE COST OF BRANCHES; 3.7.1 Branch Target Capture: Branch Target Buffers (BTBs); 3.7.2 Branch Prediction; 3.8 MORE ROBUST PROCESSORS: VECTOR, VERY LONG INSTRUCTION WORD (VLIW), AND SUPERSCALAR; 3.9 VECTOR PROCESSORS AND VECTOR INSTRUCTION EXTENSIONS; 3.9.1 Vector Functional Units; 3.10 VLIW PROCESSORS; 3.11 SUPERSCALAR PROCESSORS; 3.11.1 Data Dependencies; 3.11.2 Detecting Instruction Concurrency; 3.11.3 A Simple Implementation; 3.11.4 Preserving State with Out-of-Order Execution 3.12 PROCESSOR EVOLUTION AND TWO EXAMPLES |
| Altri titoli varianti | System-on-chip |
| Record Nr. | UNINA-9910826714103321 |
|
Flynn Michael J
|
||
| Hoboken, : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Field Programmable Logic and Applications [[electronic resource] ] : 7th International Workshop, FPL '97, London, UK, September, 1-3, 1997, Proceedings. / / edited by Wayne Luk, Peter Y.K. Cheung, Manfred Glesner
| Field Programmable Logic and Applications [[electronic resource] ] : 7th International Workshop, FPL '97, London, UK, September, 1-3, 1997, Proceedings. / / edited by Wayne Luk, Peter Y.K. Cheung, Manfred Glesner |
| Edizione | [1st ed. 1997.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1997 |
| Descrizione fisica | 1 online resource (XII, 512 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computer engineering
Architecture, Computer Programming languages (Electronic computers) Computer hardware Computational complexity Mathematical logic Computer Engineering Computer System Implementation Programming Languages, Compilers, Interpreters Computer Hardware Complexity Mathematical Logic and Formal Languages |
| ISBN | 3-540-69557-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Multicontext dynamic reconfiguration and real-time probing on a novel mixed signal programmable device with on-chip microprocessor -- CAD-oriented FPGA and dedicated CAD system for telecommunications -- Rothko: A three dimensional FPGA architecture, its fabrication, and design tools -- Extending dynamic circuit switching to meet the challenges of new FPGA architectures -- Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs -- Implementation of pipelined multipliers on Xilinx FPGAs -- The XC620ODS development system -- Thermal monitoring on FPGAs using ring-oscillators -- A reconfigurable approach to low cost media processing -- Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research -- Stream synthesis for a wormhole run-time reconfigurable platform -- Pipeline morphing and virtual pipelines -- Parallel graph colouring using FPGAs -- Run-time compaction of FPGA designs -- Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement -- A case study of partially evaluated hardware circuits: Key-specific DES -- Run-time parameterised circuits for the Xilinx XC6200 -- Automatic identification of swappable logic units in XC6200 circuitry -- Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic -- Exploiting reconfigurability through domain-specific systems -- Technology mapping by binate covering -- VPR: a new packing, placement and routing tool for FPGA research -- Technology mapping of heterogeneous LUT-based FPGAs -- Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs -- Technology mapping of LUT based FPGAs for delay optimisation -- Automatic Mapping of Algorithms onto multiple FPGA-SRAM Modules -- FPLD HDL synthesis employing high-level evolutionary algorithm optimisation -- An hardware/software partitioning algorithm for custom computing machines -- The Java Environment for Reconfigurable Computing -- Data scheduling to increase performance of parallel accelerators -- An operating system for custom computing machines based on the Xputer paradigm -- Fast parallel implementation of DFT using configurable devices -- Enhancing fixed point DSP processor performance by adding CPLD's as coprocessing elements -- A case study of algorithm implementation in reconfigurable hardware and software -- A reconfigurable data-localised array for morphological algorithms -- Virtual radix array processors (V-RaAP) -- An FPGA implementation of a matched filter detector for spread spectrum communications systems -- An NTSC and PAL closed caption processor -- A 800Mpixel/sec reconfigurable image correlator on XC6216 -- A reconfigurable coprocessor for a PCI-based real time computer vision system -- Real-time stereopsis using FPGAs -- FPGAs Implementation of a digital IQ demodulator using VHDL -- Hardware compilation, configurable platforms and ASICs for self-validating sensors -- PostScript™ rendering with virtual hardware -- P4: A platform for FPGA implementation of protocol boosters -- Satisfiability on reconfigurable hardware -- Auto-configurable array for GCD computation -- Structural versus algorithmic approaches for efficient adders on xilinx 5200 FPGA -- FPGA implementation of real-time digital controllers using on-line arithmetic -- A prototyping environment for fuzzy controllers -- A reconfigurable sensor-data processing system for personal robots. |
| Record Nr. | UNISA-996465493603316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Field Programmable Logic and Applications [[electronic resource] ] : 7th International Workshop, FPL '97, London, UK, September, 1-3, 1997, Proceedings. / / edited by Wayne Luk, Peter Y.K. Cheung, Manfred Glesner
| Field Programmable Logic and Applications [[electronic resource] ] : 7th International Workshop, FPL '97, London, UK, September, 1-3, 1997, Proceedings. / / edited by Wayne Luk, Peter Y.K. Cheung, Manfred Glesner |
| Edizione | [1st ed. 1997.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1997 |
| Descrizione fisica | 1 online resource (XII, 512 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computer engineering
Computer architecture Programming languages (Electronic computers) Computer hardware Computational complexity Logic, Symbolic and mathematical Computer Engineering Computer System Implementation Programming Languages, Compilers, Interpreters Computer Hardware Complexity Mathematical Logic and Formal Languages |
| ISBN | 3-540-69557-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Multicontext dynamic reconfiguration and real-time probing on a novel mixed signal programmable device with on-chip microprocessor -- CAD-oriented FPGA and dedicated CAD system for telecommunications -- Rothko: A three dimensional FPGA architecture, its fabrication, and design tools -- Extending dynamic circuit switching to meet the challenges of new FPGA architectures -- Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs -- Implementation of pipelined multipliers on Xilinx FPGAs -- The XC620ODS development system -- Thermal monitoring on FPGAs using ring-oscillators -- A reconfigurable approach to low cost media processing -- Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research -- Stream synthesis for a wormhole run-time reconfigurable platform -- Pipeline morphing and virtual pipelines -- Parallel graph colouring using FPGAs -- Run-time compaction of FPGA designs -- Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement -- A case study of partially evaluated hardware circuits: Key-specific DES -- Run-time parameterised circuits for the Xilinx XC6200 -- Automatic identification of swappable logic units in XC6200 circuitry -- Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic -- Exploiting reconfigurability through domain-specific systems -- Technology mapping by binate covering -- VPR: a new packing, placement and routing tool for FPGA research -- Technology mapping of heterogeneous LUT-based FPGAs -- Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs -- Technology mapping of LUT based FPGAs for delay optimisation -- Automatic Mapping of Algorithms onto multiple FPGA-SRAM Modules -- FPLD HDL synthesis employing high-level evolutionary algorithm optimisation -- An hardware/software partitioning algorithm for custom computing machines -- The Java Environment for Reconfigurable Computing -- Data scheduling to increase performance of parallel accelerators -- An operating system for custom computing machines based on the Xputer paradigm -- Fast parallel implementation of DFT using configurable devices -- Enhancing fixed point DSP processor performance by adding CPLD's as coprocessing elements -- A case study of algorithm implementation in reconfigurable hardware and software -- A reconfigurable data-localised array for morphological algorithms -- Virtual radix array processors (V-RaAP) -- An FPGA implementation of a matched filter detector for spread spectrum communications systems -- An NTSC and PAL closed caption processor -- A 800Mpixel/sec reconfigurable image correlator on XC6216 -- A reconfigurable coprocessor for a PCI-based real time computer vision system -- Real-time stereopsis using FPGAs -- FPGAs Implementation of a digital IQ demodulator using VHDL -- Hardware compilation, configurable platforms and ASICs for self-validating sensors -- PostScript™ rendering with virtual hardware -- P4: A platform for FPGA implementation of protocol boosters -- Satisfiability on reconfigurable hardware -- Auto-configurable array for GCD computation -- Structural versus algorithmic approaches for efficient adders on xilinx 5200 FPGA -- FPGA implementation of real-time digital controllers using on-line arithmetic -- A prototyping environment for fuzzy controllers -- A reconfigurable sensor-data processing system for personal robots. |
| Record Nr. | UNINA-9910144916003321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Field-Programmable Logic and Applications [[electronic resource] ] : 5th International Workshop, FPL '95, Oxford, United Kingdom, August 29 - September 1, 1995. Proceedings / / edited by Will Moore, Wayne Luk
| Field-Programmable Logic and Applications [[electronic resource] ] : 5th International Workshop, FPL '95, Oxford, United Kingdom, August 29 - September 1, 1995. Proceedings / / edited by Will Moore, Wayne Luk |
| Edizione | [1st ed. 1995.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1995 |
| Descrizione fisica | 1 online resource (XII, 456 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Software engineering Logic design Electronics Microelectronics Computer-aided engineering Electrical engineering Computer System Implementation Software Engineering/Programming and Operating Systems Logic Design Electronics and Microelectronics, Instrumentation Computer-Aided Engineering (CAD, CAE) and Design Communications Engineering, Networks |
| ISBN | 3-540-44786-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | The design of a new FPGA architecture -- Migration of a dual granularity globally interconnected PLD architecture to a 0.5? TLM process -- Self-timed FPGA systems -- The XC6200 FastMap™ processor interface -- The Teramac configurable compute engine -- Telecommunication-oriented FPGA and dedicated CAD system -- A configurable logic processor for machine vision -- Extending DSP-boards with FPGA-based structures of interconnection -- High-speed region detection and labeling using an FPGA-based custom computing platform -- Using FPGAS as control support in MIMD executions -- Customised hardware based on the REDOC III algorithm for high performance data ciphering -- Using reconfigurable hardware to speed up product development and performance -- Creation of hardware objects in a reconfigurable computer -- Rapid hardware prototyping of Digital Signal Processing systems using Field Programmable Gate Arrays -- Delay minimal mapping of RTL structures onto LUT based FPGAs -- Some notes on power management on FPGA-based systems -- An automatic technique for realising user interaction processing in PLD based systems -- Proper use of hierarchy in HDL-based high density FGPA design -- Compiling regular arrays onto FPGAs -- Compiling Ruby into FPGAs -- The CSYN verilog compiler and other tools -- A VHDL design methodology for FPGAs -- VHDL-based rapid hardware prototyping using FPGA technology -- Integer programming for partitioning in software oriented codesign -- Test standard serves dual role as on-board programming solution -- Advanced method for industry related education with an FPGA design self-learning kit -- FPGA implementation of a rational adder -- FPLD-implementation of computations over finite fields GF(2m) with applications to error control coding -- Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs -- Implementation of a 2-D fast Fourier transform on an FPGA-based custom computing machine -- An assessment of the suitability of FPGA-based systems for use in digital signal processing -- An FPGA prototype for a multiplierless FIR filter built using the logarithmic number system -- Bit-serial FIR filters with CSD coefficients for FPGAs -- A self-validating temperature sensor implemented in FPGAs -- Developing interface libraries for reconfigurable data acquisition boards -- Prototype generation of application specific embedded controllers for microsystems -- A hardware genetic algorithm for the traveling salesman problem on Splash 2 -- Modular architecture for real-time astronomical image processing with FPGA -- A programmable I/O system for real-time AC drive control applications -- Reconfigurable logic for fault tolerance -- Supercomputing with reconfigurable architectures -- Automatic synthesis of parallel programs targeted to dynamically reconfigurable logic arrays -- Prototyping environment for dynamically reconfigurable logic -- Implementation approaches for reconfigurable logic applications -- Use of reconfigurability in variable-length code detection at video rates -- Classification and performance of reconfigurable architectures. |
| Record Nr. | UNISA-996466143303316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1995 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Machine learning under resource constraints Fundamentals / / edited by Katharina Morik and Peter Marwedel
| Machine learning under resource constraints Fundamentals / / edited by Katharina Morik and Peter Marwedel |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Berlin ; ; Boston : , : De Gruyter, , [2023] |
| Descrizione fisica | 1 online resource (xiii, 491 pages) : illustrations (chiefly colour) |
| Disciplina | 006.31 |
| Collana | De Gruyter STEM |
| Soggetto topico |
Machine learning
SCIENCE / Chemistry / General |
| Soggetto non controllato |
Artificial Intelligence
Big Data and Machine Learning Cyber-physical systems Data mining for Ubiquitous System Software Embedded Systems and Machine Learning Highly Distributed Data ML on Small devices Machine learning for knowledge discovery Machine learning in high-energy physics Resource-Aware Machine Learning Resource-Constrained Data Analysis |
| ISBN | 3-11-078594-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | ; 1 Introduction / Katharina Morik, Jian-Jia Chen -- ; 1.1 Embedded Systems and Sustainability -- ; 1.2 The Energy Consumption of Machine Learning -- ; 1.3 Memory Demands of Machine Learning -- ; 1.4 Structure of this Book -- ; 2 Data Gathering and Resource Measuring -- ; 2.1 Declarative Stream-Based Acquisition and Processing of OS Data with kCQL / Christoph Borchert, Jochen Streicher, Alexander Lochmann,Olaf Spinczyk -- ; 2.2 PhyNetLab Test Bed / Mojtaba Masoudinejad, Markus Buschhoff -- ; 2.3 Zero-Power/Low-Power Sensing / Andres Gomez, Lars Suter, Simon Mayer -- ; 3 Streaming Data, Small Devices -- ; 3.1 Summary Extraction from Streams / Sebastian Buschjäger, Katharina Morik -- ; 3.2 Coresets and Sketches for Regression Problems on Data Streams and Distributed Data / Alexander Munteanu -- ; 4 Structured Data -- ; 4.1 Spatio-Temporal Random Fields / Nico Piatkowski, Katharina Morik -- ; 4.2 The Weisfeiler-Leman Method for Machine Learning with Graphs / Nils Kriege, Christopher Morris -- ; 4.3 Deep Graph Representation Learning / Matthias Fey, Frank Weichert -- ; 4.4 High-Quality Parallel Max-Cut Approximation Algorithms for Shared Memory / Nico Bertram, Jonas Ellert, Johannes Fischer -- ; 4.5 Millions of Formulas / Lukas Pfahler -- ; 5 Cluster Analysis -- ; 5.1 Sparse Partitioning Around Medoids / Lars Lenssen, Erich Schubert -- ; 5.2 Clustering of Polygonal Curves and Time Series / Amer Krivošija -- ; 5.3 Data Aggregation for Hierarchical Clustering / Erich Schubert, Andreas Lang -- ; 5.4 Matrix Factorization with Binary Constraints / Sibylle Hess ; 6 Hardware-Aware Execution -- ; 6.1 FPGA-Based Backpropagation Engine for Feed-Forward Neural Networks / Wayne Luk, Ce Guo -- ; 6.2 Processor-Specific Code Transformation / Henning Funke, Jens Teubner -- ; 6.3 Extreme Multicore Classification / Erik Schultheis, Rohit Babbar -- ; 6.4 Optimization of ML on Modern Multicore Systems / Helena Kotthaus, Peter Marwedel -- 7 Memory Awareness -- ; 7.1 Efficient Memory Footprint Reduction / Helena Kotthaus, Peter Marwedel -- ; 7.2 Machine Learning Based on Emerging Memories / Mikail Yayla, Sebastian Buschjäger, Hussam Amrouch -- ; 7.3 Cache-Friendly Execution of Tree Ensembles / Sebastian Buschjäger, Kuan-Hsun Chen -- ; 8 Communication Awareness -- ; 8.1 Timing-Predictable Learning and Multiprocessor Synchronization / Kuan-Hsun Chen, Junjie Shi -- ; 8.2 Communication Architecture for Heterogeneous Hardware / Henning Funke, Jens Teubner -- ; 9 Energy Awareness -- ; 9.1 Integer Exponential Families / Nico Piatkowski -- ; 9.2 Power Consumption Analysis and Uplink Transmission Power / Robert Falkenberg. |
| Record Nr. | UNISA-996503570003316 |
| Berlin ; ; Boston : , : De Gruyter, , [2023] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Synthesis and optimization of DSP algorithms / / by George A. Constantinides, Peter Y.K. Cheung and Wayne Luk
| Synthesis and optimization of DSP algorithms / / by George A. Constantinides, Peter Y.K. Cheung and Wayne Luk |
| Autore | Constantinides George A. <1975-> |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Boston, : Kluwer Academic Publishers, 2004 |
| Descrizione fisica | 1 online resource (170 pages) |
| Disciplina | 621.382/2 |
| Altri autori (Persone) |
CheungPeter Y. K
LukWayne |
| Soggetto topico |
Signal processing - Digital techniques
Digital communications - Equipment and supplies - Design - Data processing |
| ISBN |
9781402079313
1402079311 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Intro -- Contents. |
| Record Nr. | UNINA-9910964172303321 |
|
Constantinides George A. <1975->
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| Boston, : Kluwer Academic Publishers, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Synthesis and Optimization of DSP Algorithms
| Synthesis and Optimization of DSP Algorithms |
| Autore | Constantinides George A |
| Pubbl/distr/stampa | Springer US |
| Altri autori (Persone) |
CheungPeter Y. K
LukWayne |
| ISBN | 1-4020-7931-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910450809403321 |
|
Constantinides George A
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||
| Springer US | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Synthesis and optimization of DSP algorithms / / by George A. Constantinides, Peter Y.K. Cheung, and Wayne Luk
| Synthesis and optimization of DSP algorithms / / by George A. Constantinides, Peter Y.K. Cheung, and Wayne Luk |
| Autore | Constantinides George A |
| Pubbl/distr/stampa | Springer US |
| Disciplina | 621.382/2 |
| Altri autori (Persone) |
CheungPeter Y. K
LukWayne |
| Soggetto topico |
Signal processing - Digital techniques
Digital communications - Equipment and supplies - Design - Data processing |
| ISBN | 1-4020-7931-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910777446803321 |
|
Constantinides George A
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| Springer US | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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