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Arithmetic and logic in computer systems [[electronic resource] /] / Mi Lu
| Arithmetic and logic in computer systems [[electronic resource] /] / Mi Lu |
| Autore | Lu Mi |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, NJ, : Wiley-Interscience, c2004 |
| Descrizione fisica | 1 online resource (270 p.) |
| Disciplina | 004/.01/51 |
| Collana | Wiley Series in Microwave and Optical Engineering |
| Soggetto topico |
Computer arithmetic
Logic programming |
| ISBN |
1-280-25336-3
9786610253364 0-470-35774-6 0-471-72621-4 0-471-72851-9 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Arithmetic and Logic in Computer Systems; Contents; Preface; List of Figures; List of Figures; List of Tables; List of Tables; About the Author; 1 Computer Number Systems; 1.1 Conventional Radix Number System; 1.2 Conversion of Radix Numbers; 1.3 Representation of Signed Numbers; 1.3.1 Sign-Magnitude; 1.3.2 Diminished Radix Complement; 1.3.3 Radix Complement; 1.4 Signed-Digit Number System; 1.1 Numbers Represented by 4 bits in Different Number Systems; 1.2 Finding Signed Digits; 1.5 Floating-point Number Representation; 1.5.1 Normalization; 1.5.2 Bias; 1.1 Floating-point Representation
1.2 Range of the Numbers1.3 Precision of Floating-Point Numbers; 1.4 Double Precision Floating-Point Representation; 1.3 Reserved Representation in IEEE Standard; 1.6 Residue Number System; 1.7 Logarithmic Number System; References; Problems; 2 Addition and Subtraction; 2.1 Single-Bit Adders; 2.1.1 Logical Devices; 2.1 AOI Function; 2.1 Delay Time and Area of Logic Gates; 2.2 Decoder and Multiplexer; 2.1.2 Single-Bit Half-Adder and Full-Adders; 2.3 Single-Bit Half-Adder; 2.2 Logic Function of a Half-Adder; 2.3 Logic Function of a Full-Adder; 2.4 Design of Full-Adder; 2.2 Negation 2.4 Single-Bit Subtractor2.2.1 Negation in One's Complement System; 2.5 Single-Bit Subtrator; 2.5 Negation in One's Complement System; 2.6 Negation in One's Complement System; 2.2.2 Negation in Two's Complement System; 2.7 Negation in Two's Complement System; 2.3 Subtraction through Addition; 2.8 Subtraction through Addition; 2.9 One-Bit Adder/Subtractor; 2.4 Over flow; 2.5 Ripple Carry Adders; 2.5.1 Two's Complement Addition; 2.10 Two's Complement Addition/Subtraction; 2.5.2 One's Complement Addition; 2.11 One's Complement Addition/Subtraction; 2.5.3 Sign-Magnitude Addition 2.12 Block Diagram of Sign-Magnitude Addition/SubtractionReferences; 2.13 Sign-Magnitude Addition/Subtraction; Problems; 3 High-Speed Adder; 3.1 Conditional-Sum Addition; 3.1 Conditional-Sum Addition; 3.2 Carry-Completion Sensing Addition; 3.2 Conditional-Sum Adder; 3.3 Generation and Transmission of Carries; 3.4 Construction of Carry-Completion Sensing Adder; 3.3 Carry-Lookahead Addition (CLA); 3.3.1 Carry-Lookahead Adder; 3.3.2 Block Carry Lookahead Adder; 3.5 Carry-Lookahead Adder; 3.6 Block Carry-Lookahead Adder; 3.4 Carry-Save Adders (CSA); 3.7 Carry-Save Adder; 3.8 Carry-Save Adder Tree 3.9 Two Types of Parallelization in Multi-Operand Addition3.5 Bit-Partitioned Multiple Addition; 3.1 Maximum Inputs of CSA Trees; 3.10 Bit-Partitioned Multiple Addition; References; Problems; 3.11 Carry-Completion Sensing Adder; 3.12 Carry-Save Adder; 3.13 Bit-Partitional Adder; 4 Sequential Multiplication; 4.1 Add-and-shift Approach; 4.1 Hardware for Sequential Multiplication; 4.2 Register Occupation; 4.2 Indirect Multiplication Schemes; 4.2. 1 Unsigned Number Multiplication; 4.2.2 Sign-Magnitude Number Multiplication; 4.2.3 One's Complement Number Multiplication 4.3 Unsigned Number Multiplication |
| Record Nr. | UNINA-9910145764203321 |
Lu Mi
|
||
| Hoboken, NJ, : Wiley-Interscience, c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Arithmetic and logic in computer systems / / Mi Lu
| Arithmetic and logic in computer systems / / Mi Lu |
| Autore | Lu Mi |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, NJ, : Wiley-Interscience, c2004 |
| Descrizione fisica | 1 online resource (270 p.) |
| Disciplina | 004/.01/51 |
| Collana | Wiley Series in Microwave and Optical Engineering |
| Soggetto topico |
Computer arithmetic
Logic programming |
| ISBN |
9786610253364
9781280253362 1280253363 9780470357743 0470357746 9780471726210 0471726214 9780471728511 0471728519 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Arithmetic and Logic in Computer Systems; Contents; Preface; List of Figures; List of Figures; List of Tables; List of Tables; About the Author; 1 Computer Number Systems; 1.1 Conventional Radix Number System; 1.2 Conversion of Radix Numbers; 1.3 Representation of Signed Numbers; 1.3.1 Sign-Magnitude; 1.3.2 Diminished Radix Complement; 1.3.3 Radix Complement; 1.4 Signed-Digit Number System; 1.1 Numbers Represented by 4 bits in Different Number Systems; 1.2 Finding Signed Digits; 1.5 Floating-point Number Representation; 1.5.1 Normalization; 1.5.2 Bias; 1.1 Floating-point Representation
1.2 Range of the Numbers1.3 Precision of Floating-Point Numbers; 1.4 Double Precision Floating-Point Representation; 1.3 Reserved Representation in IEEE Standard; 1.6 Residue Number System; 1.7 Logarithmic Number System; References; Problems; 2 Addition and Subtraction; 2.1 Single-Bit Adders; 2.1.1 Logical Devices; 2.1 AOI Function; 2.1 Delay Time and Area of Logic Gates; 2.2 Decoder and Multiplexer; 2.1.2 Single-Bit Half-Adder and Full-Adders; 2.3 Single-Bit Half-Adder; 2.2 Logic Function of a Half-Adder; 2.3 Logic Function of a Full-Adder; 2.4 Design of Full-Adder; 2.2 Negation 2.4 Single-Bit Subtractor2.2.1 Negation in One's Complement System; 2.5 Single-Bit Subtrator; 2.5 Negation in One's Complement System; 2.6 Negation in One's Complement System; 2.2.2 Negation in Two's Complement System; 2.7 Negation in Two's Complement System; 2.3 Subtraction through Addition; 2.8 Subtraction through Addition; 2.9 One-Bit Adder/Subtractor; 2.4 Over flow; 2.5 Ripple Carry Adders; 2.5.1 Two's Complement Addition; 2.10 Two's Complement Addition/Subtraction; 2.5.2 One's Complement Addition; 2.11 One's Complement Addition/Subtraction; 2.5.3 Sign-Magnitude Addition 2.12 Block Diagram of Sign-Magnitude Addition/SubtractionReferences; 2.13 Sign-Magnitude Addition/Subtraction; Problems; 3 High-Speed Adder; 3.1 Conditional-Sum Addition; 3.1 Conditional-Sum Addition; 3.2 Carry-Completion Sensing Addition; 3.2 Conditional-Sum Adder; 3.3 Generation and Transmission of Carries; 3.4 Construction of Carry-Completion Sensing Adder; 3.3 Carry-Lookahead Addition (CLA); 3.3.1 Carry-Lookahead Adder; 3.3.2 Block Carry Lookahead Adder; 3.5 Carry-Lookahead Adder; 3.6 Block Carry-Lookahead Adder; 3.4 Carry-Save Adders (CSA); 3.7 Carry-Save Adder; 3.8 Carry-Save Adder Tree 3.9 Two Types of Parallelization in Multi-Operand Addition3.5 Bit-Partitioned Multiple Addition; 3.1 Maximum Inputs of CSA Trees; 3.10 Bit-Partitioned Multiple Addition; References; Problems; 3.11 Carry-Completion Sensing Adder; 3.12 Carry-Save Adder; 3.13 Bit-Partitional Adder; 4 Sequential Multiplication; 4.1 Add-and-shift Approach; 4.1 Hardware for Sequential Multiplication; 4.2 Register Occupation; 4.2 Indirect Multiplication Schemes; 4.2. 1 Unsigned Number Multiplication; 4.2.2 Sign-Magnitude Number Multiplication; 4.2.3 One's Complement Number Multiplication 4.3 Unsigned Number Multiplication |
| Record Nr. | UNINA-9910817402703321 |
|
Lu Mi
|
||
| Hoboken, NJ, : Wiley-Interscience, c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||