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Designing SOCs with configured cores [[electronic resource] ] : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson
| Designing SOCs with configured cores [[electronic resource] ] : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson |
| Autore | Leibson Steve |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (341 p.) |
| Disciplina | 621.3815 |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Embedded computer systems - Design and construction
Systems on a chip - Design and construction |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-96685-8
9786610966851 0-08-047245-1 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; About the Author; Title page; Copyright Page; Table of contents; Foreword; Preface; Acknowledgements; 1 Introduction to 21st-Century SOC Design; 1.1 The Start of Something Big; 1.2 Few Pins = Massive Multiplexing; 1.3 Third Time's a Charm; 1.4 The Microprocessor: A Universal System Building Block; 1.5 The Consequences of Performance-in the Macro World; 1.6 Increasing Processor Performance in the Micro World; 1.7 I/O Bandwidth and Processor Core Clock Rate; 1.8 Multitasking and Processor Core Clock Rate; 1.9 System-Design Evolution
1.10 Heterogeneous- and Homogeneous-Processor System-Design Approaches1.11 The Rise of MPSOC Design; 1.12 Veering Away from Processor Multitasking in SOC Design; 1.13 Processors: The Original, Reusable Design Block; 1.14 A Closer Look at 21st-Century Processor Cores for SOC Design; Bibliography; 2 The SOC Design Flow; 2.1 System-Design Goals; 2.2 The ASIC Design Flow; 2.3 The ad-hoc SOC Design Flow; 2.4 A Systematic MPSOC Design Flow; 2.5 Computational Alternatives; 2.6 Communication Alternatives; 2.7 Cycle-Accurate System Simulation; 2.8 Detailed Implementation 2.9 Summary: Handling SOC ComplexityBibliography; 3 Xtensa Architectural Basics; 3.1 Introduction to Configurable Processor Architectures; 3.2 Xtensa Registers; 3.3 Register Windowing; 3.4 The Xtensa Program Counter; 3.5 Memory Address Space; 3.6 Bit and Byte Ordering; 3.7 Base Xtensa Instructions; 3.8 Benchmarking the Xtensa Core ISA; Bibliography; 4 Basic Processor Configurability; 4.1 Processor Generation; 4.2 Xtensa Processor Block Diagram; 4.3 Pre-Configured Processor Cores; 4.4 Basics of TIE; 4.5 TIE Instructions; 4.6 Improving Application Performance Using TIE 4.7 TIE Registers and Register Files4.8 TIE Ports; 4.9 TIE Queue Interfaces; 4.10 Combining Instruction Extensions with Queues; 4.11 Diamond Standard Series Processor Cores-Dealing with Complexity; Bibliography; 5 MPSOC System Architectures and Design Tools; 5.1 SOC Architectural Evolution; 5.2 The Consequences of Architectural Evolution; 5.3 Memory Interfaces; 5.4 Memory Caches; 5.5 Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF; 5.6 The PIF; 5.7 Ports and Queue Interfaces; 5.8 SOC Connection Topologies; 5.9 Shared-Memory Topologies; 5.10 Direct Port-Connected Topologies 5.11 Queue-Based System Topologies5.12 Existing Design Tools for Complex SOC Designs; 5.13 MPSOC Architectural-Design Tools; 5.14 Platform Design; 5.15 An MPSOC-Design Tool; 5.16 MPSOC System-Level Simulation Example; 5.17 SOC Design in the 21st Century; Bibliography; 6 Introduction to Diamond Standard Series Processor Cores; 6.1 The Diamond Standard Series of 32-bit Processor Cores; 6.2 Diamond Standard Series Software-Development Tools; 6.3 Diamond Standard Series Feature Summary; 6.4 Diamond Standard Series Processor Core Hardware Overview and Comparison 6.5 Diamond-Core Local-Memory Interfaces |
| Record Nr. | UNINA-9910458596803321 |
Leibson Steve
|
||
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designing SOCs with configured cores [[electronic resource] ] : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson
| Designing SOCs with configured cores [[electronic resource] ] : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson |
| Autore | Leibson Steve |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (341 p.) |
| Disciplina | 621.3815 |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Embedded computer systems - Design and construction
Systems on a chip - Design and construction |
| ISBN |
1-280-96685-8
9786610966851 0-08-047245-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; About the Author; Title page; Copyright Page; Table of contents; Foreword; Preface; Acknowledgements; 1 Introduction to 21st-Century SOC Design; 1.1 The Start of Something Big; 1.2 Few Pins = Massive Multiplexing; 1.3 Third Time's a Charm; 1.4 The Microprocessor: A Universal System Building Block; 1.5 The Consequences of Performance-in the Macro World; 1.6 Increasing Processor Performance in the Micro World; 1.7 I/O Bandwidth and Processor Core Clock Rate; 1.8 Multitasking and Processor Core Clock Rate; 1.9 System-Design Evolution
1.10 Heterogeneous- and Homogeneous-Processor System-Design Approaches1.11 The Rise of MPSOC Design; 1.12 Veering Away from Processor Multitasking in SOC Design; 1.13 Processors: The Original, Reusable Design Block; 1.14 A Closer Look at 21st-Century Processor Cores for SOC Design; Bibliography; 2 The SOC Design Flow; 2.1 System-Design Goals; 2.2 The ASIC Design Flow; 2.3 The ad-hoc SOC Design Flow; 2.4 A Systematic MPSOC Design Flow; 2.5 Computational Alternatives; 2.6 Communication Alternatives; 2.7 Cycle-Accurate System Simulation; 2.8 Detailed Implementation 2.9 Summary: Handling SOC ComplexityBibliography; 3 Xtensa Architectural Basics; 3.1 Introduction to Configurable Processor Architectures; 3.2 Xtensa Registers; 3.3 Register Windowing; 3.4 The Xtensa Program Counter; 3.5 Memory Address Space; 3.6 Bit and Byte Ordering; 3.7 Base Xtensa Instructions; 3.8 Benchmarking the Xtensa Core ISA; Bibliography; 4 Basic Processor Configurability; 4.1 Processor Generation; 4.2 Xtensa Processor Block Diagram; 4.3 Pre-Configured Processor Cores; 4.4 Basics of TIE; 4.5 TIE Instructions; 4.6 Improving Application Performance Using TIE 4.7 TIE Registers and Register Files4.8 TIE Ports; 4.9 TIE Queue Interfaces; 4.10 Combining Instruction Extensions with Queues; 4.11 Diamond Standard Series Processor Cores-Dealing with Complexity; Bibliography; 5 MPSOC System Architectures and Design Tools; 5.1 SOC Architectural Evolution; 5.2 The Consequences of Architectural Evolution; 5.3 Memory Interfaces; 5.4 Memory Caches; 5.5 Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF; 5.6 The PIF; 5.7 Ports and Queue Interfaces; 5.8 SOC Connection Topologies; 5.9 Shared-Memory Topologies; 5.10 Direct Port-Connected Topologies 5.11 Queue-Based System Topologies5.12 Existing Design Tools for Complex SOC Designs; 5.13 MPSOC Architectural-Design Tools; 5.14 Platform Design; 5.15 An MPSOC-Design Tool; 5.16 MPSOC System-Level Simulation Example; 5.17 SOC Design in the 21st Century; Bibliography; 6 Introduction to Diamond Standard Series Processor Cores; 6.1 The Diamond Standard Series of 32-bit Processor Cores; 6.2 Diamond Standard Series Software-Development Tools; 6.3 Diamond Standard Series Feature Summary; 6.4 Diamond Standard Series Processor Core Hardware Overview and Comparison 6.5 Diamond-Core Local-Memory Interfaces |
| Record Nr. | UNINA-9910784654303321 |
|
Leibson Steve
|
||
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designing SOCs with configured cores : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson
| Designing SOCs with configured cores : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson |
| Autore | Leibson Steve |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (341 p.) |
| Disciplina | 621.3815 |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Embedded computer systems - Design and construction
Systems on a chip - Design and construction |
| ISBN |
1-280-96685-8
9786610966851 0-08-047245-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; About the Author; Title page; Copyright Page; Table of contents; Foreword; Preface; Acknowledgements; 1 Introduction to 21st-Century SOC Design; 1.1 The Start of Something Big; 1.2 Few Pins = Massive Multiplexing; 1.3 Third Time's a Charm; 1.4 The Microprocessor: A Universal System Building Block; 1.5 The Consequences of Performance-in the Macro World; 1.6 Increasing Processor Performance in the Micro World; 1.7 I/O Bandwidth and Processor Core Clock Rate; 1.8 Multitasking and Processor Core Clock Rate; 1.9 System-Design Evolution
1.10 Heterogeneous- and Homogeneous-Processor System-Design Approaches1.11 The Rise of MPSOC Design; 1.12 Veering Away from Processor Multitasking in SOC Design; 1.13 Processors: The Original, Reusable Design Block; 1.14 A Closer Look at 21st-Century Processor Cores for SOC Design; Bibliography; 2 The SOC Design Flow; 2.1 System-Design Goals; 2.2 The ASIC Design Flow; 2.3 The ad-hoc SOC Design Flow; 2.4 A Systematic MPSOC Design Flow; 2.5 Computational Alternatives; 2.6 Communication Alternatives; 2.7 Cycle-Accurate System Simulation; 2.8 Detailed Implementation 2.9 Summary: Handling SOC ComplexityBibliography; 3 Xtensa Architectural Basics; 3.1 Introduction to Configurable Processor Architectures; 3.2 Xtensa Registers; 3.3 Register Windowing; 3.4 The Xtensa Program Counter; 3.5 Memory Address Space; 3.6 Bit and Byte Ordering; 3.7 Base Xtensa Instructions; 3.8 Benchmarking the Xtensa Core ISA; Bibliography; 4 Basic Processor Configurability; 4.1 Processor Generation; 4.2 Xtensa Processor Block Diagram; 4.3 Pre-Configured Processor Cores; 4.4 Basics of TIE; 4.5 TIE Instructions; 4.6 Improving Application Performance Using TIE 4.7 TIE Registers and Register Files4.8 TIE Ports; 4.9 TIE Queue Interfaces; 4.10 Combining Instruction Extensions with Queues; 4.11 Diamond Standard Series Processor Cores-Dealing with Complexity; Bibliography; 5 MPSOC System Architectures and Design Tools; 5.1 SOC Architectural Evolution; 5.2 The Consequences of Architectural Evolution; 5.3 Memory Interfaces; 5.4 Memory Caches; 5.5 Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF; 5.6 The PIF; 5.7 Ports and Queue Interfaces; 5.8 SOC Connection Topologies; 5.9 Shared-Memory Topologies; 5.10 Direct Port-Connected Topologies 5.11 Queue-Based System Topologies5.12 Existing Design Tools for Complex SOC Designs; 5.13 MPSOC Architectural-Design Tools; 5.14 Platform Design; 5.15 An MPSOC-Design Tool; 5.16 MPSOC System-Level Simulation Example; 5.17 SOC Design in the 21st Century; Bibliography; 6 Introduction to Diamond Standard Series Processor Cores; 6.1 The Diamond Standard Series of 32-bit Processor Cores; 6.2 Diamond Standard Series Software-Development Tools; 6.3 Diamond Standard Series Feature Summary; 6.4 Diamond Standard Series Processor Core Hardware Overview and Comparison 6.5 Diamond-Core Local-Memory Interfaces |
| Record Nr. | UNINA-9910808929603321 |
|
Leibson Steve
|
||
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||