Learning from VLSI Design Experience / / by Weng Fook Lee |
Autore | Lee Weng Fook |
Edizione | [1st ed. 2019.] |
Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
Descrizione fisica | 1 online resource (xxix, 214 pages) |
Disciplina | 621.395 |
Soggetto topico |
Electronic circuits
Microprocessors Electronics Microelectronics Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
ISBN | 3-030-03238-8 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Chapter 1. Introduction -- Chapter 2. Design Methodology and Flow -- Chapter 3. Multiple Clock Design -- Chapter 4. Latch Inference -- Chapter 5. Design for Test -- Chapter 6. Signed Verilog -- Chapter 7. State Machine -- Chapter 8. RTL Coding Guideline -- Chapter 9. Code Coverage. . |
Record Nr. | UNINA-9910337645003321 |
Lee Weng Fook | ||
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Verilog Coding for Logic Synthesis |
Autore | Lee Weng Fook |
Edizione | [1st edition] |
Pubbl/distr/stampa | [Place of publication not identified], : Wiley Interscience Imprint, 2003 |
Descrizione fisica | 1 online resource (1 v.) : ill |
Disciplina | 621.395 |
Soggetto topico |
Digital electronics
Logic circuits - Computer-aided design Verilog (Computer hardware description language) |
Soggetto genere / forma | Electronic books. |
ISBN |
1-280-55652-8
9786610556526 0-471-45755-8 0-470-35692-8 0-471-45756-6 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Introduction -- Asic design flow -- Verilog coding -- Coding style : best-known method for synthesis -- Design example of programmable timer -- Design example of programmable logic block for peripheral interface. |
Record Nr. | UNINA-9910146065603321 |
Lee Weng Fook | ||
[Place of publication not identified], : Wiley Interscience Imprint, 2003 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Verilog Coding for Logic Synthesis |
Autore | Lee Weng Fook |
Edizione | [1st edition] |
Pubbl/distr/stampa | [Place of publication not identified], : Wiley Interscience Imprint, 2003 |
Descrizione fisica | 1 online resource (1 v.) : ill |
Disciplina | 621.395 |
Soggetto topico |
Digital electronics
Logic circuits - Computer-aided design Verilog (Computer hardware description language) |
ISBN |
1-280-55652-8
9786610556526 0-471-45755-8 0-470-35692-8 0-471-45756-6 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Introduction -- Asic design flow -- Verilog coding -- Coding style : best-known method for synthesis -- Design example of programmable timer -- Design example of programmable logic block for peripheral interface. |
Record Nr. | UNINA-9910831077603321 |
Lee Weng Fook | ||
[Place of publication not identified], : Wiley Interscience Imprint, 2003 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
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