Verilog Quickstart [[electronic resource] ] : a practical guide to simulation and synthesis in Verilog / / James M. Lee |
Autore | Lee James M. <1962-> |
Edizione | [3rd ed.] |
Pubbl/distr/stampa | Boston, : Kluwer Academic Publishers, 2002 |
Descrizione fisica | 1 online resource (378 p.) |
Disciplina | 621.39/2 |
Collana | The Kluwer international series in engineering and computer science |
Soggetto topico | Verilog (Computer hardware description language) |
Soggetto genere / forma | Electronic books. |
ISBN |
1-280-20636-5
9786610206360 0-306-47680-0 |
Formato | Materiale a stampa ![]() |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | to the Verilog Language -- Structural Modeling -- Starting Procedural Modeling -- System Tasks for Displaying Results -- Data Objects -- Procedural Assignments -- Operators -- Creating Combinatorial and Sequential Logic -- Procedural Flow Control -- Tasks and Functions -- Advanced Procedural Modeling -- User-Defined Primitives -- Parameterized Modules -- State Machines -- Modeling Tips -- Modeling Style Trade-Offs -- Test Benches and Test Management -- Model Organization -- Common Errors -- Debugging a Design -- Code Coverage. |
Record Nr. | UNINA-9910456199503321 |
Lee James M. <1962->
![]() |
||
Boston, : Kluwer Academic Publishers, 2002 | ||
![]() | ||
Lo trovi qui: Univ. Federico II | ||
|
Verilog Quickstart [[electronic resource] ] : a practical guide to simulation and synthesis in Verilog / / James M. Lee |
Autore | Lee James M. <1962-> |
Edizione | [3rd ed.] |
Pubbl/distr/stampa | Boston, : Kluwer Academic Publishers, 2002 |
Descrizione fisica | 1 online resource (378 p.) |
Disciplina | 621.39/2 |
Collana | The Kluwer international series in engineering and computer science |
Soggetto topico | Verilog (Computer hardware description language) |
ISBN |
1-280-20636-5
9786610206360 0-306-47680-0 |
Formato | Materiale a stampa ![]() |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | to the Verilog Language -- Structural Modeling -- Starting Procedural Modeling -- System Tasks for Displaying Results -- Data Objects -- Procedural Assignments -- Operators -- Creating Combinatorial and Sequential Logic -- Procedural Flow Control -- Tasks and Functions -- Advanced Procedural Modeling -- User-Defined Primitives -- Parameterized Modules -- State Machines -- Modeling Tips -- Modeling Style Trade-Offs -- Test Benches and Test Management -- Model Organization -- Common Errors -- Debugging a Design -- Code Coverage. |
Record Nr. | UNINA-9910780216403321 |
Lee James M. <1962->
![]() |
||
Boston, : Kluwer Academic Publishers, 2002 | ||
![]() | ||
Lo trovi qui: Univ. Federico II | ||
|
Verilog Quickstart [[electronic resource] ] : a practical guide to simulation and synthesis in Verilog / / James M. Lee |
Autore | Lee James M. <1962-> |
Edizione | [3rd ed.] |
Pubbl/distr/stampa | Boston, : Kluwer Academic Publishers, 2002 |
Descrizione fisica | 1 online resource (378 p.) |
Disciplina | 621.39/2 |
Collana | The Kluwer international series in engineering and computer science |
Soggetto topico | Verilog (Computer hardware description language) |
ISBN |
1-280-20636-5
9786610206360 0-306-47680-0 |
Formato | Materiale a stampa ![]() |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | to the Verilog Language -- Structural Modeling -- Starting Procedural Modeling -- System Tasks for Displaying Results -- Data Objects -- Procedural Assignments -- Operators -- Creating Combinatorial and Sequential Logic -- Procedural Flow Control -- Tasks and Functions -- Advanced Procedural Modeling -- User-Defined Primitives -- Parameterized Modules -- State Machines -- Modeling Tips -- Modeling Style Trade-Offs -- Test Benches and Test Management -- Model Organization -- Common Errors -- Debugging a Design -- Code Coverage. |
Record Nr. | UNINA-9910809900903321 |
Lee James M. <1962->
![]() |
||
Boston, : Kluwer Academic Publishers, 2002 | ||
![]() | ||
Lo trovi qui: Univ. Federico II | ||
|