| Nota di contenuto |
Intro -- Preface -- Acknowledgments -- Contents -- About the Author -- 1 Flip Chip Technology -- 1.1 Introduction -- 1.2 Wafer Bumping-Stencil Printing -- 1.2.1 Sample Description and Experiment Setup -- 1.2.2 Taguchi Design of Experiments -- 1.2.3 Control Factors in Stencil Printing -- 1.2.4 Paste Printing and Reflow -- 1.2.5 Solder Volume -- 1.2.6 Data Analysis of the L8 Experiments -- 1.2.7 Data Analysis of the L4 Experiments -- 1.2.8 Summary -- 1.3 Wafer Bumping-Electroplating -- 1.3.1 C4 Bump -- 1.3.2 C2 Bump -- 1.3.3 C4 Bump versus C2 Bump -- 1.4 Flip Chip Package Substrate -- 1.5 Flip Chip Package Substrates-Organic -- 1.5.1 Printed Circuit Boards (PCBs) -- 1.5.2 Build-Up Package Substrates -- 1.5.3 Coreless Package Substrates -- 1.5.4 BOC and BOL Substrates -- 1.5.5 Embedded Trace Substrates (ETS) -- 1.5.6 Thin-Film Layers on Build-Up Package Substrates -- 1.6 Flip Chip Package Substrates-Fan-Out EMC/RDL -- 1.6.1 Fan-Out Chip-First RDL-Substrate -- 1.6.2 Fan-Out Chip-Last Hybrid Substrate -- 1.7 Flip Chip Package Substrates-TSV-Interposer -- 1.7.1 Passive TSV-Interposers -- 1.7.2 Active TSV-Interposers -- 1.8 Flip Chip Package Substrates-Si-Bridge Embedded in Organic Substrate -- 1.8.1 Intel's EMIB -- 1.8.2 IBM's DBHi -- 1.9 Flip Chip Package Substrates-Si-Bridge Embedded in Fan-Out EMC with RDLs -- 1.9.1 Unimicron's Si-Bridge -- 1.9.2 TSMC's CoWoS-L -- 1.9.3 SPIL's FO-EB-T -- 1.10 Flip Chip Assembly -- 1.10.1 Cu-to-Cu TCB Direct Bonding -- 1.10.2 Cu-to-Cu Room Temperature Direct (Hybrid) Bonding -- 1.10.3 C4 Solder Mass Reflow with CUF -- 1.10.4 C2 Solder Mass Reflow with CUF -- 1.10.5 TCB with Low-Bonding Force with CUF -- 1.10.6 C2 TCB with High-Bonding Force (NCP and NCF) -- 1.11 Underfill/Reliability -- 1.11.1 Post-Assembly Underfill -- 1.11.2 Pre-assembly Underfill -- 1.12 Reliability-Characterization of Underfill.
1.12.1 Underfill Materials and Applications -- 1.12.2 Curing Conditions -- 1.12.3 Underfill Material Properties -- 1.12.4 Underfill Flow Rate -- 1.12.5 Mechanical Performance -- 1.12.6 Electrical Performance -- 1.12.7 Ranking of Underfill Encapsulants -- 1.12.8 Summary -- 1.13 Reliability-Stencil Printing of Underfill -- 1.13.1 New Stencil Design -- 1.13.2 Test Vehicles -- 1.13.3 Experiments -- 1.13.4 Characterizations -- 1.13.5 Summary -- 1.14 LPC-A High Throughput TCB Process -- 1.14.1 Experimental Procedure -- 1.14.2 Bonding Quality Evaluation -- 1.14.3 Stand-Off Height Control -- 1.14.4 Thermal Fatigue -- 1.14.5 Summary -- 1.15 Summary -- References -- 2 Cu-Cu Hybrid Bonding -- 2.1 Introduction -- 2.2 Samsung's Hybrid Bonding -- 2.3 SK Hynix's Hybrid Bonding -- 2.4 Micron's Hybrid Bonding -- 2.5 Mitsui's Hybrid Bonding -- 2.6 Sony's Hybrid Bonding -- 2.7 CEA-Leti's Hybrid Bonding -- 2.8 TEL's Hybrid Bonding -- 2.9 Applied Materials' Hybrid Bonding -- 2.10 Intel's Hybrid Bonding -- 2.11 TSMC's Bumpless Cu-Cu Bonding -- 2.12 MKS' Hybrid Bonding -- 2.13 Resonac's Hybrid Bonding -- 2.14 Adeia's Hybrid Bonding -- 2.15 Technische Universitaet Dresden's Hybrid Bonding -- 2.16 EVG's Hybrid Bonding -- 2.17 Iemc's Hybrid Bonding -- 2.18 UCLA's Hybrid Bonding -- 2.19 Summary -- References -- 3 Fan-In Technology -- 3.1 Introduction -- 3.2 Creep Analysis of a Lead-Free WLCSP -- 3.2.1 The Structure -- 3.2.2 Material Properties -- 3.2.3 Boundary Conditions -- 3.2.4 Deformed Shapes, Strains, and Stresses -- 3.2.5 Hysteresis Loops -- 3.2.6 Time-Dependent Shear Stress -- 3.2.7 Time-Dependent Shear Creep Strain -- 3.3 Creep Analysis of a Lead-Free WLCSP on PCB with Microvia -- 3.3.1 Microvia Build-Up PCB -- 3.3.2 Deformed Shapes -- 3.3.3 Hysteresis Loops, Stress, and Creep Strain -- 3.4 Creep Analysis of a Lead-Free WLCSP on PCB with Two-Layers of Microvia.
3.4.1 The Structure -- 3.4.2 Elastic Analysis and Results -- 3.4.3 Elastic-Plastic Analysis and Results -- 3.4.4 Creep Analysis and Results -- 3.5 Hitachi's WLCSP -- 3.6 TSMC's WLCSP -- 3.7 Material, Process, and Fabrication of Six-Sides Molded PLCSP -- 3.7.1 Introduction -- 3.7.2 Test Chip and Test Package -- 3.7.3 Six-Side Molded PLCSP Process Flow -- 3.7.4 Wafer and Panel Preparation -- 3.7.5 Fabrication of Redistribution Layer -- 3.7.6 Solder Resist Opening and Solder Ball Mounting -- 3.7.7 Cutting and Epoxy Molding Compound Molding of Wafer from the Front Side -- 3.7.8 Backgrinding and Wafer Backside Molding -- 3.7.9 Plasma Etching and Dicing -- 3.8 Reliability (Drop Test) of Six-Sides Molded PLCSP -- 3.8.1 Test Printed Circuited Board -- 3.8.2 Surface Mount Technology Assembly of the PLCSP on PCB -- 3.8.3 Drop Test Setup and Spectrum -- 3.8.4 Drop Test Results and Failure Analysis -- 3.9 Reliability (Thermal Cycling Test and Simulation) of Six-Sides Molded PLCSP -- 3.9.1 Thermal Cycling Test Failure Criteria -- 3.9.2 Test Results of the Six-Sides Molded PLCSP -- 3.9.3 Failure Location and Failure Mode of the Six-Sides Molded PLCSP PCB Assembly -- 3.9.4 Test Results of the Ordinary PLCSP -- 3.9.5 Failure Location and Failure Mode of the Ordinary PLCSP PCB Assembly -- 3.9.6 Comparison Between the Six-Sides Molded PLCSP and the Ordinary PLCSP -- 3.9.7 Simulation Results of the Six-Sides Molded PLCSP Solder Joint -- 3.9.8 Simulation Results of the Ordinary PLCSP Solder Joint -- 3.9.9 Summary -- 3.10 eWLCSP by Statschippac -- 3.11 WLCSP by UTAC -- 3.12 mWLCSP by SPIL -- 3.13 WLCSP by Huatian -- 3.14 mWLCSP by SPIL and MediaTek -- 3.15 Summary -- References -- 4 Fan-Out Technology -- 4.1 Introduction -- 4.2 Topics in This Chapter -- 4.3 Chip-First with Die Face-Down for Heterogeneous Integration of 4 Chips and 4 Capacitors -- 4.3.1 Test Chip.
4.3.2 Test Package -- 4.3.3 Conventional Chip-First (Die Face-Down) Wafer Process -- 4.3.4 RDLS and Solder Ball Mounting by a New Process -- 4.3.5 PCB Assembly -- 4.3.6 Reliability Assessments-Thermal Cycling Test -- 4.3.7 Reliability Assessments-Drop Test -- 4.3.8 Reliability Assessments-Thermal Simulations -- 4.3.9 Reliability Assessments-Drop Simulations -- 4.3.10 Summary -- 4.4 Chip-First with Die Face-Down for Heterogeneous Integration of Mini-LED RGB Display -- 4.4.1 Test Mini-LEDs -- 4.4.2 Test Mini-LED Package -- 4.4.3 RDL and Mini-LED RGB SMD Fabrication -- 4.4.4 PCB Assembly -- 4.4.5 Drop Test -- 4.4.6 Thermal Cycling Simulation -- 4.4.7 Summary -- 4.5 Chip-First with Die Face-Up for a Large 10 mm × 10 mm Chip -- 4.5.1 Test Chip -- 4.5.2 Test Package -- 4.5.3 Chip-First (Die Face-Up) FOWLP Assembly Process -- 4.5.4 On the Test Chip Wafer -- 4.5.5 On the Reconstituted Wafer -- 4.5.6 PCB Assembly -- 4.5.7 Thermal Cycling Test and Results -- 4.5.8 Drop Test and Results -- 4.5.9 Thermal Cycling Simulation -- 4.5.10 Shock (Drop) Simulation -- 4.5.11 Summary -- 4.6 Apple/TSMC's Application Processor with Chip-First (Die Face-Up) Process -- 4.7 Chip-Last or RDL-First Fan-Out Technology -- 4.8 Panel-Level Fan-Out RDL-First Packaging for Heterogeneous Integration -- 4.8.1 Test Chips -- 4.8.2 Test Package -- 4.8.3 RDL-First Panel-Level Packaging for Heterogeneous Integration -- 4.8.4 Thermal Cycling Simulation -- 4.8.5 PCB Assemble -- 4.8.6 Drop Test Results and Failure Analysis -- 4.8.7 Thermal Cycling Test and Results -- 4.8.8 Thermal Cycling Simulation of the Package PCB Assemble -- 4.8.9 Summary -- 4.9 Hybrid Substrate for Heterogeneous Integration -- 4.10 Hybrid Substrate with PID by RDL-First Panel-Level Packaging -- 4.10.1 Test Chips -- 4.10.2 Test Package -- 4.10.3 Organic Interposer Fabrication -- 4.10.4 Build-Up Substrate Fabrication.
4.10.5 C4 Bump Formation -- 4.10.6 Warpage Measurements -- 4.10.7 Hybrid Substrate Formation -- 4.10.8 Remove the Temporary Glass Panel -- 4.10.9 Chips-to-Hybrid Substrate Bonding -- 4.10.10 Underfilling -- 4.10.11 Thermal Cycling Simulation and Results -- 4.10.12 Summary -- 4.11 Hybrid Substrate with ABF by RDL-First Panel-Level Packaging -- 4.11.1 The Structure and Material Properties -- 4.11.2 Fabrication Process of the Organic Interposer -- 4.11.3 Warpage -- 4.11.4 Fabrication Process of the Build-Up Package Substrate -- 4.11.5 Fabrication Process of the Hybrid Substrate -- 4.11.6 Chips-to-Hybrid Substrate Bonding -- 4.11.7 Quality of Chips-to-Hybrid Substrate Bonding -- 4.11.8 Thermal Cycling Simulation and Results -- 4.11.9 Summary -- 4.12 Hybrid Substrate with Ultralarge Organic Interposer for Heterogeneous Integration -- 4.12.1 The Structure -- 4.12.2 Finite Element Analysis -- 4.12.3 Anand Viscoplasticity Constitute Equation -- 4.12.4 Boundary Condition -- 4.12.5 Accumulated Equivalent Inelastic Strain -- 4.12.6 Hybrid Substrate with Ultralarge Organic Interposer -- 4.12.7 Summary -- 4.13 Hybrid Substrate with Interconnect-Layer for Heterogeneous Integration -- 4.13.1 The Structure -- 4.13.2 Test Chips -- 4.13.3 Fine Metal L/S RDL (Organic Interposer) -- 4.13.4 Interconnect-Layer -- 4.13.5 HDI PCB -- 4.13.6 Final Assembly of the Hybrid Interposer -- 4.13.7 X-Ray and OM -- 4.13.8 Continuity Check -- 4.13.9 Final Assembly -- 4.13.10 Six-Time Reflow -- 4.13.11 Drop Test -- 4.13.12 Thermal Cycling Simulation -- 4.13.13 Summary -- References -- 5 Chiplet Communications (Bridges) -- 5.1 Introduction -- 5.2 Background -- 5.3 Rigid Bridge Versus Flexible Bridge -- 5.4 How to Fabricate the Silicon Bridge with TSV? -- 5.4.1 Fabrication of TSVs -- 5.4.2 Fabrication of RDLs on Top of TSV -- 5.5 Intel's Embedded Multi-die Interconnect Bridge (EMIB).
5.5.1 Solder Bumps for Embedded Multi-die Interconnect Bridge.
|
Info
Assembly and reliability of lead-free solder joints / / John H. Lau, Ning-Cheng Lee
