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Real-time systems design and analysis [[electronic resource] ] : tools for the practitioner / / Phillip A. Laplante, Seppo J. Ovaska
Real-time systems design and analysis [[electronic resource] ] : tools for the practitioner / / Phillip A. Laplante, Seppo J. Ovaska
Autore Laplante Phillip A
Edizione [4th ed.]
Pubbl/distr/stampa Hoboken, NJ, : Wiley-IEEE Press, c2012
Descrizione fisica 1 online resource (584 p.)
Disciplina 004.33
Altri autori (Persone) OvaskaSeppo J. <1956->
Soggetto topico Real-time data processing
System design
ISBN 1-283-33228-0
9786613332288
1-118-13659-4
1-118-13657-8
Classificazione SCI067000
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto REAL-TIME SYSTEMS DESIGN AND ANALYSIS: Tools for the Practitioner, Fourth Edition; CONTENTS; PREFACE; ACKNOWLEDGMENTS; 1: FUNDAMENTALS OF REAL-TIME SYSTEMS; 1.1 CONCEPTS AND MISCONCEPTIONS; 1.1.1 Definitions for Real-Time Systems; 1.1.2 Usual Misconceptions; 1.2 MULTIDISCIPLINARY DESIGN CHALLENGES; 1.2.1 Influencing Disciplines; 1.3 BIRTH AND EVOLUTION OF REAL-TIME SYSTEMS; 1.3.1 Diversifying Applications; 1.3.2 Advancements behind Modern Real-Time Systems; 1.4 SUMMARY; 1.5 EXERCISES; REFERENCES; 2: HARDWARE FOR REAL-TIME SYSTEMS; 2.1 BASIC PROCESSOR ARCHITECTURE
2.1.1 Von Neumann Architecture2.1.2 Instruction Processing; 2.1.3 Input/Output and Interrupt Considerations; 2.2 MEMORY TECHNOLOGIES; 2.2.1 Different Classes of Memory; 2.2.2 Memory Access and Layout Issues; 2.2.3 Hierarchical Memory Organization; 2.3 ARCHITECTURAL ADVANCEMENTS; 2.3.1 Pipelined Instruction Processing; 2.3.2 Superscalar and Very Long Instruction Word Architectures; 2.3.3 Multi-Core Processors; 2.3.4 Complex Instruction Set versus Reduced Instruction Set; 2.4 PERIPHERAL INTERFACING; 2.4.1 Interrupt-Driven Input/Output; 2.4.2 Direct Memory Access
2.4.3 Analog and Digital Input/Output2.5 MICROPROCESSOR VERSUS MICROCONTROLLER; 2.5.1 Microprocessors; 2.5.2 Standard Microcontrollers; 2.5.3 Custom Microcontrollers; 2.6 DISTRIBUTED REAL-TIME ARCHITECTURES; 2.6.1 Fieldbus Networks; 2.6.2 Time-Triggered Architectures; 2.7 SUMMARY; 2.8 EXERCISES; REFERENCES; 3: REAL-TIME OPERATING SYSTEMS; 3.1 FROM PSEUDOKERNELS TO OPERATING SYSTEMS; 3.1.1 Miscellaneous Pseudokernels; 3.1.2 Interrupt-Only Systems; 3.1.3 Preemptive Priority Systems; 3.1.4 Hybrid Scheduling Systems; 3.1.5 The Task Control Block Model; 3.2 THEORETICAL FOUNDATIONS OF SCHEDULING
3.2.1 Scheduling Framework3.2.2 Round-Robin Scheduling; 3.2.3 Cyclic Code Scheduling; 3.2.4 Fixed-Priority Scheduling: Rate-Monotonic Approach; 3.2.5 Dynamic Priority Scheduling: Earliest Deadline First Approach; 3.3 SYSTEM SERVICES FOR APPLICATION PROGRAMS; 3.3.1 Linear Buffers; 3.3.2 Ring Buffers; 3.3.3 Mailboxes; 3.3.4 Semaphores; 3.3.5 Deadlock and Starvation Problems; 3.3.6 Priority Inversion Problem; 3.3.7 Timer and Clock Services; 3.3.8 Application Study: A Real-Time Structure; 3.4 MEMORY MANAGEMENT ISSUES; 3.4.1 Stack and Task Control Block Management; 3.4.2 Multiple-Stack Arrangement
3.4.3 Memory Management in the Task Control Block Model3.4.4 Swapping, Overlaying, and Paging; 3.5 SELECTING REAL-TIME OPERATING SYSTEMS; 3.5.1 Buying versus Building; 3.5.2 Selection Criteria and a Metric for Commercial Real-Time Operating Systems; 3.5.3 Case Study: Selecting a Commercial Real-Time Operating System; 3.5.4 Supplementary Criteria for Multi-Core and Energy-Aware Support; 3.6 SUMMARY; 3.7 EXERCISES; REFERENCES; 4: PROGRAMMING LANGUAGES FOR REAL-TIME SYSTEMS; 4.1 CODING OF REAL-TIME SOFTWARE; 4.1.1 Fitness of a Programming Language for Real-Time Applications
4.1.2 Coding Standards for Real-Time Software
Record Nr. UNINA-9910141180303321
Laplante Phillip A  
Hoboken, NJ, : Wiley-IEEE Press, c2012
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Real-time systems design and analysis [[electronic resource] ] : tools for the practitioner / / Phillip A. Laplante, Seppo J. Ovaska
Real-time systems design and analysis [[electronic resource] ] : tools for the practitioner / / Phillip A. Laplante, Seppo J. Ovaska
Autore Laplante Phillip A
Edizione [4th ed.]
Pubbl/distr/stampa Hoboken, NJ, : Wiley-IEEE Press, c2012
Descrizione fisica 1 online resource (584 p.)
Disciplina 004.33
Altri autori (Persone) OvaskaSeppo J. <1956->
Soggetto topico Real-time data processing
System design
ISBN 1-283-33228-0
9786613332288
1-118-13659-4
1-118-13657-8
Classificazione SCI067000
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto REAL-TIME SYSTEMS DESIGN AND ANALYSIS: Tools for the Practitioner, Fourth Edition; CONTENTS; PREFACE; ACKNOWLEDGMENTS; 1: FUNDAMENTALS OF REAL-TIME SYSTEMS; 1.1 CONCEPTS AND MISCONCEPTIONS; 1.1.1 Definitions for Real-Time Systems; 1.1.2 Usual Misconceptions; 1.2 MULTIDISCIPLINARY DESIGN CHALLENGES; 1.2.1 Influencing Disciplines; 1.3 BIRTH AND EVOLUTION OF REAL-TIME SYSTEMS; 1.3.1 Diversifying Applications; 1.3.2 Advancements behind Modern Real-Time Systems; 1.4 SUMMARY; 1.5 EXERCISES; REFERENCES; 2: HARDWARE FOR REAL-TIME SYSTEMS; 2.1 BASIC PROCESSOR ARCHITECTURE
2.1.1 Von Neumann Architecture2.1.2 Instruction Processing; 2.1.3 Input/Output and Interrupt Considerations; 2.2 MEMORY TECHNOLOGIES; 2.2.1 Different Classes of Memory; 2.2.2 Memory Access and Layout Issues; 2.2.3 Hierarchical Memory Organization; 2.3 ARCHITECTURAL ADVANCEMENTS; 2.3.1 Pipelined Instruction Processing; 2.3.2 Superscalar and Very Long Instruction Word Architectures; 2.3.3 Multi-Core Processors; 2.3.4 Complex Instruction Set versus Reduced Instruction Set; 2.4 PERIPHERAL INTERFACING; 2.4.1 Interrupt-Driven Input/Output; 2.4.2 Direct Memory Access
2.4.3 Analog and Digital Input/Output2.5 MICROPROCESSOR VERSUS MICROCONTROLLER; 2.5.1 Microprocessors; 2.5.2 Standard Microcontrollers; 2.5.3 Custom Microcontrollers; 2.6 DISTRIBUTED REAL-TIME ARCHITECTURES; 2.6.1 Fieldbus Networks; 2.6.2 Time-Triggered Architectures; 2.7 SUMMARY; 2.8 EXERCISES; REFERENCES; 3: REAL-TIME OPERATING SYSTEMS; 3.1 FROM PSEUDOKERNELS TO OPERATING SYSTEMS; 3.1.1 Miscellaneous Pseudokernels; 3.1.2 Interrupt-Only Systems; 3.1.3 Preemptive Priority Systems; 3.1.4 Hybrid Scheduling Systems; 3.1.5 The Task Control Block Model; 3.2 THEORETICAL FOUNDATIONS OF SCHEDULING
3.2.1 Scheduling Framework3.2.2 Round-Robin Scheduling; 3.2.3 Cyclic Code Scheduling; 3.2.4 Fixed-Priority Scheduling: Rate-Monotonic Approach; 3.2.5 Dynamic Priority Scheduling: Earliest Deadline First Approach; 3.3 SYSTEM SERVICES FOR APPLICATION PROGRAMS; 3.3.1 Linear Buffers; 3.3.2 Ring Buffers; 3.3.3 Mailboxes; 3.3.4 Semaphores; 3.3.5 Deadlock and Starvation Problems; 3.3.6 Priority Inversion Problem; 3.3.7 Timer and Clock Services; 3.3.8 Application Study: A Real-Time Structure; 3.4 MEMORY MANAGEMENT ISSUES; 3.4.1 Stack and Task Control Block Management; 3.4.2 Multiple-Stack Arrangement
3.4.3 Memory Management in the Task Control Block Model3.4.4 Swapping, Overlaying, and Paging; 3.5 SELECTING REAL-TIME OPERATING SYSTEMS; 3.5.1 Buying versus Building; 3.5.2 Selection Criteria and a Metric for Commercial Real-Time Operating Systems; 3.5.3 Case Study: Selecting a Commercial Real-Time Operating System; 3.5.4 Supplementary Criteria for Multi-Core and Energy-Aware Support; 3.6 SUMMARY; 3.7 EXERCISES; REFERENCES; 4: PROGRAMMING LANGUAGES FOR REAL-TIME SYSTEMS; 4.1 CODING OF REAL-TIME SOFTWARE; 4.1.1 Fitness of a Programming Language for Real-Time Applications
4.1.2 Coding Standards for Real-Time Software
Record Nr. UNINA-9910830095303321
Laplante Phillip A  
Hoboken, NJ, : Wiley-IEEE Press, c2012
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Real-time systems design and analysis : tools for the practitioner / / Phillip A. Laplante, Seppo J. Ovaska
Real-time systems design and analysis : tools for the practitioner / / Phillip A. Laplante, Seppo J. Ovaska
Autore Laplante Phillip A
Edizione [4th ed.]
Pubbl/distr/stampa Hoboken, NJ, : Wiley-IEEE Press, c2012
Descrizione fisica 1 online resource (584 p.)
Disciplina 004/.33
Altri autori (Persone) OvaskaSeppo J. <1956->
Soggetto topico Real-time data processing
System design
ISBN 9786613332288
9781283332286
1283332280
9781118136591
1118136594
9781118136577
1118136578
Classificazione SCI067000
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto REAL-TIME SYSTEMS DESIGN AND ANALYSIS: Tools for the Practitioner, Fourth Edition; CONTENTS; PREFACE; ACKNOWLEDGMENTS; 1: FUNDAMENTALS OF REAL-TIME SYSTEMS; 1.1 CONCEPTS AND MISCONCEPTIONS; 1.1.1 Definitions for Real-Time Systems; 1.1.2 Usual Misconceptions; 1.2 MULTIDISCIPLINARY DESIGN CHALLENGES; 1.2.1 Influencing Disciplines; 1.3 BIRTH AND EVOLUTION OF REAL-TIME SYSTEMS; 1.3.1 Diversifying Applications; 1.3.2 Advancements behind Modern Real-Time Systems; 1.4 SUMMARY; 1.5 EXERCISES; REFERENCES; 2: HARDWARE FOR REAL-TIME SYSTEMS; 2.1 BASIC PROCESSOR ARCHITECTURE
2.1.1 Von Neumann Architecture2.1.2 Instruction Processing; 2.1.3 Input/Output and Interrupt Considerations; 2.2 MEMORY TECHNOLOGIES; 2.2.1 Different Classes of Memory; 2.2.2 Memory Access and Layout Issues; 2.2.3 Hierarchical Memory Organization; 2.3 ARCHITECTURAL ADVANCEMENTS; 2.3.1 Pipelined Instruction Processing; 2.3.2 Superscalar and Very Long Instruction Word Architectures; 2.3.3 Multi-Core Processors; 2.3.4 Complex Instruction Set versus Reduced Instruction Set; 2.4 PERIPHERAL INTERFACING; 2.4.1 Interrupt-Driven Input/Output; 2.4.2 Direct Memory Access
2.4.3 Analog and Digital Input/Output2.5 MICROPROCESSOR VERSUS MICROCONTROLLER; 2.5.1 Microprocessors; 2.5.2 Standard Microcontrollers; 2.5.3 Custom Microcontrollers; 2.6 DISTRIBUTED REAL-TIME ARCHITECTURES; 2.6.1 Fieldbus Networks; 2.6.2 Time-Triggered Architectures; 2.7 SUMMARY; 2.8 EXERCISES; REFERENCES; 3: REAL-TIME OPERATING SYSTEMS; 3.1 FROM PSEUDOKERNELS TO OPERATING SYSTEMS; 3.1.1 Miscellaneous Pseudokernels; 3.1.2 Interrupt-Only Systems; 3.1.3 Preemptive Priority Systems; 3.1.4 Hybrid Scheduling Systems; 3.1.5 The Task Control Block Model; 3.2 THEORETICAL FOUNDATIONS OF SCHEDULING
3.2.1 Scheduling Framework3.2.2 Round-Robin Scheduling; 3.2.3 Cyclic Code Scheduling; 3.2.4 Fixed-Priority Scheduling: Rate-Monotonic Approach; 3.2.5 Dynamic Priority Scheduling: Earliest Deadline First Approach; 3.3 SYSTEM SERVICES FOR APPLICATION PROGRAMS; 3.3.1 Linear Buffers; 3.3.2 Ring Buffers; 3.3.3 Mailboxes; 3.3.4 Semaphores; 3.3.5 Deadlock and Starvation Problems; 3.3.6 Priority Inversion Problem; 3.3.7 Timer and Clock Services; 3.3.8 Application Study: A Real-Time Structure; 3.4 MEMORY MANAGEMENT ISSUES; 3.4.1 Stack and Task Control Block Management; 3.4.2 Multiple-Stack Arrangement
3.4.3 Memory Management in the Task Control Block Model3.4.4 Swapping, Overlaying, and Paging; 3.5 SELECTING REAL-TIME OPERATING SYSTEMS; 3.5.1 Buying versus Building; 3.5.2 Selection Criteria and a Metric for Commercial Real-Time Operating Systems; 3.5.3 Case Study: Selecting a Commercial Real-Time Operating System; 3.5.4 Supplementary Criteria for Multi-Core and Energy-Aware Support; 3.6 SUMMARY; 3.7 EXERCISES; REFERENCES; 4: PROGRAMMING LANGUAGES FOR REAL-TIME SYSTEMS; 4.1 CODING OF REAL-TIME SOFTWARE; 4.1.1 Fitness of a Programming Language for Real-Time Applications
4.1.2 Coding Standards for Real-Time Software
Record Nr. UNINA-9911019349803321
Laplante Phillip A  
Hoboken, NJ, : Wiley-IEEE Press, c2012
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Real-time systems design and analysis [[electronic resource] /] / Phillip A. Laplante
Real-time systems design and analysis [[electronic resource] /] / Phillip A. Laplante
Autore Laplante Phillip A
Edizione [3rd ed.]
Pubbl/distr/stampa Hoboken, N.J., : Wiley, 2004
Descrizione fisica 1 online resource (529 p.)
Disciplina 001.6
004.33
Soggetto topico Real-time data processing
System design
ISBN 1-280-36809-8
9786610368099
0-470-34265-X
0-471-64828-0
0-471-64829-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto REAL-TIME SYSTEMS DESIGN AND ANALYSIS; CONTENTS; Preface to the Third Edition; 1 Basic Real-Time Concepts; 1.1 Terminology; 1.1.1 Systems Concepts; 1.1.2 Real-Time Definitions; 1.1.3 Events and Determinism; 1.1.4 CPU Utilization; 1.2 Real-Time System Design Issues; 1.3 Example Real-Time Systems; 1.4 Common Misconceptions; 1.5 Brief History; 1.5.1 Theoretical Advances; 1.5.2 Early Systems; 1.5.3 Hardware Developments; 1.5.4 Early Software; 1.5.5 Commercial Operating System Support; 1.6 Exercises; 2 Hardware Considerations; 2.1 Basic Architecture; 2.2 Hardware Interfacing; 2.2.1 Latching
2.2.2 Edge versus Level Triggered2.2.3 Tristate Logic; 2.2.4 Wait States; 2.2.5 Systems Interfaces and Buses; 2.3 Central Processing Unit; 2.3.1 Fetch and Execute Cycle; 2.3.2 Microcontrollers; 2.3.3 Instruction Forms; 2.3.4 Core Instructions; 2.3.5 Addressing Modes; 2.3.6 RISC versus CISC; 2.4 Memory; 2.4.1 Memory Access; 2.4.2 Memory Technologies; 2.4.3 Memory Hierarchy; 2.4.4 Memory Organization; 2.5 Input/Output; 2.5.1 Programmed Input/Output; 2.5.2 Direct Memory Access; 2.5.3 Memory-Mapped Input/Output; 2.5.4 Interrupts; 2.6 Enhancing Performance; 2.6.1 Locality of Reference; 2.6.2 Cache
2.6.3 Pipelining2.6.4 Coprocessors; 2.7 Other Special Devices; 2.7.1 Applications-Specific Integrated Circuits; 2.7.2 Programmable Array Logic/Programmable Logic Array; 2.7.3 Field-Programmable Gate Arrays; 2.7.4 Transducers; 2.7.5 Analog/Digital Converters; 2.7.6 Digital/Analog Converters; 2.8 Non-von-Neumann Architectures; 2.8.1 Parallel Systems; 2.8.2 Flynn's Taxonomy for Parallelism; 2.9 Exercises; 3 Real-Time Operating Systems; 3.1 Real-Time Kernels; 3.1.1 Pseudokernels; 3.1.2 Interrupt-Driven Systems; 3.1.3 Preemptive-Priority Systems; 3.1.4 Hybrid Systems
3.1.5 The Task-Control Block Model3.2 Theoretical Foundations of Real-Time Operating Systems; 3.2.1 Process Scheduling; 3.2.2 Round-Robin Scheduling; 3.2.3 Cyclic Executives; 3.2.4 Fixed-Priority Scheduling-Rate-Monotonic Approach; 3.2.5 Dynamic-Priority Scheduling: Earliest-Deadline-First Approach; 3.3 Intertask Communication and Synchronization; 3.3.1 Buffering Data; 3.3.2 Time-Relative Buffering; 3.3.3 Ring Buffers; 3.3.4 Mailboxes; 3.3.5 Queues; 3.3.6 Critical Regions; 3.3.7 Semaphores; 3.3.8 Other Synchronization Mechanisms; 3.3.9 Deadlock; 3.3.10 Priority Inversion
3.4 Memory Management3.4.1 Process Stack Management; 3.4.2 Run-Time Ring Buffer; 3.4.3 Maximum Stack Size; 3.4.4 Multiple-Stack Arrangements; 3.4.5 Memory Management in the Task-Control-Block Model; 3.4.6 Swapping; 3.4.7 Overlays; 3.4.8 Block or Page Management; 3.4.9 Replacement Algorithms; 3.4.10 Memory Locking; 3.4.11 Working Sets; 3.4.12 Real-Time Garbage Collection; 3.4.13 Contiguous File Systems; 3.4.14 Building versus Buying Real-Time Operating Systems; 3.4.15 Selecting Real-Time Kernels; 3.5 Case Study: POSIX; 3.5.1 Threads; 3.5.2 POSIX Mutexes and Condition Variables
3.5.3 POSIX Semaphores
Record Nr. UNINA-9910143643703321
Laplante Phillip A  
Hoboken, N.J., : Wiley, 2004
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Real-time systems design and analysis [[electronic resource] /] / Phillip A. Laplante
Real-time systems design and analysis [[electronic resource] /] / Phillip A. Laplante
Autore Laplante Phillip A
Edizione [3rd ed.]
Pubbl/distr/stampa Hoboken, N.J., : Wiley, 2004
Descrizione fisica 1 online resource (529 p.)
Disciplina 001.6
004.33
Soggetto topico Real-time data processing
System design
ISBN 1-280-36809-8
9786610368099
0-470-34265-X
0-471-64828-0
0-471-64829-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto REAL-TIME SYSTEMS DESIGN AND ANALYSIS; CONTENTS; Preface to the Third Edition; 1 Basic Real-Time Concepts; 1.1 Terminology; 1.1.1 Systems Concepts; 1.1.2 Real-Time Definitions; 1.1.3 Events and Determinism; 1.1.4 CPU Utilization; 1.2 Real-Time System Design Issues; 1.3 Example Real-Time Systems; 1.4 Common Misconceptions; 1.5 Brief History; 1.5.1 Theoretical Advances; 1.5.2 Early Systems; 1.5.3 Hardware Developments; 1.5.4 Early Software; 1.5.5 Commercial Operating System Support; 1.6 Exercises; 2 Hardware Considerations; 2.1 Basic Architecture; 2.2 Hardware Interfacing; 2.2.1 Latching
2.2.2 Edge versus Level Triggered2.2.3 Tristate Logic; 2.2.4 Wait States; 2.2.5 Systems Interfaces and Buses; 2.3 Central Processing Unit; 2.3.1 Fetch and Execute Cycle; 2.3.2 Microcontrollers; 2.3.3 Instruction Forms; 2.3.4 Core Instructions; 2.3.5 Addressing Modes; 2.3.6 RISC versus CISC; 2.4 Memory; 2.4.1 Memory Access; 2.4.2 Memory Technologies; 2.4.3 Memory Hierarchy; 2.4.4 Memory Organization; 2.5 Input/Output; 2.5.1 Programmed Input/Output; 2.5.2 Direct Memory Access; 2.5.3 Memory-Mapped Input/Output; 2.5.4 Interrupts; 2.6 Enhancing Performance; 2.6.1 Locality of Reference; 2.6.2 Cache
2.6.3 Pipelining2.6.4 Coprocessors; 2.7 Other Special Devices; 2.7.1 Applications-Specific Integrated Circuits; 2.7.2 Programmable Array Logic/Programmable Logic Array; 2.7.3 Field-Programmable Gate Arrays; 2.7.4 Transducers; 2.7.5 Analog/Digital Converters; 2.7.6 Digital/Analog Converters; 2.8 Non-von-Neumann Architectures; 2.8.1 Parallel Systems; 2.8.2 Flynn's Taxonomy for Parallelism; 2.9 Exercises; 3 Real-Time Operating Systems; 3.1 Real-Time Kernels; 3.1.1 Pseudokernels; 3.1.2 Interrupt-Driven Systems; 3.1.3 Preemptive-Priority Systems; 3.1.4 Hybrid Systems
3.1.5 The Task-Control Block Model3.2 Theoretical Foundations of Real-Time Operating Systems; 3.2.1 Process Scheduling; 3.2.2 Round-Robin Scheduling; 3.2.3 Cyclic Executives; 3.2.4 Fixed-Priority Scheduling-Rate-Monotonic Approach; 3.2.5 Dynamic-Priority Scheduling: Earliest-Deadline-First Approach; 3.3 Intertask Communication and Synchronization; 3.3.1 Buffering Data; 3.3.2 Time-Relative Buffering; 3.3.3 Ring Buffers; 3.3.4 Mailboxes; 3.3.5 Queues; 3.3.6 Critical Regions; 3.3.7 Semaphores; 3.3.8 Other Synchronization Mechanisms; 3.3.9 Deadlock; 3.3.10 Priority Inversion
3.4 Memory Management3.4.1 Process Stack Management; 3.4.2 Run-Time Ring Buffer; 3.4.3 Maximum Stack Size; 3.4.4 Multiple-Stack Arrangements; 3.4.5 Memory Management in the Task-Control-Block Model; 3.4.6 Swapping; 3.4.7 Overlays; 3.4.8 Block or Page Management; 3.4.9 Replacement Algorithms; 3.4.10 Memory Locking; 3.4.11 Working Sets; 3.4.12 Real-Time Garbage Collection; 3.4.13 Contiguous File Systems; 3.4.14 Building versus Buying Real-Time Operating Systems; 3.4.15 Selecting Real-Time Kernels; 3.5 Case Study: POSIX; 3.5.1 Threads; 3.5.2 POSIX Mutexes and Condition Variables
3.5.3 POSIX Semaphores
Record Nr. UNINA-9910830410003321
Laplante Phillip A  
Hoboken, N.J., : Wiley, 2004
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Real-time systems design and analysis / / Phillip A. Laplante
Real-time systems design and analysis / / Phillip A. Laplante
Autore Laplante Phillip A
Edizione [3rd ed.]
Pubbl/distr/stampa Hoboken, N.J., : Wiley, 2004
Descrizione fisica 1 online resource (529 p.)
Disciplina 004/.33
Soggetto topico Real-time data processing
System design
ISBN 9786610368099
9781280368097
1280368098
9780470342657
047034265X
9780471648284
0471648280
9780471648291
0471648299
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto REAL-TIME SYSTEMS DESIGN AND ANALYSIS; CONTENTS; Preface to the Third Edition; 1 Basic Real-Time Concepts; 1.1 Terminology; 1.1.1 Systems Concepts; 1.1.2 Real-Time Definitions; 1.1.3 Events and Determinism; 1.1.4 CPU Utilization; 1.2 Real-Time System Design Issues; 1.3 Example Real-Time Systems; 1.4 Common Misconceptions; 1.5 Brief History; 1.5.1 Theoretical Advances; 1.5.2 Early Systems; 1.5.3 Hardware Developments; 1.5.4 Early Software; 1.5.5 Commercial Operating System Support; 1.6 Exercises; 2 Hardware Considerations; 2.1 Basic Architecture; 2.2 Hardware Interfacing; 2.2.1 Latching
2.2.2 Edge versus Level Triggered2.2.3 Tristate Logic; 2.2.4 Wait States; 2.2.5 Systems Interfaces and Buses; 2.3 Central Processing Unit; 2.3.1 Fetch and Execute Cycle; 2.3.2 Microcontrollers; 2.3.3 Instruction Forms; 2.3.4 Core Instructions; 2.3.5 Addressing Modes; 2.3.6 RISC versus CISC; 2.4 Memory; 2.4.1 Memory Access; 2.4.2 Memory Technologies; 2.4.3 Memory Hierarchy; 2.4.4 Memory Organization; 2.5 Input/Output; 2.5.1 Programmed Input/Output; 2.5.2 Direct Memory Access; 2.5.3 Memory-Mapped Input/Output; 2.5.4 Interrupts; 2.6 Enhancing Performance; 2.6.1 Locality of Reference; 2.6.2 Cache
2.6.3 Pipelining2.6.4 Coprocessors; 2.7 Other Special Devices; 2.7.1 Applications-Specific Integrated Circuits; 2.7.2 Programmable Array Logic/Programmable Logic Array; 2.7.3 Field-Programmable Gate Arrays; 2.7.4 Transducers; 2.7.5 Analog/Digital Converters; 2.7.6 Digital/Analog Converters; 2.8 Non-von-Neumann Architectures; 2.8.1 Parallel Systems; 2.8.2 Flynn's Taxonomy for Parallelism; 2.9 Exercises; 3 Real-Time Operating Systems; 3.1 Real-Time Kernels; 3.1.1 Pseudokernels; 3.1.2 Interrupt-Driven Systems; 3.1.3 Preemptive-Priority Systems; 3.1.4 Hybrid Systems
3.1.5 The Task-Control Block Model3.2 Theoretical Foundations of Real-Time Operating Systems; 3.2.1 Process Scheduling; 3.2.2 Round-Robin Scheduling; 3.2.3 Cyclic Executives; 3.2.4 Fixed-Priority Scheduling-Rate-Monotonic Approach; 3.2.5 Dynamic-Priority Scheduling: Earliest-Deadline-First Approach; 3.3 Intertask Communication and Synchronization; 3.3.1 Buffering Data; 3.3.2 Time-Relative Buffering; 3.3.3 Ring Buffers; 3.3.4 Mailboxes; 3.3.5 Queues; 3.3.6 Critical Regions; 3.3.7 Semaphores; 3.3.8 Other Synchronization Mechanisms; 3.3.9 Deadlock; 3.3.10 Priority Inversion
3.4 Memory Management3.4.1 Process Stack Management; 3.4.2 Run-Time Ring Buffer; 3.4.3 Maximum Stack Size; 3.4.4 Multiple-Stack Arrangements; 3.4.5 Memory Management in the Task-Control-Block Model; 3.4.6 Swapping; 3.4.7 Overlays; 3.4.8 Block or Page Management; 3.4.9 Replacement Algorithms; 3.4.10 Memory Locking; 3.4.11 Working Sets; 3.4.12 Real-Time Garbage Collection; 3.4.13 Contiguous File Systems; 3.4.14 Building versus Buying Real-Time Operating Systems; 3.4.15 Selecting Real-Time Kernels; 3.5 Case Study: POSIX; 3.5.1 Threads; 3.5.2 POSIX Mutexes and Condition Variables
3.5.3 POSIX Semaphores
Record Nr. UNINA-9911019744903321
Laplante Phillip A  
Hoboken, N.J., : Wiley, 2004
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui