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Transient-induced latchup in CMOS integrated circuits / / Ming-Dou Ker and Sheng-Fu Hsu
| Transient-induced latchup in CMOS integrated circuits / / Ming-Dou Ker and Sheng-Fu Hsu |
| Autore | Ker Ming-Dou |
| Pubbl/distr/stampa | Singapore ; , : Wiley, , c2009 |
| Descrizione fisica | 1 online resource (265 p.) |
| Disciplina |
621.3815
621.39/5 |
| Altri autori (Persone) | HsuSheng-Fu |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Defects
Metal oxide semiconductors, Complementary - Reliability |
| ISBN |
1-282-38218-7
9786612382185 0-470-82409-3 0-470-82408-5 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Physical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process. |
| Record Nr. | UNINA-9910139930203321 |
Ker Ming-Dou
|
||
| Singapore ; , : Wiley, , c2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Transient-induced latchup in CMOS integrated circuits / / Ming-Dou Ker and Sheng-Fu Hsu
| Transient-induced latchup in CMOS integrated circuits / / Ming-Dou Ker and Sheng-Fu Hsu |
| Autore | Ker Ming-Dou |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Singapore ; ; Hoboken, NJ, : Wiley, c2009 |
| Descrizione fisica | 1 online resource (265 p.) |
| Disciplina |
621.3815
621.39/5 |
| Altri autori (Persone) | HsuSheng-Fu |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Defects
Metal oxide semiconductors, Complementary - Reliability |
| ISBN |
9786612382185
9781282382183 1282382187 9780470824092 0470824093 9780470824085 0470824085 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Physical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process. |
| Record Nr. | UNINA-9910808037403321 |
|
Ker Ming-Dou
|
||
| Singapore ; ; Hoboken, NJ, : Wiley, c2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||