Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
Computer Performance Evaluation and Benchmarking [[electronic resource] ] : SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009, Proceedings / / edited by David Kaeli
| Computer Performance Evaluation and Benchmarking [[electronic resource] ] : SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009, Proceedings / / edited by David Kaeli |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (IX, 145 p.) |
| Disciplina | 004.0151 |
| Collana | Programming and Software Engineering |
| Soggetto topico |
Computers
Application software Computer system failures Microprocessors Microprogramming Logic design Theory of Computation Computer Applications System Performance and Evaluation Processor Architectures Control Structures and Microprogramming Logic Design |
| ISBN | 3-540-93799-4 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Benchmark Suites -- SPECrate2006: Alternatives Considered, Lessons Learned -- SPECjvm2008 Performance Characterization -- CPU Benchmarking -- Performance Characterization of Itanium® 2-Based Montecito Processor -- A Tale of Two Processors: Revisiting the RISC-CISC Debate -- Investigating Cache Parameters of x86 Family Processors -- Power/Thermal Benchmarking -- The Next Frontier for Power/Performance Benchmarking: Energy Efficiency of Storage Subsystems -- Thermal Design Space Exploration of 3D Die Stacked Multi-core Processors Using Geospatial-Based Predictive Models -- Modeling and Sampling Techniques -- Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics -- A Note on the Effects of Service Time Distribution in the M/G/1 Queue. |
| Record Nr. | UNISA-996465717103316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Computer Performance Evaluation and Benchmarking [[electronic resource] ] : SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009, Proceedings / / edited by David Kaeli
| Computer Performance Evaluation and Benchmarking [[electronic resource] ] : SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009, Proceedings / / edited by David Kaeli |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (IX, 145 p.) |
| Disciplina | 004.0151 |
| Collana | Programming and Software Engineering |
| Soggetto topico |
Computers
Application software Computer system failures Microprocessors Microprogramming Logic design Theory of Computation Computer Applications System Performance and Evaluation Processor Architectures Control Structures and Microprogramming Logic Design |
| ISBN | 3-540-93799-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Benchmark Suites -- SPECrate2006: Alternatives Considered, Lessons Learned -- SPECjvm2008 Performance Characterization -- CPU Benchmarking -- Performance Characterization of Itanium® 2-Based Montecito Processor -- A Tale of Two Processors: Revisiting the RISC-CISC Debate -- Investigating Cache Parameters of x86 Family Processors -- Power/Thermal Benchmarking -- The Next Frontier for Power/Performance Benchmarking: Energy Efficiency of Storage Subsystems -- Thermal Design Space Exploration of 3D Die Stacked Multi-core Processors Using Geospatial-Based Predictive Models -- Modeling and Sampling Techniques -- Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics -- A Note on the Effects of Service Time Distribution in the M/G/1 Queue. |
| Record Nr. | UNINA-9910483563003321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
GPGPU-7 : proceedings of the 7th Workshop on General Purpose Processing Using Graphics Processing Units : March 1, 2014, Salt Lake City, Utah
| GPGPU-7 : proceedings of the 7th Workshop on General Purpose Processing Using Graphics Processing Units : March 1, 2014, Salt Lake City, Utah |
| Autore | Cavazos John |
| Pubbl/distr/stampa | [Place of publication not identified], : ACM, 2014 |
| Descrizione fisica | 1 online resource (110 pages) |
| Collana | ACM Other conferences |
| Soggetto topico |
Engineering & Applied Sciences
Computer Science |
| ISBN | 1-4503-2766-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
General Purpose Processing Using Graphics Processing Units-7
Proceedings of Workshop on General Purpose Processing Using GPUs GPGPU-7 Seventh Workshop on General Purpose Processing Using GPUs, Salt Lake City, UT, USA - March 01 - 01, 2014 |
| Record Nr. | UNINA-9910376388003321 |
Cavazos John
|
||
| [Place of publication not identified], : ACM, 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Heterogeneous computing with OpenCL 2.0 / / David Kaeli [and three others]
| Heterogeneous computing with OpenCL 2.0 / / David Kaeli [and three others] |
| Edizione | [Third edition.] |
| Pubbl/distr/stampa | Amsterdam, [Netherlands] : , : Morgan Kaufman, , 2015 |
| Descrizione fisica | 1 online resource (330 p.) |
| Disciplina | 005.275 |
| Soggetto topico |
Parallel programming (Computer science)
OpenCL (Computer program language) |
| ISBN |
0-12-801649-3
0-12-801414-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Heterogeneous Computing with OpenCL 2.0; Copyright; Contents; List of Figures; List of Tables; Foreword; Acknowledgments; Chapter 1: Introduction; 1.1 Introduction to Heterogeneous Computing; 1.2 The Goals of This Book; 1.3 Thinking Parallel; 1.4 Concurrency and Parallel Programming Models; 1.5 Threads and Shared Memory; 1.6 Message-Passing Communication; 1.7 Different Grains of Parallelism; 1.7.1 Data Sharing and Synchronization; 1.7.2 Shared Virtual Memory; 1.8 Heterogeneous Computing with OpenCL; 1.9 Book Structure; References; Chapter 2: Device architectures; 2.1 Introduction
2.2 Hardware Trade-offs2.2.1 Performance Increase with Frequency, and its Limitations; 2.2.2 Superscalar Execution; 2.2.3 Very Long Instruction Word; 2.2.4 SIMD and Vector Processing; 2.2.5 Hardware Multithreading; 2.2.6 Multicore Architectures; 2.2.7 Integration: Systems-on-Chip and the APU; 2.2.8 Cache Hierarchies and Memory Systems; 2.3 The Architectural Design Space; 2.3.1 CPU Designs; Low-power CPUs; Mainstream desktop CPUs; Server CPUs; 2.3.2 GPU Architectures; Handheld GPUs; At the high end: AMD Radeon R9 290X and NVIDIA GeForce GTX 780; 2.3.3 APU and APU-like Designs; 2.4 Summary ReferencesChapter 3: Introduction to OpenCL; 3.1 Introduction; 3.1.1 The OpenCL Standard; 3.1.2 The OpenCL Specification; 3.2 The OpenCL Platform Model; 3.2.1 Platforms and Devices; 3.3 The OpenCL Execution Model; 3.3.1 Contexts; 3.3.2 Command-Queues; 3.3.3 Events; 3.3.4 Device-Side Enqueuing; 3.4 Kernels and the OpenCL Programming Model; 3.4.1 Compilation and Argument Handling; 3.4.2 Starting Kernel Execution on a Device; 3.5 OpenCL Memory Model; 3.5.1 Memory Objects; Buffers; Images; Pipes; 3.5.2 Data Transfer Commands; 3.5.3 Memory Regions; 3.5.4 Generic Address Space 3.6 The OpenCL Runtime with an Example3.6.1 Complete Vector Addition Listing; 3.7 Vector Addition Using an OpenCL C++ Wrapper; 3.8 OpenCL for CUDA Programmers; 3.9 Summary; Reference; Chapter 4: Examples; 4.1 OpenCL Examples; 4.2 Histogram; 4.3 Image Rotation; 4.4 Image Convolution; 4.5 Producer-Consumer; 4.6 Utility Functions; 4.6.1 Reporting Compilation Errors; 4.6.2 Creating a Program String; 4.7 Summary; Chapter 5: OpenCL runtime and concurrency model; 5.1 Commands and the Queuing Model; 5.1.1 Blocking Memory Operations; 5.1.2 Events; 5.1.3 Command Barriers and Markers 5.1.4 Event Callbacks5.1.5 Profiling Using Events; 5.1.6 User Events; 5.1.7 Out-of-Order Command-Queues; 5.2 Multiple Command-Queues; 5.3 The Kernel Execution Domain: Work-Items, Work-Groups, and NDRanges; 5.3.1 Synchronization; 5.3.2 Work-Group Barriers; 5.3.3 Built-In Work-Group Functions; 5.3.4 Predicate Evaluation Functions; 5.3.5 Broadcast Functions; 5.3.6 Parallel Primitive Functions; 5.4 Native and Built-In Kernels; 5.4.1 Native kernels; 5.4.2 Built-in kernels; 5.5 Device-Side Queuing; 5.5.1 Creating a Device-Side Queue; 5.5.2 Enqueuing Device-Side Kernels; Dynamic local memory Enforcing dependencies using events |
| Record Nr. | UNINA-9910797128303321 |
| Amsterdam, [Netherlands] : , : Morgan Kaufman, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Heterogeneous computing with OpenCL 2.0 / / David Kaeli [and three others]
| Heterogeneous computing with OpenCL 2.0 / / David Kaeli [and three others] |
| Edizione | [Third edition.] |
| Pubbl/distr/stampa | Amsterdam, [Netherlands] : , : Morgan Kaufman, , 2015 |
| Descrizione fisica | 1 online resource (330 p.) |
| Disciplina | 005.275 |
| Soggetto topico |
Parallel programming (Computer science)
OpenCL (Computer program language) |
| ISBN |
0-12-801649-3
0-12-801414-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Heterogeneous Computing with OpenCL 2.0; Copyright; Contents; List of Figures; List of Tables; Foreword; Acknowledgments; Chapter 1: Introduction; 1.1 Introduction to Heterogeneous Computing; 1.2 The Goals of This Book; 1.3 Thinking Parallel; 1.4 Concurrency and Parallel Programming Models; 1.5 Threads and Shared Memory; 1.6 Message-Passing Communication; 1.7 Different Grains of Parallelism; 1.7.1 Data Sharing and Synchronization; 1.7.2 Shared Virtual Memory; 1.8 Heterogeneous Computing with OpenCL; 1.9 Book Structure; References; Chapter 2: Device architectures; 2.1 Introduction
2.2 Hardware Trade-offs2.2.1 Performance Increase with Frequency, and its Limitations; 2.2.2 Superscalar Execution; 2.2.3 Very Long Instruction Word; 2.2.4 SIMD and Vector Processing; 2.2.5 Hardware Multithreading; 2.2.6 Multicore Architectures; 2.2.7 Integration: Systems-on-Chip and the APU; 2.2.8 Cache Hierarchies and Memory Systems; 2.3 The Architectural Design Space; 2.3.1 CPU Designs; Low-power CPUs; Mainstream desktop CPUs; Server CPUs; 2.3.2 GPU Architectures; Handheld GPUs; At the high end: AMD Radeon R9 290X and NVIDIA GeForce GTX 780; 2.3.3 APU and APU-like Designs; 2.4 Summary ReferencesChapter 3: Introduction to OpenCL; 3.1 Introduction; 3.1.1 The OpenCL Standard; 3.1.2 The OpenCL Specification; 3.2 The OpenCL Platform Model; 3.2.1 Platforms and Devices; 3.3 The OpenCL Execution Model; 3.3.1 Contexts; 3.3.2 Command-Queues; 3.3.3 Events; 3.3.4 Device-Side Enqueuing; 3.4 Kernels and the OpenCL Programming Model; 3.4.1 Compilation and Argument Handling; 3.4.2 Starting Kernel Execution on a Device; 3.5 OpenCL Memory Model; 3.5.1 Memory Objects; Buffers; Images; Pipes; 3.5.2 Data Transfer Commands; 3.5.3 Memory Regions; 3.5.4 Generic Address Space 3.6 The OpenCL Runtime with an Example3.6.1 Complete Vector Addition Listing; 3.7 Vector Addition Using an OpenCL C++ Wrapper; 3.8 OpenCL for CUDA Programmers; 3.9 Summary; Reference; Chapter 4: Examples; 4.1 OpenCL Examples; 4.2 Histogram; 4.3 Image Rotation; 4.4 Image Convolution; 4.5 Producer-Consumer; 4.6 Utility Functions; 4.6.1 Reporting Compilation Errors; 4.6.2 Creating a Program String; 4.7 Summary; Chapter 5: OpenCL runtime and concurrency model; 5.1 Commands and the Queuing Model; 5.1.1 Blocking Memory Operations; 5.1.2 Events; 5.1.3 Command Barriers and Markers 5.1.4 Event Callbacks5.1.5 Profiling Using Events; 5.1.6 User Events; 5.1.7 Out-of-Order Command-Queues; 5.2 Multiple Command-Queues; 5.3 The Kernel Execution Domain: Work-Items, Work-Groups, and NDRanges; 5.3.1 Synchronization; 5.3.2 Work-Group Barriers; 5.3.3 Built-In Work-Group Functions; 5.3.4 Predicate Evaluation Functions; 5.3.5 Broadcast Functions; 5.3.6 Parallel Primitive Functions; 5.4 Native and Built-In Kernels; 5.4.1 Native kernels; 5.4.2 Built-in kernels; 5.5 Device-Side Queuing; 5.5.1 Creating a Device-Side Queue; 5.5.2 Enqueuing Device-Side Kernels; Dynamic local memory Enforcing dependencies using events |
| Record Nr. | UNINA-9910810195503321 |
| Amsterdam, [Netherlands] : , : Morgan Kaufman, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
High Performance Embedded Architectures and Compilers [[electronic resource] ] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (297 p.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computer arithmetic and logic units Microprocessors Computer architecture Computer input-output equipment Logic design Computer networks Theory of Computation Arithmetic and Logic Structures Processor Architectures Input/Output and Data Communications Logic Design Computer Communication Networks |
| ISBN | 3-540-69338-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints. |
| Record Nr. | UNISA-996466023003316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
High Performance Embedded Architectures and Compilers [[electronic resource] ] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (297 p.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computer arithmetic and logic units Microprocessors Computer architecture Computer input-output equipment Logic design Computer networks Theory of Computation Arithmetic and Logic Structures Processor Architectures Input/Output and Data Communications Logic Design Computer Communication Networks |
| ISBN | 3-540-69338-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints. |
| Record Nr. | UNINA-9910484914503321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units
| Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units |
| Autore | Kaeli David |
| Pubbl/distr/stampa | [Place of publication not identified], : Association for Computing Machinery, 2009 |
| Descrizione fisica | 1 online resource (107 p.;) |
| Collana | ACM Other conferences |
| Soggetto topico | Information Technology - Computer Science (Hardware & Networks) |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | GPGPU-2 |
| Record Nr. | UNINA-9910375798703321 |
|
Kaeli David
|
||
| [Place of publication not identified], : Association for Computing Machinery, 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units
| Proceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units |
| Autore | Kaeli David |
| Pubbl/distr/stampa | [Place of publication not identified] : , : Association for Computing Machinery, , 2010 |
| Descrizione fisica | 1 online resource (124 pages) |
| Collana | ACM Other conferences. |
| Soggetto topico | Information Technology - Computer Science (Hardware & Networks) |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | GPGPU-3 |
| Record Nr. | UNINA-9910376071103321 |
|
Kaeli David
|
||
| [Place of publication not identified] : , : Association for Computing Machinery, , 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units : GPGPU-6 : March 16, 2013, Houston, Texas
| Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units : GPGPU-6 : March 16, 2013, Houston, Texas |
| Autore | Cavazos John |
| Pubbl/distr/stampa | [Place of publication not identified], : ACM, 2013 |
| Descrizione fisica | 1 online resource (156 pages) |
| Collana | ACM Other conferences |
| Soggetto topico |
Engineering & Applied Sciences
Technology - General |
| ISBN | 1-4503-2017-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | GPGPU-6 sixth Workshop on General Purpose Processing Using GPUs, Houston, TX, USA - March 16 - 16, 2013 |
| Record Nr. | UNINA-9910375898203321 |
|
Cavazos John
|
||
| [Place of publication not identified], : ACM, 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||