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Applied Reconfigurable Computing [[electronic resource] ] : 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings / / edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger Woods, Pedro Diniz
| Applied Reconfigurable Computing [[electronic resource] ] : 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings / / edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger Woods, Pedro Diniz |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIII, 418 p. 217 illus., 110 illus. in color.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Operating systems (Computers) Software engineering Computer systems Computers, Special purpose Artificial intelligence Computer Hardware Operating Systems Software Engineering Computer System Implementation Special Purpose and Application-Based Systems Artificial Intelligence |
| ISBN | 3-030-17227-9 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Applications -- Fault-Tolerant Architecture for On-Board Dual-Core Synthetic-Aperture Radar Imaging -- Optimizing CNN-based Hyperspectral Image Classification on FPGAs -- Supporting Columnar In-Memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow -- A Novel Encoder for TDCs -- A Resource Reduced Application-Specific FPGA Switch -- Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications -- Partial Reconfiguration and Security -- Probabilistic Performance Modelling when using Partial Reconfiguration to Accelerate Streaming Applications with Non-Deterministic Task Scheduling -- Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems -- (ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-based Countermeasures on FPGAs -- Proof-Carrying Hardware versus the Stealthy Malicious LUT Hardware Trojan -- Secure Local Configuration of Intellectual Property Without a Trusted Third Party -- Image/Video Processing -- HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing -- Real-time FPGA implementation of connected component labelling for a 4K video stream -- A Scalable FPGA-based Architecture for Depth Estimation in SLAM -- High-Level Synthesis -- Evaluating LULESH Kernels on OpenCL FPGA -- The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems -- Graph-based Code Restructuring Targeting HLS for FPGAs -- CGRAs and Vector Processing -- UltraSynth: Integration of a CGRA into a Control Engineering Environment -- Exploiting reconfigurable vector processing for energy-efficient computation in 3D-stacked memories -- Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms -- Architectures -- ReM: a Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures -- Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators -- Design Frameworks and Methodology -- Hybrid Prototyping for Manycore Design and Validation -- Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks -- Invited Talk -- Third Party CAD Tools for FPGA Design | A Survey of the Current Landscape -- Convolutional Neural Networks -- Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation -- Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs -- Faster Convolutional Neural Networks in Low Density FPGAs using Block Pruning. |
| Record Nr. | UNISA-996466302503316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Applied Reconfigurable Computing : 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings / / edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger Woods, Pedro Diniz
| Applied Reconfigurable Computing : 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings / / edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger Woods, Pedro Diniz |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIII, 418 p. 217 illus., 110 illus. in color.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Operating systems (Computers) Software engineering Computer systems Computers, Special purpose Artificial intelligence Computer Hardware Operating Systems Software Engineering Computer System Implementation Special Purpose and Application-Based Systems Artificial Intelligence |
| ISBN | 3-030-17227-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Applications -- Fault-Tolerant Architecture for On-Board Dual-Core Synthetic-Aperture Radar Imaging -- Optimizing CNN-based Hyperspectral Image Classification on FPGAs -- Supporting Columnar In-Memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow -- A Novel Encoder for TDCs -- A Resource Reduced Application-Specific FPGA Switch -- Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications -- Partial Reconfiguration and Security -- Probabilistic Performance Modelling when using Partial Reconfiguration to Accelerate Streaming Applications with Non-Deterministic Task Scheduling -- Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems -- (ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-based Countermeasures on FPGAs -- Proof-Carrying Hardware versus the Stealthy Malicious LUT Hardware Trojan -- Secure Local Configuration of Intellectual Property Without a Trusted Third Party -- Image/Video Processing -- HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing -- Real-time FPGA implementation of connected component labelling for a 4K video stream -- A Scalable FPGA-based Architecture for Depth Estimation in SLAM -- High-Level Synthesis -- Evaluating LULESH Kernels on OpenCL FPGA -- The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems -- Graph-based Code Restructuring Targeting HLS for FPGAs -- CGRAs and Vector Processing -- UltraSynth: Integration of a CGRA into a Control Engineering Environment -- Exploiting reconfigurable vector processing for energy-efficient computation in 3D-stacked memories -- Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms -- Architectures -- ReM: a Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures -- Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators -- Design Frameworks and Methodology -- Hybrid Prototyping for Manycore Design and Validation -- Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks -- Invited Talk -- Third Party CAD Tools for FPGA Design | A Survey of the Current Landscape -- Convolutional Neural Networks -- Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation -- Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs -- Faster Convolutional Neural Networks in Low Density FPGAs using Block Pruning. |
| Record Nr. | UNINA-9910337562203321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Architecture of Computing Systems [[electronic resource] ] : 34th International Conference, ARCS 2021, Virtual Event, June 7–8, 2021, Proceedings / / edited by Christian Hochberger, Lars Bauer, Thilo Pionteck
| Architecture of Computing Systems [[electronic resource] ] : 34th International Conference, ARCS 2021, Virtual Event, June 7–8, 2021, Proceedings / / edited by Christian Hochberger, Lars Bauer, Thilo Pionteck |
| Edizione | [1st ed. 2021.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2021 |
| Descrizione fisica | 1 online resource (239 pages) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Computer systems Computer input-output equipment Software engineering Computer Communication Networks Computer System Implementation Input/Output and Data Communications Software Engineering |
| ISBN | 3-030-81682-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Memory Organization -- Locality: The 3rd Wall and The Need for Innovation in Parallel Architectures -- Static extraction of memory access profiles for multi-core interference analysis of real-time tasks -- Transparent Resilience for Approximate DRAM -- Heterogeneous Computing -- Automatic Mapping of Parallel Pattern-based Algorithms on Heterogeneous Architectures -- Assessing and Improving the Suitability of Model-Based Design for GPU-Accelerated Railway Control Systems -- DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model -- Instruction Set Transformations -- Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode -- Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA -- Organic Computing -- An Organic Computing System for Automated Testing -- Evaluating a Priority-Based Task Distribution Strategy for an Artificial Hormone System -- Low Power Design -- Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-Core MCUs -- Energy Efficient Power-Management for Out-of-Order Processors using Cyclic Power-Gating -- VEFRE Workshop -- BCH 2-Bit and 3-Bit Error Correction with Fast Multi-Bit Error Detection -- Evaluating Soft Error Mitigation Trade-offs During Early Design Stages. |
| Record Nr. | UNISA-996464513403316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2021 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Architecture of Computing Systems : 34th International Conference, ARCS 2021, Virtual Event, June 7–8, 2021, Proceedings / / edited by Christian Hochberger, Lars Bauer, Thilo Pionteck
| Architecture of Computing Systems : 34th International Conference, ARCS 2021, Virtual Event, June 7–8, 2021, Proceedings / / edited by Christian Hochberger, Lars Bauer, Thilo Pionteck |
| Edizione | [1st ed. 2021.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2021 |
| Descrizione fisica | 1 online resource (239 pages) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Computer systems Computer input-output equipment Software engineering Computer Communication Networks Computer System Implementation Input/Output and Data Communications Software Engineering Arquitectura d'ordinadors Sistemes informàtics |
| Soggetto genere / forma |
Congressos
Llibres electrònics |
| ISBN | 3-030-81682-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Memory Organization -- Locality: The 3rd Wall and The Need for Innovation in Parallel Architectures -- Static extraction of memory access profiles for multi-core interference analysis of real-time tasks -- Transparent Resilience for Approximate DRAM -- Heterogeneous Computing -- Automatic Mapping of Parallel Pattern-based Algorithms on Heterogeneous Architectures -- Assessing and Improving the Suitability of Model-Based Design for GPU-Accelerated Railway Control Systems -- DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model -- Instruction Set Transformations -- Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode -- Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA -- Organic Computing -- An Organic Computing System for Automated Testing -- Evaluating a Priority-Based Task Distribution Strategy for an Artificial Hormone System -- Low Power Design -- Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-Core MCUs -- Energy Efficient Power-Management for Out-of-Order Processors using Cyclic Power-Gating -- VEFRE Workshop -- BCH 2-Bit and 3-Bit Error Correction with Fast Multi-Bit Error Detection -- Evaluating Soft Error Mitigation Trade-offs During Early Design Stages. |
| Record Nr. | UNINA-9910492144003321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2021 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Architecture of Computing Systems - ARCS 2009 [[electronic resource] ] : 22nd International Conference, Delft, The Netherlands, March 10-13, 2009, Proceedings / / edited by Mladen Berekovic, Christian Müller-Schloer, Christian Hochberger, Stephan Wong
| Architecture of Computing Systems - ARCS 2009 [[electronic resource] ] : 22nd International Conference, Delft, The Netherlands, March 10-13, 2009, Proceedings / / edited by Mladen Berekovic, Christian Müller-Schloer, Christian Hochberger, Stephan Wong |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XIII, 259 p.) |
| Disciplina | 004.2/2 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Computer engineering Software engineering Computer systems Operating systems (Computers) Computer Communication Networks Computer Engineering and Networks Software Engineering Computer System Implementation Operating Systems |
| Soggetto genere / forma |
Delft (2009)
Kongress. |
| ISBN | 3-642-00454-7 |
| Classificazione |
DAT 200f
DAT 250f SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- Life on the Treadmill -- Key Microarchitectural Innovations for Future Microprocessors -- The Challenges of Multicore: Information and Mis-Information -- Compilation Technologies -- Extracting Coarse-Grained Pipelined Parallelism Out of Sequential Applications for Parallel Processor Arrays -- Parallelization Approaches for Hardware Accelerators – Loop Unrolling Versus Loop Partitioning -- Evaluating Sampling Based Hotspot Detection -- Reconfigurable Hardware and Applications -- A Reconfigurable Bloom Filter Architecture for BLASTN -- SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs -- A Light-Weight Approach to Dynamical Runtime Linking Supporting Heterogenous, Parallel, and Reconfigurable Architectures -- Ultra-Fast Downloading of Partial Bitstreams through Ethernet -- Massive Parallel Architectures -- SCOPE - Sensor Mote Configuration and Operation Enhancement -- Generated Horizontal and Vertical Data Parallel GCA Machines for the N-Body Force Calculation -- Hybrid Resource Discovery Mechanism in Ad Hoc Grid Using Structured Overlay -- Organic Computing -- Marketplace-Oriented Behavior in Semantic Multi-Criteria Decision Making Autonomous Systems -- Self-organized Parallel Cooperation for Solving Optimization Problems -- Memory Architectures -- Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture -- An Enhanced DMA Controller in SIMD Processors for Video Applications -- Cache Controller Design on Ultra Low Leakage Embedded Processors -- Energy Awareness -- Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication -- Energy Management System as an Embedded Service: Saving Energy Consumption of ICT -- Java Processing -- A Garbage Collection Technique for Embedded Multithreaded Multicore Processors -- Empirical Performance Models for Java Workloads -- Chip-Level Multiprocessing -- Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis -- Evaluating CMPs and Their Memory Architecture. |
| Record Nr. | UNISA-996465953403316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Architecture of Computing Systems -- ARCS 2013 [[electronic resource] ] : 26th International Conference, Prague, Czech Republic, February 19-22, 2013 Proceedings / / edited by Hana Kubatova, Christian Hochberger, Martin Daněk, Bernhard Sick
| Architecture of Computing Systems -- ARCS 2013 [[electronic resource] ] : 26th International Conference, Prague, Czech Republic, February 19-22, 2013 Proceedings / / edited by Hana Kubatova, Christian Hochberger, Martin Daněk, Bernhard Sick |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 |
| Descrizione fisica | 1 online resource (XIV, 354 p. 146 illus.) |
| Disciplina | 004.6 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Computer systems Operating systems (Computers) Software engineering Application software Information storage and retrieval systems Computer Communication Networks Computer System Implementation Operating Systems Software Engineering Computer and Information Systems Applications Information Storage and Retrieval |
| ISBN | 3-642-36424-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | An Unstructured Termination Detection Algorithm Using Gossip in Cloud Computing Environments -- Power Monitoring for Mixed-Criticality on a Many-Core Platform -- On Confident Task-Accurate Performance Estimation -- Exploiting Thermal Coupling Information in MPSoC Dynamic Thermal Management -- A Multi-core Memory Organization for 3-D DRAM as Main Memory -- Synthetic Aperture Radar Data Processing on an FPGA Multi-core System -- Virtual Register Renaming -- Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates -- Producer-Consumer: The Programming Model for Future Many-Core Processors -- A Highly Dependable Self-adaptive Mixed-Signal Multi-core System-on-Chip -- Inter-warp Instruction Temporal Locality in Deep-Multithreaded GPUs -- GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems -- HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN) -- A Data-Driven Approach for Executing the CG Method on Reconfigurable High-Performance Systems -- Custom Reconfigurable Architecture Based on Virtex 5 Lookup Tables -- Profiling Energy Consumption of I/O Functions in Embedded Applications -- An Application-Aware Cache Replacement Policy for Last-Level Caches -- Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory -- Self-adaptation for Mobile Robot Algorithms Using Organic Computing Principles -- Self-virtualized CAN Controller for Multi-core Processors in Real-Time Applications -- Shrinking L1 Instruction Caches to Improve Energy–Delay in SMT Embedded Processors -- Arithmetic Unit for Computations in GF(p) with the Left-Shifting Multiplicative Inverse Algorithm -- HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation -- Comparison of GPU and FPGA Implementation of SVM Algorithm for Fast Image Segmentation -- Automatic Floorplanning and Interface Synthesis of Island Style Reconfigurable Systems with GoAhead -- Separable 2D Convolution with Polymorphic Register Files -- Architecture of a Parallel MOSFET Parameter Extraction System -- Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets. |
| Record Nr. | UNISA-996466239303316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Architecture of Computing Systems -- ARCS 2013 : 26th International Conference, Prague, Czech Republic, February 19-22, 2013 Proceedings / / edited by Hana Kubatova, Christian Hochberger, Martin Daněk, Bernhard Sick
| Architecture of Computing Systems -- ARCS 2013 : 26th International Conference, Prague, Czech Republic, February 19-22, 2013 Proceedings / / edited by Hana Kubatova, Christian Hochberger, Martin Daněk, Bernhard Sick |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 |
| Descrizione fisica | 1 online resource (XIV, 354 p. 146 illus.) |
| Disciplina | 004.6 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Computer systems Operating systems (Computers) Software engineering Application software Information storage and retrieval systems Computer Communication Networks Computer System Implementation Operating Systems Software Engineering Computer and Information Systems Applications Information Storage and Retrieval |
| ISBN | 3-642-36424-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | An Unstructured Termination Detection Algorithm Using Gossip in Cloud Computing Environments -- Power Monitoring for Mixed-Criticality on a Many-Core Platform -- On Confident Task-Accurate Performance Estimation -- Exploiting Thermal Coupling Information in MPSoC Dynamic Thermal Management -- A Multi-core Memory Organization for 3-D DRAM as Main Memory -- Synthetic Aperture Radar Data Processing on an FPGA Multi-core System -- Virtual Register Renaming -- Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates -- Producer-Consumer: The Programming Model for Future Many-Core Processors -- A Highly Dependable Self-adaptive Mixed-Signal Multi-core System-on-Chip -- Inter-warp Instruction Temporal Locality in Deep-Multithreaded GPUs -- GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems -- HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN) -- A Data-Driven Approach for Executing the CG Method on Reconfigurable High-Performance Systems -- Custom Reconfigurable Architecture Based on Virtex 5 Lookup Tables -- Profiling Energy Consumption of I/O Functions in Embedded Applications -- An Application-Aware Cache Replacement Policy for Last-Level Caches -- Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory -- Self-adaptation for Mobile Robot Algorithms Using Organic Computing Principles -- Self-virtualized CAN Controller for Multi-core Processors in Real-Time Applications -- Shrinking L1 Instruction Caches to Improve Energy–Delay in SMT Embedded Processors -- Arithmetic Unit for Computations in GF(p) with the Left-Shifting Multiplicative Inverse Algorithm -- HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation -- Comparison of GPU and FPGA Implementation of SVM Algorithm for Fast Image Segmentation -- Automatic Floorplanning and Interface Synthesis of Island Style Reconfigurable Systems with GoAhead -- Separable 2D Convolution with Polymorphic Register Files -- Architecture of a Parallel MOSFET Parameter Extraction System -- Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets. |
| Record Nr. | UNINA-9910484547803321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Architecture of Computing Systems – ARCS 2019 [[electronic resource] ] : 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings / / edited by Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck
| Architecture of Computing Systems – ARCS 2019 [[electronic resource] ] : 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings / / edited by Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIX, 335 p. 212 illus., 88 illus. in color.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Operating systems (Computers) Logic design Computer systems Computer input-output equipment Microprocessors Computer architecture Computer Communication Networks Operating Systems Logic Design Computer System Implementation Input/Output and Data Communications Processor Architectures |
| ISBN | 3-030-18656-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Dependable Systems -- Hardware/Software Co-designed Security Extensions for Embedded Devices -- SDES - Scalable Software Support for Dependable Embedded Systems -- Real-Time Systems -- Asynchronous Critical Sections in Real-Time Multiprocessor Systems -- Resource-Aware Parameter Tuning for Real-Time Applications -- A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC -- Special Applications -- DSL-based Acceleration of Automotive Environment Perception and Mapping Algorithms for embedded CPUs, GPUs, and FPGAs -- Applying the Concept of Artificial DNA and Hormone System to a Low-Performance Automotive Environment -- A Parallel Adaptive Swarm Search Framework for Solving Black-Box Optimization Problems -- Architecture -- Leros: the Return of the Accumulator Machine -- A Generic Functional Simulation of Heterogeneous Systems -- Evaluating Dynamic Task Scheduling in a Task-based Runtime System for Heterogeneous Architectures -- Dynamic Scheduling of Pipelined Functional Units in Coarse-Grained Reconfigurable Array Elements -- Memory Hierarchy -- CyPhOS { A Component-based Cache-Aware Multi-Core Operating System -- Investigation of L2-Cache interferences in a NXP QorIQ T4240 multicore processor -- MEMPower: Data-Aware GPU Memory Power Model -- FPGA -- Effective FPGA Architecture for General CRC -- Receive-Side Notification for Enhanced RDMA in FPGA Based Networks -- An Efficient FPGA Accelerator Design for Optimized CNNs using OpenCL -- Energy Awareness -- The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures -- A Heterogeneous and Reconfigurable Embedded Architecture for Energy-efficient Execution of Convolutional Neural Networks -- An energy efficient embedded processor for hard real-time Java applications -- NoC/SoC -- A Minimal Network Interface for a Simple Network-on-Chip -- Network Coding in Networks-on-Chip with Lossy Links -- Application Specific Reconfigurable SoC Interconnection Network Architectures. |
| Record Nr. | UNISA-996466197103316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Architecture of Computing Systems – ARCS 2019 : 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings / / edited by Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck
| Architecture of Computing Systems – ARCS 2019 : 32nd International Conference, Copenhagen, Denmark, May 20–23, 2019, Proceedings / / edited by Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIX, 335 p. 212 illus., 88 illus. in color.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Operating systems (Computers) Logic design Computer systems Computer input-output equipment Microprocessors Computer architecture Computer Communication Networks Operating Systems Logic Design Computer System Implementation Input/Output and Data Communications Processor Architectures |
| ISBN | 3-030-18656-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Dependable Systems -- Hardware/Software Co-designed Security Extensions for Embedded Devices -- SDES - Scalable Software Support for Dependable Embedded Systems -- Real-Time Systems -- Asynchronous Critical Sections in Real-Time Multiprocessor Systems -- Resource-Aware Parameter Tuning for Real-Time Applications -- A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC -- Special Applications -- DSL-based Acceleration of Automotive Environment Perception and Mapping Algorithms for embedded CPUs, GPUs, and FPGAs -- Applying the Concept of Artificial DNA and Hormone System to a Low-Performance Automotive Environment -- A Parallel Adaptive Swarm Search Framework for Solving Black-Box Optimization Problems -- Architecture -- Leros: the Return of the Accumulator Machine -- A Generic Functional Simulation of Heterogeneous Systems -- Evaluating Dynamic Task Scheduling in a Task-based Runtime System for Heterogeneous Architectures -- Dynamic Scheduling of Pipelined Functional Units in Coarse-Grained Reconfigurable Array Elements -- Memory Hierarchy -- CyPhOS { A Component-based Cache-Aware Multi-Core Operating System -- Investigation of L2-Cache interferences in a NXP QorIQ T4240 multicore processor -- MEMPower: Data-Aware GPU Memory Power Model -- FPGA -- Effective FPGA Architecture for General CRC -- Receive-Side Notification for Enhanced RDMA in FPGA Based Networks -- An Efficient FPGA Accelerator Design for Optimized CNNs using OpenCL -- Energy Awareness -- The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures -- A Heterogeneous and Reconfigurable Embedded Architecture for Energy-efficient Execution of Convolutional Neural Networks -- An energy efficient embedded processor for hard real-time Java applications -- NoC/SoC -- A Minimal Network Interface for a Simple Network-on-Chip -- Network Coding in Networks-on-Chip with Lossy Links -- Application Specific Reconfigurable SoC Interconnection Network Architectures. |
| Record Nr. | UNINA-9910337841203321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Sixth International Workshop on FPGAs for Software Programmers (FSP 2019) : September 12, 2019, Barcelona, Spain co-located with International Conference on Field Programmable Logic and Applications (FPL)
| Sixth International Workshop on FPGAs for Software Programmers (FSP 2019) : September 12, 2019, Barcelona, Spain co-located with International Conference on Field Programmable Logic and Applications (FPL) |
| Edizione | [Neuerscheinung] |
| Pubbl/distr/stampa | Berlin, : VDE Verlag, 2019 |
| Descrizione fisica | Online-Ressource (70 S.) |
| Soggetto topico |
FPGA
Design Automation Hardware Acceleration High-Level Synthesis Reconfigurable Computing Software-Driven FPGA Developm System-on-Chip |
| ISBN | 3-8007-5046-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996581168003316 |
| Berlin, : VDE Verlag, 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
