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Complete Symbolic Simulation of SystemC Models : Efficient Formal Verification of Finite Non-Terminating Programs / / by Vladimir Herdt
Complete Symbolic Simulation of SystemC Models : Efficient Formal Verification of Finite Non-Terminating Programs / / by Vladimir Herdt
Autore Herdt Vladimir
Edizione [1st ed. 2016.]
Pubbl/distr/stampa Wiesbaden : , : Springer Fachmedien Wiesbaden : , : Imprint : Springer Vieweg, , 2016
Descrizione fisica 1 online resource (172 p.)
Disciplina 004
Collana BestMasters
Soggetto topico Computers
Software engineering
Computer science - Mathematics
Computer Hardware
Software Engineering
Mathematics of Computing
ISBN 3-658-12680-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Verification of Systems -- Introduction to Formal Verification of SystemC Models -- Symbolic Model Checking with Partial Order Reduction -- Efficient Symbolic State Matching using State Subsumption -- Heuristic Approaches for Symbolic State Matching -- Evaluation of Proposed Techniques.
Record Nr. UNINA-9910254990403321
Herdt Vladimir  
Wiesbaden : , : Springer Fachmedien Wiesbaden : , : Imprint : Springer Vieweg, , 2016
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Enhanced virtual prototyping : featuring RISC-V case studies / / Vladimir Herdt, Daniel Grosse, Rolf Drechsler
Enhanced virtual prototyping : featuring RISC-V case studies / / Vladimir Herdt, Daniel Grosse, Rolf Drechsler
Autore Herdt Vladimir
Pubbl/distr/stampa Cham, Switzerland : , : Springer, , [2021]
Descrizione fisica 1 online resource (XXI, 247 p. 90 illus., 75 illus. in color.)
Disciplina 005.3
Soggetto topico Computer engineering
Software prototyping
Electronic circuits
ISBN 3-030-54828-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- Preliminaries -- An Open-Source RISC-V Evaluation Platform -- Formal Verification of SystemC-based Designs using Symbolic Simulation -- Coverage-guided Testing for Scalable Virtual Prototype Verification -- Verification of Embedded Software Binaries using Virtual Prototypes -- Validation of Firmware-Based Power Management using Virtual Prototypes -- Register-Transfer Level Correspondence Analysis -- Conclusion -- Index.
Record Nr. UNINA-9910483638003321
Herdt Vladimir  
Cham, Switzerland : , : Springer, , [2021]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui