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Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping [[electronic resource] ] : Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31 - September 2, 1992. Selected Papers / / edited by Herbert Grünbacher, Reiner W. Hartenstein
| Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping [[electronic resource] ] : Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31 - September 2, 1992. Selected Papers / / edited by Herbert Grünbacher, Reiner W. Hartenstein |
| Edizione | [1st ed. 1993.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1993 |
| Descrizione fisica | 1 online resource (IX, 223 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Electronic circuits Logic design Electronics Microelectronics Computer System Implementation Circuits and Systems Logic Design Electronics and Microelectronics, Instrumentation |
| ISBN | 3-540-47902-3 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Overview of complex array-based PLDs -- Technologies and utilization of Field Programmable Gate Arrays -- Some considerations on Field Programmable Gate Arrays and their impact on system design -- SRAM-based FPGAs ease system verification -- MONTAGE: An FPGA for synchronous and asynchronous circuits -- ORCA: A new architecture for high-performance FPGAs -- Patching method for lookup-table type FPGA's -- Automatic one-hot re-encoding for FPGAs -- Minimization of permuted Reed-Muller Trees for cellular logic programmable Gate arrays -- Self-organizing Kohonen maps for FPGA placement -- High level synthesis in an FPGA-based computer aided prototyping environment -- New application of FPGAs to programmable digital communication circuits -- FPGA based logic synthesis of squarers using VHDL -- Optimized fuzzy controller architecture for field programmable gate arrays -- A real-time kernel — Rapid prototyping with VHDL and FPGAs -- JAPROC — A 8 bit micro controller design and its test environment -- Chameleon: A workstation of a different colour -- A highly parallel FPGA-based machine and its formal verification -- FPGA based self-test with deterministic test patterns -- FPGA implementation of systolic sequence alignment -- Using FPGAs to prototype a self-timed computer -- Using FPGAs to implement a reconfigurable highly parallel computer -- Novel high performance machine paradigms and fast-turnaround ASIC design methods: A consequence of, and, a challenge to, field-programmable logic. |
| Record Nr. | UNISA-996466153503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1993 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing [[electronic resource] ] : 10th International Conference, FPL 2000 Villach, Austria, August 27-30, 2000 Proceedings / / edited by Reiner W. Hartenstein, Herbert Grünbacher
| Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing [[electronic resource] ] : 10th International Conference, FPL 2000 Villach, Austria, August 27-30, 2000 Proceedings / / edited by Reiner W. Hartenstein, Herbert Grünbacher |
| Edizione | [1st ed. 2000.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2000 |
| Descrizione fisica | 1 online resource (XXXIV, 858 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Logic design Computer System Implementation Logic Design |
| ISBN | 3-540-44614-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Keynote -- Network Processors -- Prototyping -- Dynamically Reconfigurable I -- Miscellaneous I -- Technology Mapping and Routing & Placement -- Biologically Inspired Methods -- Invited Keynote -- Invited Papers -- Mobile Communication -- Dynamically Reconfigurable II -- Design Space Exploration -- Miscellaneous II -- Applications I -- Optimization -- Invited Keynote -- Invited Paper -- Architectures -- Methodology and Technology -- Compilation and Related Issues -- Applications II -- Short Papers. |
| Record Nr. | UNISA-996465372903316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2000 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing : 10th International Conference, FPL 2000 Villach, Austria, August 27-30, 2000 Proceedings / / edited by Reiner W. Hartenstein, Herbert Grünbacher
| Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing : 10th International Conference, FPL 2000 Villach, Austria, August 27-30, 2000 Proceedings / / edited by Reiner W. Hartenstein, Herbert Grünbacher |
| Edizione | [1st ed. 2000.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2000 |
| Descrizione fisica | 1 online resource (XXXIV, 858 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Logic design Computer System Implementation Logic Design |
| ISBN | 3-540-44614-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Keynote -- Network Processors -- Prototyping -- Dynamically Reconfigurable I -- Miscellaneous I -- Technology Mapping and Routing & Placement -- Biologically Inspired Methods -- Invited Keynote -- Invited Papers -- Mobile Communication -- Dynamically Reconfigurable II -- Design Space Exploration -- Miscellaneous II -- Applications I -- Optimization -- Invited Keynote -- Invited Paper -- Architectures -- Methodology and Technology -- Compilation and Related Issues -- Applications II -- Short Papers. |
| Record Nr. | UNINA-9910143621103321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2000 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Field-Programmable Logic, Smart Applications, New Paradigms and Compilers [[electronic resource] ] : 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, September 23 - 25, Proceedings / / edited by Reiner W. Hartenstein, Manfred Glesner
| Field-Programmable Logic, Smart Applications, New Paradigms and Compilers [[electronic resource] ] : 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, September 23 - 25, Proceedings / / edited by Reiner W. Hartenstein, Manfred Glesner |
| Edizione | [1st ed. 1996.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1996 |
| Descrizione fisica | 1 online resource (X, 436 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Logic design Microprocessors Computational complexity Computer-aided engineering Electronics Microelectronics Computer System Implementation Logic Design Register-Transfer-Level Implementation Complexity Computer-Aided Engineering (CAD, CAE) and Design Electronics and Microelectronics, Instrumentation |
| ISBN | 3-540-70670-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Portable pipeline synthesis for FCCMs -- Performance-directed technology mapping for LUT-based FPGAs — What role do decomposition and covering play? -- A framework for developing parametrised FPGA libraries -- FACT: Co-evaluation environment for FPGA architecture and CAD system -- An universal CLA adder generator for SRAM-based FPGAs -- An emulation system of the WASMII: A data driven computer on a virtual hardware -- Costum computing machines vs. Hardware/Software Co-Design: From a globalized point of view -- The design of a coprocessor board using Xilinx's XC6200 FPGA — An experience report -- RACE: Reconfigurable and adaptive computing environment -- Computing 2-D DFTs using FPGAs -- CAPpartx: Computer aided prototyping partitioning for Xilinx FPGAs, a hierarchical partitioning tool for rapid prototyping -- Architectural synthesis and efficient circuit implementation for field programmable gate arrays -- RaPiD — Reconfigurable pipelined datapath -- Solving satisfiability problems on FPGAs -- FPGA implementation of the block-matching algorithm for motion estimation in image coding -- Parallel CRC computation in FPGAs -- Coherent demodulation with FPGAs -- The Trianus system and its application to custom computing -- Logic synthesis for FPGAs using a mixed exclusive-/inclusive-OR form -- Flexible codesign target architecture for early prototyping of CMIST systems -- Attempt-1: A reconfigurable multiprocessor testbed -- A slow motion engine for the analysis of FPGA-based prototypes -- Implementing reconfigurable datapaths in FPGAs for adaptive filter design -- A fast constant coefficient multiplier for the XC6200 -- Key issues for user acceptance of FPGA design tools -- Reconfigurable DSP demonstrators for the development of spacecraft payload processors -- Reconfigurable logic based fibre channel network card with sub 2 ?s raw latency -- An asynchronous transfer mode (ATM) stream demultiplexer and switch -- Optically reconfigurable FPGAs: Is this a future trend? -- CCSimP — An instruction-level costum-configurable processor for FPLDs -- Architectural synthesis techniques for dynamically reconfigurable logic -- Fast reconfigurable crossbar switching in FPGAs -- Growable FPGA macro generator -- Architectural strategies for implementing an image processing algorithm on XC6000 FPGA -- A virtual hardware operating system for the Xilinx XC6200 -- An experimental programmable environment for prototyping digital circuits -- Migration from schematic-based designs to a VHDL synthesis environment -- ASIC design and FPGA design: A unified design methodology applied to different technologies -- FIR filtering with FPGAs using quadrature sigma-delta modulation encoding -- A new FPGA technology mapping approach by cluster merging -- An EPLD based transient recorder for simulation of video signal processing devices in a VHDL environment close to system level conditions -- Convolutional error decoding with FPGAs -- Metastability characteristics testing for programmable logic design -- Implementing ?? modulator prototype designs on an FPGA -- Design of a VME parameterized library for FPGAs -- Development of a telephone answering machine in a lab — FPGAs in Education -- FPGA design migration: Some remarks -- Concurrent design of hardware/software dedicated systems -- The implementation of a field programmable logic based co-processor for the acceleration of discrete event simulators -- Computing weight distributions of binary linear block codes on a CCM. |
| Record Nr. | UNISA-996465857503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1996 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Field-Programmable Logic: Architectures, Synthesis and Applications [[electronic resource] ] : 4th International Workshop on Field-Programmable Logic and Applications, FPL'94, Prague, Czech Republic, September 7 - 9, 1994. Proceedings / / edited by Reiner W. Hartenstein, Michal Z. Servit
| Field-Programmable Logic: Architectures, Synthesis and Applications [[electronic resource] ] : 4th International Workshop on Field-Programmable Logic and Applications, FPL'94, Prague, Czech Republic, September 7 - 9, 1994. Proceedings / / edited by Reiner W. Hartenstein, Michal Z. Servit |
| Edizione | [1st ed. 1994.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1994 |
| Descrizione fisica | 1 online resource (XIII, 439 p.) |
| Disciplina | 003.3 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Software engineering Logic design Electronics Microelectronics Computer-aided engineering Computer System Implementation Software Engineering/Programming and Operating Systems Logic Design Electronics and Microelectronics, Instrumentation Computer-Aided Engineering (CAD, CAE) and Design |
| ISBN | 3-540-48783-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Fault modeling and test generation for FPGAs -- A test methodology applied to Cellular logic Programmable Gate Arrays -- Integrated layout synthesis for FPGA's -- Influence of logic block layout architecture on FPGA performance -- A global routing heuristic for FPGAs based on mean field annealing -- Power dissipation driven FPGA place and route under delay constraints -- FPGA technology mapping for power minimization -- Specification and synthesis of complex arithmetic operators for FPGAs -- A speed-up technique for synchronous circuits realized as LUT-based FPGAs -- An efficient technique for mapping RTL structures onto FPGAs -- A testbench design method suitable for FPGA-based prototyping of reactive systems -- Using consensusless covers for fast operating on Boolean functions -- Formal verification of timing rules in design specifications -- Optimized synthesis of self-testable finite state machines (FSM) using BIST-PST structures in Altera structures -- A high-speed rotation processor -- The MD5 message-digest algorithm in the XILINX FPGA -- A reprogrammable processor for fractal image compression -- Implementing GCD systolic Arrays on FPGA -- Formal CAD techniques for safety-critical FPGA design and deployment in embedded subsystems -- Direct sequence spread spectrum digital Radio DSP prototyping using xilinx FPGAs -- FPGA based reconfigurable architecture for a compact vision system -- A new FPGA architecture for word-oriented datapaths -- Image processing on a custom computing platform -- A superscalar and reconfigurable processor -- A fast FPGA implementation of a general purpose neuron -- Data-procedural languages for FPL-based machines -- Implementing on line arithmetic on PAM -- Software environment for WASMII: A data driven machine with a virtual hardware -- Constraint-based hierarchical placement of parallel programs -- ZAREPTA: A zero lead-time, all reconfigurable system for emulation, prototyping and testing of ASICs -- Simulating static and dynamic faults in BIST structures with a FPGA based emulator -- FPGA based prototyping for verification and evaluation in hardware-software cosynthesis -- FPGA based low cost Generic Reusable Module for the rapid prototyping of subsystems -- FPGA development tools: Keeping pace with design complexity -- Meaningful benchmarks for logic optimization of table-lookup FPGAs -- Educational use of Field Programmable Gate Arrays -- Hardwire: A risk-free FPGA-to-ASIC migration path -- Reconfigurable hardware from programmable logic devices -- On some limits of XILINX based control logic implementations -- Experiences of using XBLOX for implementing a digital filter algorithm -- Continuous interconnect provides solution to density/performance trade-off in programmable logic -- A high density complex PLD family optimized for flexibility, predictability and 100% routability -- Design experience with fine-grained FPGAs -- FPGA routing structures from real circuits -- A tool-set for simulating altera-PLDs using VHDL -- A CAD tool for the development of an Extra-Fast Fuzzy Logic Controller based on FPGAs and memory modules -- Performance characteristics of the Monte-Carlo clustering processor (MCCP) - a field programmable logic based custom computing machine -- A Design Environment with Emulation of Prototypes for hardware/software systems using XILINX FPGA -- DSP development with full-speed prototyping based on HW/SW codesign techniques -- The architecture of a general-purpose processor cell -- The design of a stack-based microprocessor -- Implementation and performance evaluation of an image pre-processing chain on FPGA -- Signature testability of PLA -- A FPL prototyping package with a C++ interface for the PC bus -- Design of safety systems using Field Programmable Gate Arrays -- A job dispatcher-collector made of FPGA's for a centralized Voice Server -- An optoelectronic 3-D Field Programmable Gate Array -- On channel architecture and routability for FPGA's under faulty conditions -- High-performance datapath implementation on Field-Programmable Multi-Chip Module (FPMCM) -- A laboratory for a digital design course using FPGAs -- Coordinate Rotation DIgital Computer (CORDIC) synthesis for FPGA -- MARC: A Macintosh NUBUS-expansion board based reconfigurable test system for validating communication systems -- Artificial neural network implementation on a fine-grained FPGA. |
| Record Nr. | UNISA-996466128503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1994 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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