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Practical design verification / / edited by Dhiraj K. Pradhan, Ian G. Harris [[electronic resource]]
| Practical design verification / / edited by Dhiraj K. Pradhan, Ian G. Harris [[electronic resource]] |
| Pubbl/distr/stampa | Cambridge : , : Cambridge University Press, , 2009 |
| Descrizione fisica | 1 online resource (xi, 276 pages) : digital, PDF file(s) |
| Disciplina | 621.3815/48 |
| Soggetto topico | Integrated circuits - Verification |
| ISBN |
1-107-19643-4
1-282-39124-0 0-511-64683-6 9786612391248 0-511-62691-6 0-511-57932-2 0-511-65091-4 0-511-57858-X 0-511-58006-1 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva. |
| Record Nr. | UNINA-9910454505003321 |
| Cambridge : , : Cambridge University Press, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Practical design verification / / edited by Dhiraj K. Pradhan, Ian G. Harris [[electronic resource]]
| Practical design verification / / edited by Dhiraj K. Pradhan, Ian G. Harris [[electronic resource]] |
| Pubbl/distr/stampa | Cambridge : , : Cambridge University Press, , 2009 |
| Descrizione fisica | 1 online resource (xi, 276 pages) : digital, PDF file(s) |
| Disciplina | 621.3815/48 |
| Soggetto topico | Integrated circuits - Verification |
| ISBN |
1-107-19643-4
1-282-39124-0 0-511-64683-6 9786612391248 0-511-62691-6 0-511-57932-2 0-511-65091-4 0-511-57858-X 0-511-58006-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva. |
| Record Nr. | UNINA-9910777912103321 |
| Cambridge : , : Cambridge University Press, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||