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Cognitive radio receiver front-ends : RF/analog circuit techniques / / Bodhisatwa Sadhu, Ramesh Harjani
| Cognitive radio receiver front-ends : RF/analog circuit techniques / / Bodhisatwa Sadhu, Ramesh Harjani |
| Autore | Sadhu Bodhisatwa |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | New York : , : Springer, , 2014 |
| Descrizione fisica | 1 online resource (vi, 79 pages) : illustrations (chiefly color) |
| Disciplina | 621.381 |
| Collana | Analog Circuits and Signal Processing |
| Soggetto topico |
Radio frequency integrated circuits - Design and construction
Cognitive radio networks |
| ISBN | 1-4614-9296-3 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Cognitive Radio Architectures -- Wideband Voltage Controlled Oscillator -- RF Sampling and Signal Processing -- CRAFT: Charge Re-use Analog Fourier Transform -- Conclusions. |
| Record Nr. | UNINA-9910299495903321 |
Sadhu Bodhisatwa
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| New York : , : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Design of high-speed communication circuits [[electronic resource] /] / editor, Ramesh Harjani
| Design of high-speed communication circuits [[electronic resource] /] / editor, Ramesh Harjani |
| Pubbl/distr/stampa | New Jersey, : World Scientific, 2006 |
| Descrizione fisica | 1 online resource (232 p.) |
| Disciplina | 621.3192 |
| Altri autori (Persone) | HarjaniRamesh <1959-> |
| Collana | Selected topics in electronics and systems |
| Soggetto topico |
Electric circuits - Design and construction
Electrical engineering |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-37920-4
9786611379209 981-277-458-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
CONTENTS; Preface; Achieving Analog Accuracy in Nanometer CMOS; 1 Introduction; 2 Transistor Mismatch; 3 Methods of Achieving Yield; 4 Alternative Techniques for Nanometer CMOS; References; Self-Induced Noise in Integrated Circuits; 1 Introduction
2 Self-Induced Noise-Injection and Sensing Mechanisms 3 Extraction of Substrate Parasitics; 4 Conclusions; References; High-Speed Oversampling Analog-to-Digital Converters; 1 Introduction; 2 Single-Loop AE Modulator Topologies; 3 Time-Interleaved AE Modulators 4 Continuous-Time AE Modulators 5 Conclusions; References; Designing LC VCOs Using Capacitive Degeneration Techniques; 1 Introduction; 2 LC Tank-based VCO Design; 3 Design Examples; 4 Summary and Conclusions; Referencesntegrated Frequency Synthesizers: A Tutorial 1 Introduction 2 Interpreting Specifications; 3 Types of Frequency Synthesizers; 4 Phase Locked Loop (PLL) Design; 5 Recent Progress in Frequency Synthesizer Design Techniques; 6 Conclusion; References Recent Advances and Design Trends in CMOS Radio Frequency Integrated Circuits 1 Introduction; 2 Radio Receiver Architectures; 3 Low Noise Amplifiers; 4 Mixers; 5 Voltage-controlled Oscillators; References; Equalizers for High-Speed Serial Links ; 1 Introduction 2 Channel Modeling |
| Record Nr. | UNINA-9910458622503321 |
| New Jersey, : World Scientific, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design of high-speed communication circuits [[electronic resource] /] / editor, Ramesh Harjani
| Design of high-speed communication circuits [[electronic resource] /] / editor, Ramesh Harjani |
| Pubbl/distr/stampa | New Jersey, : World Scientific, 2006 |
| Descrizione fisica | 1 online resource (232 p.) |
| Disciplina | 621.3192 |
| Altri autori (Persone) | HarjaniRamesh <1959-> |
| Collana | Selected topics in electronics and systems |
| Soggetto topico |
Electric circuits - Design and construction
Electrical engineering |
| ISBN |
1-281-37920-4
9786611379209 981-277-458-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
CONTENTS; Preface; Achieving Analog Accuracy in Nanometer CMOS; 1 Introduction; 2 Transistor Mismatch; 3 Methods of Achieving Yield; 4 Alternative Techniques for Nanometer CMOS; References; Self-Induced Noise in Integrated Circuits; 1 Introduction
2 Self-Induced Noise-Injection and Sensing Mechanisms 3 Extraction of Substrate Parasitics; 4 Conclusions; References; High-Speed Oversampling Analog-to-Digital Converters; 1 Introduction; 2 Single-Loop AE Modulator Topologies; 3 Time-Interleaved AE Modulators 4 Continuous-Time AE Modulators 5 Conclusions; References; Designing LC VCOs Using Capacitive Degeneration Techniques; 1 Introduction; 2 LC Tank-based VCO Design; 3 Design Examples; 4 Summary and Conclusions; Referencesntegrated Frequency Synthesizers: A Tutorial 1 Introduction 2 Interpreting Specifications; 3 Types of Frequency Synthesizers; 4 Phase Locked Loop (PLL) Design; 5 Recent Progress in Frequency Synthesizer Design Techniques; 6 Conclusion; References Recent Advances and Design Trends in CMOS Radio Frequency Integrated Circuits 1 Introduction; 2 Radio Receiver Architectures; 3 Low Noise Amplifiers; 4 Mixers; 5 Voltage-controlled Oscillators; References; Equalizers for High-Speed Serial Links ; 1 Introduction 2 Channel Modeling |
| Record Nr. | UNINA-9910784755003321 |
| New Jersey, : World Scientific, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
High performance multi-channel high-speed I/O circuits / / Taehyoun Oh, Ramesh Harjani
| High performance multi-channel high-speed I/O circuits / / Taehyoun Oh, Ramesh Harjani |
| Autore | Oh Taehyoun |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | New York : , : Springer, , 2014 |
| Descrizione fisica | 1 online resource (x, 89 pages) : illustrations (some color) |
| Disciplina | 621.3822 |
| Collana | Analog Circuits and Signal Processing |
| Soggetto topico |
Signal processing
Electronic circuit design Electromagnetic interference - Prevention Crosstalk - Prevention |
| ISBN | 1-4614-4963-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process -- 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process -- Adaptive XTCR, AGC, and Adaptive DFE Loop -- Research Summary & Contributions -- References -- Appendix A: Noise Analysis -- Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os (≥ 4) -- Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter -- Appendix D: Line Mismatch Sensitivity -- Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench -- Appendix F: Bandwidth Improvement by Technology Scaling. |
| Record Nr. | UNINA-9910299745103321 |
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Oh Taehyoun
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| New York : , : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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