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Applied Reconfigurable Computing [[electronic resource] ] : 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings / / edited by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
Applied Reconfigurable Computing [[electronic resource] ] : 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings / / edited by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
Edizione [1st ed. 2015.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015
Descrizione fisica 1 online resource (XVIII, 557 p. 257 illus.)
Disciplina 004
Collana Theoretical Computer Science and General Issues
Soggetto topico Computers
Computer engineering
Computer networks
Algorithms
Artificial intelligence
Application software
Computer Hardware
Computer Engineering and Networks
Artificial Intelligence
Computer and Information Systems Applications
ISBN 3-319-16214-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Architecture and Modeling -- Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks -- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators -- Hierarchical Dynamic Power-Gating in FPGAs -- Tools and Compilers -- Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation -- ArchHDL: A Novel Hardware RTL Design Environment in C++ -- Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA -- Systems and Applications -- Preemptive Hardware Multitasking in ReconOS -- A Fully Parallel Particle Filter Architecture for FPGAs -- TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools -- Tools and Compilers -- Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures -- SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs -- Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties -- Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components -- Network-on-a-Chip Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays -- Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip -- Survey on Real-Time Network-on-Chip Architectures -- Cryptography Applications Efficient SR-Latch PUF -- Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study -- Dual CLEFIA/AES Cipher Core on FPGA -- Systems and Applications -- An Efficient and Flexible FPGA Implementation of a Face Detection System -- A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context -- A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank -- The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs -- Extended Abstracts (Posters) -- A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures -- Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA. -- A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware -- Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures -- Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects -- Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments -- DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems -- Acceleration of Data Streaming Classification Using Reconfigurable Technology -- On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach -- Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform -- A Challenge of Portable and High-Speed FPGA Accelerator -- Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array -- Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture -- Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization -- DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost -- A Flexible Multilayer Perceptron Co-processor for FPGAs -- Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs -- Towards Performance Modeling of 3D Memory Integrated FPGA Architectures -- Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL -- Special Session 1: Funded R&D Running and Completed Projects (Invited Papers) -- Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing -- SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms -- Hardware Task Scheduling for Partially Reconfigurable FPGAs -- SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring -- Special Session 2: Horizon 2020 Funded Projects (Invited Papers) -- DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications -- Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective -- Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach -- COSSIM : A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator.
Record Nr. UNISA-996200347303316
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Applied Reconfigurable Computing : 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings / / edited by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
Applied Reconfigurable Computing : 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings / / edited by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
Edizione [1st ed. 2015.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015
Descrizione fisica 1 online resource (XVIII, 557 p. 257 illus.)
Disciplina 004
Collana Theoretical Computer Science and General Issues
Soggetto topico Computers
Computer engineering
Computer networks
Algorithms
Artificial intelligence
Application software
Computer Hardware
Computer Engineering and Networks
Artificial Intelligence
Computer and Information Systems Applications
ISBN 3-319-16214-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Architecture and Modeling -- Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks -- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators -- Hierarchical Dynamic Power-Gating in FPGAs -- Tools and Compilers -- Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation -- ArchHDL: A Novel Hardware RTL Design Environment in C++ -- Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA -- Systems and Applications -- Preemptive Hardware Multitasking in ReconOS -- A Fully Parallel Particle Filter Architecture for FPGAs -- TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools -- Tools and Compilers -- Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures -- SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs -- Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties -- Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components -- Network-on-a-Chip Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays -- Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip -- Survey on Real-Time Network-on-Chip Architectures -- Cryptography Applications Efficient SR-Latch PUF -- Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study -- Dual CLEFIA/AES Cipher Core on FPGA -- Systems and Applications -- An Efficient and Flexible FPGA Implementation of a Face Detection System -- A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context -- A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank -- The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs -- Extended Abstracts (Posters) -- A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures -- Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA. -- A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware -- Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures -- Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects -- Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments -- DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems -- Acceleration of Data Streaming Classification Using Reconfigurable Technology -- On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach -- Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform -- A Challenge of Portable and High-Speed FPGA Accelerator -- Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array -- Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture -- Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization -- DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost -- A Flexible Multilayer Perceptron Co-processor for FPGAs -- Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs -- Towards Performance Modeling of 3D Memory Integrated FPGA Architectures -- Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL -- Special Session 1: Funded R&D Running and Completed Projects (Invited Papers) -- Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing -- SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms -- Hardware Task Scheduling for Partially Reconfigurable FPGAs -- SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring -- Special Session 2: Horizon 2020 Funded Projects (Invited Papers) -- DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications -- Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective -- Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach -- COSSIM : A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator.
Record Nr. UNINA-9910485011303321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Components and Services for IoT Platforms : Paving the Way for IoT Standards / / edited by Georgios Keramidas, Nikolaos Voros, Michael Hübner
Components and Services for IoT Platforms : Paving the Way for IoT Standards / / edited by Georgios Keramidas, Nikolaos Voros, Michael Hübner
Edizione [1st ed. 2017.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017
Descrizione fisica 1 online resource (IX, 383 p. 128 illus., 106 illus. in color.)
Disciplina 621.3815
Soggetto topico Electronic circuits
Electrical engineering
Application software
Circuits and Systems
Communications Engineering, Networks
Information Systems Applications (incl. Internet)
ISBN 3-319-42304-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Part I Platforms and Design Methodologies for IoT Hardware -- 1 -Shaping Configurable Micro-Processors for IoT Devices -- 2 Shaping Configurable Micro-Processors for IoT Devices -- 3 AXIOM a Flexible Platform for the Smart Home -- PArt II Simulation, Modeling and Programming Frameworks for IoT -- 4 Internet of Things Simulation using OMNeT++ and Hardware in the Loop -- 5 Towards Self-Adaptive IoT Applications: Requirements and Adaptivity Patterns for a Fall-Detection Ambient Assisting Living Application -- 6 Small Footprint JavaScript Engine -- 7 VirISA Recruiting Virtualization and Reconfigurable Processor ISA for Malicious Code Injection Protection -- Part III Opportunities, Challenges and Limits in WSN Deployment for IoT -- 8 Deployment Strategies of Wireless Sensor Networks for IoT: Challenges, Trends and Solutions Based on Novel Tools and HW/SW Platforms -- 9 Wireless Sensor Networks for the Internet of Things barriers and synergies -- 10 Event Identification in Wireless Sensor Networks -- Part IV Efficient Data Management and Decision Making for IoT -- 11 Integrating IoT and Fog Computing for Healthcare Service Delivery -- 12 Supporting Decision Making for Large-Scale IoTs: Trading Accuracy with Computational Complexity -- 13 Fuzzy Inference Systems Design Approaches for WSNs -- Part V Use Cases for IoT -- 14 IoT in Ambient Assistant Living Environments: A View from Europe -- 15 Software Design and Optimization of ECG Signal Analysis and Diagnosis for Embedded IoT Devices -- 16 Design for a System of Multimodal Interconnected ADL Recognition Services -- 17 IoT Components for Secure Smart Building Environments -- 18 Building Automation Systems in the World of Internet of Things.
Record Nr. UNINA-9910254173903321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Near Threshold Computing : Technology, Methods and Applications / / edited by Michael Hübner, Cristina Silvano
Near Threshold Computing : Technology, Methods and Applications / / edited by Michael Hübner, Cristina Silvano
Edizione [1st ed. 2016.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016
Descrizione fisica 1 online resource (104 p.)
Disciplina 620
Soggetto topico Electronic circuits
Microprocessors
Circuits and Systems
Processor Architectures
Electronic Circuits and Devices
ISBN 3-319-23389-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto PART I: NTC opportunities, challenges and limits -- Chapter 1: Extreme Energy Efficiency by Near Threshold Voltage Operation -- Part II Micro-architecture challenges and energy management at NTC -- Chapter2: Many-core Architecture for NTC: Energy Efficiency from the Ground Up -- Chapter 3: Variability-Aware Voltage Island Management for Near-Threshold Voltage Computing With Performance Guarantees -- Part III Memory system design for NTC -- Chapter4: Resizable Data Composer (RDC) Cache: A Near-Threshold Cache tolerating Process Variation Via architectural fault tolerance -- Chapter 5 Memories for NTC.
Record Nr. UNINA-9910254193103321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
System-Level Design Methodologies for Telecommunication / / edited by Nicolas Sklavos, Michael Hübner, Diana Goehringer, Paris Kitsos
System-Level Design Methodologies for Telecommunication / / edited by Nicolas Sklavos, Michael Hübner, Diana Goehringer, Paris Kitsos
Edizione [1st ed. 2014.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2014
Descrizione fisica 1 online resource (180 p.)
Disciplina 004.6
620
621.3815
621.382
Soggetto topico Electronic circuits
Electrical engineering
Computer organization
Circuits and Systems
Communications Engineering, Networks
Computer Systems Organization and Communication Networks
ISBN 3-319-00663-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Indoor Radio Design – LTE Perspective -- VLC technology for indoor LTE planning -- Voice over LTE (VoLTE) – Service Implementation & Cell Planning Perspective -- 60 GHz Millimeter-Wave WLANs & WPANs: Introduction, System Design, and PHY Layer Challenges -- Modeling the Operation of CMOS Primitive Circuits and MOSFET Devices -- From Hardware Security Tokens to Trusted Computing and Trusted Systems -- Using Codebender and Arduino in Science and Education -- The Internet of Things: How WSNs Fit Into the Picture -- Shape Analysis In Radiotherapy Tumor Surgical Planning Using Segmentation Techniques.
Record Nr. UNINA-9910299478503321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2014
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui