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Guide to computer processor architecture : a RISC-V approach, with high-level synthesis / / Bernard Goossens
| Guide to computer processor architecture : a RISC-V approach, with high-level synthesis / / Bernard Goossens |
| Autore | Goossens Bernard |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2023] |
| Descrizione fisica | 1 online resource (451 pages) |
| Disciplina | 929.605 |
| Collana | Undergraduate Topics in Computer Science |
| Soggetto topico | Computer architecture |
| ISBN |
9783031180231
9783031180224 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Part I. Single core processors -- 1. Getting Ready -- 2. Building a RISC-V Processor -- 3. Building a Pipelined RISC-V Processor -- 4. Building a RISC-V Processor with a Multi-cycle Pipeline -- 5. Building a RISC-V Processor with a Multiple Hart Pipeline -- Part II. Multiple core processors -- 6. Connecting IPs -- 7. A Multi-core RISC-V Processor -- 8. A Multi-core RISC-V Processor with Multi-hart Cores. |
| Record Nr. | UNINA-9910647389503321 |
Goossens Bernard
|
||
| Cham, Switzerland : , : Springer, , [2023] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Guide to computer processor architecture : a RISC-V approach, with high-level synthesis / / Bernard Goossens
| Guide to computer processor architecture : a RISC-V approach, with high-level synthesis / / Bernard Goossens |
| Autore | Goossens Bernard |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2023] |
| Descrizione fisica | 1 online resource (451 pages) |
| Disciplina | 929.605 |
| Collana | Undergraduate Topics in Computer Science |
| Soggetto topico | Computer architecture |
| ISBN |
9783031180231
9783031180224 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Part I. Single core processors -- 1. Getting Ready -- 2. Building a RISC-V Processor -- 3. Building a Pipelined RISC-V Processor -- 4. Building a RISC-V Processor with a Multi-cycle Pipeline -- 5. Building a RISC-V Processor with a Multiple Hart Pipeline -- Part II. Multiple core processors -- 6. Connecting IPs -- 7. A Multi-core RISC-V Processor -- 8. A Multi-core RISC-V Processor with Multi-hart Cores. |
| Record Nr. | UNISA-996546821303316 |
|
Goossens Bernard
|
||
| Cham, Switzerland : , : Springer, , [2023] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||